CN113590528A - Multi-channel data acquisition, storage and playback card, system and method based on HP interface - Google Patents

Abstract

The invention provides a multi-channel data acquisition, storage and playback card based on an HP interface, a system and a method, wherein the system comprises acquisition equipment, the acquisition, storage and playback card and a user terminal, the acquisition, storage and playback card comprises an FPGA unit and a storage unit, the FPGA unit comprises a programmable logic component and a processor system, the programmable logic component, the processor system and the storage unit are sequentially connected, the programmable logic component is connected with external acquisition equipment, an HP bus for transmitting data is arranged between the programmable logic component and the processor system, and the HP interface of each pair of programmable logic components and the HP interface of the processor system are mutually connected to form a first channel for transmitting acquired data or a second channel for transmitting played back data in the HP bus. The invention has higher integration level, is provided with a plurality of independent channels, can simultaneously acquire and playback data, can read and write high-speed data, and can play back the stored acquired data in various ways.

Description

Multi-channel data acquisition, storage and playback card, system and method based on HP interface

Technical Field

The invention relates to the field of data acquisition and playback, in particular to a multi-channel data acquisition, storage and playback card, a system and a method based on an HP interface.

Background

With the continuous development of digital information, massive data needs to be collected and analyzed in the aspects of radar, weather, communication and the like, and due to the fact that the data are large in quantity and multiple in types, the data are often required to be stored and then analyzed afterwards in order to make more comparisons and preserve states. In some scenes, the system function is complex, the equipment is various, a small-size and low-power consumption storage playback card needs to be equipped, and the existing storage scheme with the main board cannot meet the requirements due to large size and high power consumption.

As shown in fig. 1, the existing scheme includes a collection board card, a motherboard, and a disk, where the collection board card is responsible for collecting data, and transmits the data with an external device through an SRIO bus, the collected data is buffered through DDR3, then data interaction is performed through a PCIE bus and the motherboard, and finally the motherboard stores the data in the disk. The maximum collection rate of a single channel of a collection card under an SRIO bus is 2640MB/s, the maximum total data transmission rate of one PCIE bus is 8GB/s, and the size of a magnetic disk can be changed according to requirements. The existing scheme has two modes of playback, one mode is that disk data is directly read on a mainboard with an operating system, the other mode is that an upper computer issues a playback instruction, the data in the disk is transmitted to an acquisition card through a PCIE bus, and then the data is played back through an SRIO bus on the acquisition card.

This solution has three features: firstly, when one acquisition card is provided with a plurality of acquisition channels, data of the plurality of channels need to be combined and then packaged and uploaded in the PCIE transmission process, independent acquisition and storage of at most four channels can only be realized, the total acquisition rate is 8GB/s, the data need to be analyzed by an FPGA on a mainboard when being played back, and then the data are played back by channels, so that acquisition and playback cannot be carried out simultaneously; secondly, in order to realize simultaneous acquisition and playback, a plurality of acquisition boards can be mounted on one mainboard, namely, a plurality of PCIE buses are mounted on the mainboard, each bus is independent, and data of each acquisition card can be independently stored, but the requirement on the performance of the mainboard is higher in the case; thirdly, because a plurality of board cards are needed to realize the storage and playback functions in a cooperative manner, the system is large in size, high in power consumption and high in cost.

Disclosure of Invention

The technical problem to be solved by the invention is as follows: aiming at the technical problems in the prior art, the invention provides a multi-channel data acquisition, storage and playback card, a system and a method based on an HP interface, which have higher integration level, can simultaneously acquire and playback data in independent different channels, can simultaneously acquire and playback data in the same channel, can keep high-speed data reading and writing, and can access the stored acquired data in various ways.

In order to solve the technical problems, the technical scheme provided by the invention is as follows:

a multi-channel data acquisition, storage and playback card based on an HP interface comprises an FPGA unit and a storage unit, wherein the FPGA unit comprises a programmable logic assembly and a processor system, the programmable logic assembly is connected with the storage unit through the processor system, the programmable logic assembly is connected with external acquisition equipment, an HP bus used for transmitting data is arranged between the programmable logic assembly and the processor system, a first HP interface of the programmable logic assembly is in one-to-one correspondence with a second HP interface of the processor system, a part of the first HP interface is connected with the corresponding second HP interface to form a first channel used for transmitting acquired data in the HP bus, and a part of the first HP interface is connected with the corresponding second HP interface to form a second channel used for transmitting played back data.

Furthermore, the system also comprises a network connection unit, and the network connection unit, the processor system and the storage unit are sequentially connected to form a third channel for playing back the data in the storage unit.

The system comprises a programmable logic component and a processor system, and further comprises a first cache unit and a second cache unit, wherein the programmable logic component is connected with the first cache unit, so that data to be sent to the processor system or external acquisition equipment is cached, and the processor system is connected with the second cache unit, so that data to be sent to the programmable logic component or the storage unit is cached.

Further, the first cache unit and the second cache unit are respectively a DDR4 memory, the processor system includes a third cache unit and a fourth cache unit, and the DDR4 memory, the third cache unit, the fourth cache unit and the storage unit corresponding to the processor system are sequentially connected, so that the read-write speeds of the DDR4 memory and the storage unit corresponding to the processor system are matched.

The invention also provides a multichannel data acquisition, storage and playback system based on the HP interface, which comprises acquisition equipment, an acquisition, storage and playback card, a user terminal, playback equipment and an upper computer used for issuing acquisition and playback instructions, wherein the acquisition, storage and playback card is any one multichannel data acquisition, storage and playback card based on the HP interface, the acquisition equipment, the playback equipment and the upper computer are respectively connected with the acquisition, storage and playback card, the user terminal is connected with a network connection unit of the acquisition, storage and playback card, each first channel corresponds to at least one acquisition equipment, the acquisition equipment is connected with the corresponding first channel, each second channel corresponds to at least one playback equipment, and the playback equipment is connected with the corresponding second channel.

The invention also provides a multi-channel data acquisition, storage and playback method based on the HP interface, which is applied to the multi-channel data acquisition, storage and playback system based on the HP interface and specifically comprises the following steps:

s1) dividing the first cache unit to obtain a first cache space, dividing the second cache unit to obtain a second cache space, wherein the first cache space and the second cache space correspond to the channels in the HP bus one by one;

s2) the processor system of the FPGA unit receives the instruction of the upper computer through the programmable logic component, if the instruction is an acquisition instruction, the step S3) is skipped, and if the instruction is a playback instruction, the step S4) is skipped;

s3) selecting a first channel corresponding to the acquisition equipment in the HP bus, acquiring data from the acquisition equipment by the programmable logic component, caching the data in a corresponding first cache space, sending the cached data to the processor system through the corresponding first channel, caching the received data in a corresponding second cache space in a second cache unit by the processor system, configuring a corresponding folder in the storage unit, storing the cached data in the corresponding folder, and returning to the step S2);

s4) if the playback instruction specifies playback by the playback device, the processor system obtains data in the folder specified by the playback instruction from the storage unit 2, selects a second channel corresponding to the playback device in the HP bus, and caches the data in a corresponding second cache space, and then sends the cached data to the programmable logic module via the corresponding second channel, and the programmable logic module caches the received data in a first cache space corresponding to the second channel, and then sends the cached data to the playback device, and returns to step S2); if the playback instruction specifies playback through the user side, the processor system acquires the data in the folder specified by the playback instruction from the storage unit and sends the acquired data to the user side through the network connection unit, returning to step S2).

Further, step S1) is preceded by a step of updating the program online, which specifically includes:

A1) configuring storage and loading addresses of a G mirror image and an M mirror image in FLASH;

A2) the processor system of the FPGA unit receives the updating program sent by the user end through the network connection unit, analyzes and judges the data type, stores the data of the updating program in the second cache unit for verification, and writes the data of the updating program into the storage address of the M mirror image through a QSPI mode to update the M mirror image after the verification is passed;

A3) the processor system of the FPGA unit reads the data of the M mirror image from the storage address of the M mirror image and compares the data with the data in the second cache unit, and if the data are consistent, an update completion report is sent to the user side through the network connection unit;

A4) and the processor system of the FPGA unit loads the M mirror image according to the loading address of the M mirror image, if the M mirror image is loaded successfully, the M mirror image is operated, and otherwise, the G mirror image is loaded according to the loading address of the G mirror image and operated.

Further, the specific step of step S3) includes:

the processor system selects the channels in the HP bus as corresponding first channels according to the number of the acquisition devices, sends a write enable signal, a starting address of a second cache space and a single-time data transmission length to the programmable logic assembly, the programmable logic assembly generates a write instruction and sends the write instruction to the first cache unit after acquiring the write enable signal, waits for and acquires data transmitted by the acquisition devices, stores the data in the corresponding first cache space, sends the data stored in the first cache space to the corresponding starting address of the second cache space through the corresponding first channel for storage after the data size reaches the single-time data transmission length, sends the data to the processor system through the GP bus by the programmable logic assembly after the data size reaches the single-time data transmission length, and performs self-increment on the write address of the second cache space according to the data transmission size, and after receiving the interrupt signal, the processor system sends a write enable signal to the programmable logic component again through the GP bus, simultaneously sets folders corresponding to the acquisition equipment one by one in the storage unit, sets file attributes, and stores the data stored in the second cache space in the corresponding folders.

Further, the selecting, by the processor system, the channel in the HP bus as the corresponding first channel according to the number of the acquisition devices specifically includes: if the number of the acquisition equipment is less than or equal to the number of the channels in the HP bus, selecting one channel in the HP bus as a corresponding first channel for each acquisition equipment; if the number of the acquisition devices is larger than the number of the channels in the HP bus, grouping the acquisition devices after counting the data rates of all the acquisition devices, wherein the sum of the data rates of each group of the acquisition devices is smaller than or equal to the rate of a single channel in the HP bus, and configuring a channel in the HP bus as a corresponding first channel for each group of the acquisition devices.

Further, the acquisition device is connected with the acquisition storage playback card through an SRIO bus, and step S3) further includes a step of sending data according to priority, specifically including: if the single channel rate of the SRIO bus is smaller than the data rate input by the acquisition equipment, configuring the priority of each channel of the SRIO bus and sending the priority to the processor system, sending the priority to the programmable logic component by the processor system through the GP bus, and sequentially writing the data of each channel of the SRIO bus into the corresponding first cache space by the programmable logic component according to the sequence of the priorities from large to small;

or, if the single channel rate of the SRIO bus is less than the data rate input by the acquisition device, the acquisition device sequentially sends the corresponding data to the programmable logic assembly through the SRIO bus according to a preset priority and a descending order, and the programmable logic assembly sequentially writes each data into the corresponding first cache space.

Compared with the prior art, the invention has the advantages that:

1. in the acquisition, storage and playback card of the invention, an HP bus for transmitting data is arranged between the programmable logic component of the FPGA unit and the processor system, the first HP interfaces of the programmable logic component and the second HP interfaces of the processor system are in one-to-one correspondence, the first HP interfaces and the corresponding second HP interfaces are connected with each other to form a first channel used for transmitting acquired data or a second channel used for transmitting played back data in an HP bus, a plurality of mutually independent data transmission channels are provided, the work of storage after data channel analysis is omitted, the storage efficiency is improved, the error probability in the data transmission process is reduced, so that the acquisition data in the first channel and the playback data in the second channel can be transmitted in reverse simultaneously, meanwhile, each path of channel in the HP bus provides a transmission rate of up to 1200MB/s, so that high-speed data transmission under multiple channels is ensured;

2. the acquisition storage playback card is also provided with a network connection unit, the processor system and the storage unit are sequentially connected to form a third channel for playing back data in the storage unit, and files in the storage unit can be played back through the third channel, so that the acquisition data in the first channel and the playback data in the third channel can be simultaneously transmitted without mutual interference, and great convenience is brought to the operation of a user;

3. the acquisition, storage and playback card is provided with a cache unit for a programmable logic component and a processor system of an FPGA chip respectively, the cache unit adopts a DDR4 internal memory, has read-write frequency as high as 1600MHz/s, and simultaneously carries out control information transmission between the programmable logic component and the processor system through a GP bus, the transmission rate of each channel in the GP bus is as high as 500MB/s, thereby realizing data cache and high-speed transmission of control information under multiple channels;

4. in the data acquisition, storage and playback system, each first channel corresponds to at least one acquisition device, each second channel corresponds to at least one playback device, data of a plurality of acquisition devices can be received at the same time, and can also be sent to a plurality of playback devices for playback, and each first channel and each second channel are independent from each other, so that the work of storage after the data channels of a storage end are analyzed is omitted, the storage efficiency is improved, and the error probability in the data transmission process is reduced;

5. in the method, a first cache unit and a second cache unit are divided into a first cache space and a second cache space according to the number of channels of an HP bus, and a folder corresponding to acquisition equipment is also arranged in a storage unit, so that for each acquisition equipment, the HP bus has a corresponding first channel for transmitting data, the first cache unit and the second cache unit have independent cache spaces, and the storage unit has independent storage spaces, so that data management is facilitated; meanwhile, according to a playback mode designated by the playback instruction, the method can acquire data through the acquisition equipment and directly read the data in the storage unit by the network connection unit to acquire and playback the data at the same time, and can acquire the data through the acquisition equipment and play back the data through the playback equipment to acquire and playback the data in different channels at the same time, so that the data acquisition and the data playback are realized in two modes at the same time.

Drawings

Fig. 1 is a block diagram of a conventional acquisition, storage and playback system.

Fig. 2 is a block diagram of an acquisition storage playback system according to an embodiment of the present invention.

FIG. 3 is a diagram illustrating a method for partitioning spaces of a first buffer unit and a second buffer unit according to an embodiment of the present invention.

Illustration of the drawings: the system comprises a Field Programmable Gate Array (FPGA) unit 1, a storage unit 2, a network connection unit 3, a first cache unit 4, a second cache unit 5, a third cache unit 6, a fourth cache unit 7, a collection device 101, a user terminal 102, a playback device 103 and an upper computer 104.

Detailed Description

The invention is further described below with reference to the drawings and specific preferred embodiments of the description, without thereby limiting the scope of protection of the invention.

Zynq UltraScale series of a new generation dual-core ARM + FPGA processor based on 16nm process of XILINX company comprises user programmable logic PL (programmable logic) (PL end) and processor system PS (processSytem) (PS end), wherein the processor system core mainly adopts ARM flagship product and comprises 64 bits

Dual-core processor and

the main frequency of the dual-core processor is up to 1.5GHz, different power consumption and performance requirements can be configured, the number of high-speed banks is large, a plurality of high-speed interfaces can be configured, logic resources are huge, and field programming is convenient for application and development of different requirements.

As shown in fig. 2, based on the FPGA chip, the present invention provides a multi-channel data acquisition, storage and playback card based on an HP interface, including an FPGA unit 1, a first buffer unit 4, a second buffer unit 5, a storage unit 2, and a network connection unit 3, where the FPGA unit 1 includes a PL end and a PS end, the PL end is connected to the storage unit 2 through the PS end, the PL end is connected to an external acquisition device, an HP bus for transmitting data is provided between the PL end and the PS end, the HP bus is an important data channel of a Zynq chip, is an AXI3.0(advanced extensible interface) standard interface with high performance/bandwidth, and is mainly used for the PL end to access a DDR register (DDR or on-chcip RAM) on the PS end, the rate is up to 1200MB/s, the first HP interface of the PL end and the second HP interface of the PS end are in one-to-one correspondence, and part of the first HP interface and the corresponding second HP interface are connected to form a first channel for transmitting acquired data in the HP bus, in the FPGA unit 1, the channels in the HP bus comprise at least one first channel for transmitting the acquired data and at least one second channel for transmitting the played back data, so that a plurality of mutually independent data transmission channels are provided, the work of analyzing and storing the data channels is omitted, the storage efficiency is improved, the error probability in the data transmission process is reduced, the acquired data in the first channel and the played back data in the second channel can be simultaneously and reversely transmitted, and each channel in the HP bus provides a transmission rate of up to 1200MB/s, so that the high-speed transmission of the data under multiple channels is ensured.

In this embodiment, the network connection unit 3 is configured to receive an external instruction and send the external instruction to the FPGA unit 1 or derive data of the storage unit 2, so that the storage unit 2, the PS terminal, and the network connection unit 3, which are sequentially connected, form a third channel for playing back data in the storage unit 2, and a file in the storage unit 2 can be played back through the third channel, so that the acquired data in the first channel and the played back data in the third channel can be transmitted simultaneously without interference, which is greatly convenient for a user to operate.

As shown in fig. 2, a GP bus for transmitting control information is arranged between a PL end and a PS end, the GP bus is a general axi (advanced extensible interface) interface, a transmission rate of each channel in the GP bus is as high as 500MB/s, a channel for transmitting control information at a high speed is provided, a first GP interface of the PL end and a second GP interface of the PS end are in one-to-one correspondence, a fourth channel formed by connecting the first GP interface and the corresponding second GP interface and used for exchanging control information is a channel in the GP bus, the PL end is connected with a first buffer unit 4, so that data to be sent to the PS end or external acquisition equipment is buffered, and the PS end is connected with a second buffer unit 5, so that data to be sent to the PL end or the storage unit 2 is buffered.

As shown in fig. 2, the PL end in this embodiment is provided with a high-speed data transmission interface such as an SRIO interface, an Aurora interface, or a gigabit network interface, and is connected to an external acquisition device through the SRIO interface, the Aurora interface, or the gigabit network interface. In the embodiment, the SRIO interface is adopted, and the SRIO protocol can select five speeds of 1.25Gbps, 2.5Gbps, 3.125Gbps, 5Gbps and 6.25Gbps to meet different application requirements.

In this embodiment, the HP interface-based multi-channel data acquisition, storage and playback card and external equipment may be connected by an optical fiber or a VPX backplane, and under the condition of optical fiber connection, the playback card in this embodiment further includes a photoelectric conversion module, the SRIO interface at the PL end is connected with external acquisition equipment by the photoelectric conversion module, the photoelectric conversion module is used for connecting an optical fiber, acquiring acquired data from the optical fiber, and sending the acquired data to the storage unit 2 for data acquisition and storage by the FPGA unit 1, or playing back data from the FPGA unit 1 by the optical fiber.

As shown in fig. 2, the first cache unit 4 and the second cache unit 5 in this embodiment are DDR4 memories respectively, the DDR4 memory corresponding to the PL port, the HP interface of the PS port, and the DDR4 memory corresponding to the PL port are connected in sequence, and the read-write frequency of the DDR4 memory is up to 1600MHZ/s, which can implement high-speed caching and transmission of data during acquisition and playback.

The storage unit 2 in this embodiment is an SATA hard disk, which is mounted on the PS end and used to store the acquired data, and the capacity can be selected as needed. As shown in fig. 2, the PS end in this embodiment includes a third cache unit 6 and a fourth cache unit 7, the DDR4 memory, the third cache unit 6, the fourth cache unit 7 and the storage unit 2 corresponding to the PS end are sequentially connected, because the data is read from the DDR4 at a high speed, and is written into the SATA hard disk at a low speed, and by adding the third cache unit 6 and the fourth cache unit 7, the read-write speeds of the DDR4 memory and the storage unit 2 corresponding to the PS end can be matched, so that efficient storage of data is achieved. In this embodiment, the third cache unit 6 and the fourth cache unit 7 correspond to cache blocks in two areas, namely, a kernel space and a user space, inside the PS end, respectively, and the kernel space and the user space have three levels of caches, and after the PS end takes out data from the DDR4, the data is placed in the kernel space first through DMA (automatic operation) and then is carried to the user space, so that automatic disk writing is realized. In the process, the kernel can perform other operations, so that the operation efficiency of the system is not influenced.

As shown in fig. 2, this embodiment further provides a multichannel data acquisition, storage and playback system based on an HP interface, which includes an acquisition device 101, an acquisition, storage and playback card, a user terminal 102, a playback device 103, and an upper computer 104 for issuing acquisition and playback instructions, where the acquisition, storage and playback card is any one of the above multichannel data acquisition, storage and playback cards based on an HP interface, the acquisition device 101, the playback device 103, and the upper computer 104 are connected with the acquisition, storage and playback card through an optical fiber or a VPX backplane, respectively, the user terminal 102 is connected with a network connection unit 3 of the acquisition, storage and playback card through a gigabit network, the acquisition, storage and playback card includes at least one first channel and at least one second channel, each first channel corresponds to at least one acquisition device 101, each second channel corresponds to at least one playback device 103, and the acquisition device 101 is connected with the corresponding first channel, the playback devices 103 are connected with the corresponding second channels, so that the system in this embodiment can simultaneously receive data of the multiple acquisition devices 101 and simultaneously play back the data to the multiple playback devices 103, so that data acquisition and playback of different channels are simultaneously performed, and each first channel and each second channel are independent of each other, thereby reducing the probability of errors in the transmission process of data in the FPGA unit 1, saving the work of storage after data channel analysis, and improving the storage efficiency; meanwhile, the system in this embodiment may also receive data of multiple pieces of acquisition equipment 101 at the same time, and replay the acquired data to the user terminal 102 through the network connection unit 3 via the third channel after storing the data, so that the acquisition and the replay of the data are performed simultaneously without interference, which is greatly convenient for the user to operate.

The embodiment further provides a multi-channel data acquisition, storage and playback method based on an HP interface, which is applied to the multi-channel data acquisition, storage and playback system based on the HP interface, and specifically includes the following steps:

s1) dividing the first buffer unit 4 to obtain a first buffer space and dividing the second buffer unit 5 to obtain a second buffer space according to the number of the channels in the HP bus, as shown in fig. 3, each channel in the HP bus corresponds to a segment of buffer address in the first buffer unit 4 and the second buffer unit 5, and when inputting and outputting data, the corresponding address space is operated, so as to omit the subsequent data path analysis, because the DDR4 can only execute the write or read of one channel at a time, the size of write or read at a time can be set, and the size of read and write can be adjusted once according to the requirement to improve the path efficiency, in this embodiment, buffer FIFOs are added before and after the DDR4 memory, and a ping-pong method is used to write or read data into the DDR4 memory;

s2) the PS end of the FPGA unit 1 receives the instruction of the upper computer 104 through the PL end, if the instruction is an acquisition instruction, the step S3) is skipped, and if the instruction is a playback instruction, the step S4) is skipped;

s3) selecting a first channel corresponding to the acquisition device 101 in the HP bus, the PL side obtaining data from the acquisition device 101, caching the data in a first cache space corresponding to the first cache unit 4, then sending the cached data to the PS side through the corresponding first channel, the PS side caching the received data in a second cache space corresponding to the second cache unit 5, then configuring a folder corresponding to the acquisition device 101 in the storage unit 2 and storing the cached data in the corresponding folder, and returning to step S2);

s4) if the playback instruction specifies playback by the playback device 103, the PS side obtains data in the folder specified by the playback instruction from the storage unit 2, selects a second channel corresponding to the playback device 103 in the HP bus, and caches the data in a corresponding second cache space, and then sends the cached data to the PL side via the corresponding second channel, and the PL side caches the received data in a first cache space corresponding to the second channel, and then sends the cached data to the playback device 103, and returns to step S2); if the playback instruction specifies playback by the user terminal 102, the PS terminal acquires the data in the folder specified by the playback instruction from the storage unit 2 and sends the acquired data to the user terminal 102 via the network connection unit 3, returning to step S2).

In step S1) of this embodiment, since the read/write rate of the front and back end data is interrupted, the collected and played back data need to be buffered by the DDR4 at the PL end, i.e. the first buffer unit 4, and the DDR4 at the PS end, i.e. the second buffer unit 5, before being stored or played back. According to the number of data channels used for collection in the HP bus, the space of the PL terminal DDR4 is divided to obtain first cache spaces, the number of the first cache spaces is larger than or equal to the number of the data channels used for collection, the specific dividing number can be set according to actual requirements, the number of the data channels used for collection is more, and the number of cache data in each first cache space is less.

For the PL side and the PS side of the FPGA unit 1 in this embodiment, the data output by the DDR4 is sent to the HP bus interface, the DDR4 address of the PS side is mapped to the HP bus interface, and the PL side directly writes the data into the DDR4 of the PS side. According to the number of the actual channels for acquisition and playback in the HP bus, space division is carried out on the PS end DDR4 to obtain a second cache space, the number of the actually divided second cache space is the sum of the number of the channels for acquisition and playback, the PS end is provided with a DDR4 Control controller and manages the read-write of the DDR4, and the number of the channels and the one-to-one correspondence relationship between the channels and the divided space are set in an application layer. PL end data is directly written into DDR4 Control through an HP bus, the DDR4 Control judges the current read-write state and returns a command to an application layer, and the application layer realizes the Control of the HP read-write command.

The GP interface provides a channel for control information and state interaction between the PL and the PS. After power-on, the PS end sends a write enable signal, a DDR4 initial address and a single-time data transmission length, after the PL end receives the write enable signal, a DDR4 address writing instruction is sent first, data acquisition is waited for, if data exist in a DDR4 cache space of the PL end, the data with burst length is transmitted once through an HP bus interface, interruption is sent and completed after transmission is completed, the write address is self-increased according to the size of the transmitted data, the PS end receives the interruption, one-time transmission is completed, then the PS sends the write enable signal again, next-time data transmission is started, meanwhile, the data stored in the DDR4 of the PS end are carried step by step through a kernel space and a user space, and then the data are written into a Sata disk.

Therefore, the specific step of step S3) of the present embodiment includes: the PS terminal selects the channels in the HP bus as corresponding first channels according to the number of the acquisition devices 101, as the first cache space, the second cache space and the channels in the HP bus are in one-to-one correspondence, the acquisition devices 101 have corresponding first channels, corresponding first cache spaces and corresponding second cache spaces, a write enable signal, a start address of the second cache space and a single data transmission length are sent to the PL terminal, the PL terminal generates a write instruction after acquiring the write enable signal and sends the write instruction to the first cache unit 4 to wait and acquire the data transmitted by the acquisition devices 101, the data are stored in the first cache space corresponding to the acquisition devices 101, and the data stored in the first cache space are sent to the start address of the corresponding second cache space in the second cache unit 5 through the corresponding first channels to be stored after reaching a threshold value, after the size of the sent data reaches the length of single transmission data, the PL terminal sends a complete interrupt to the PS terminal through the GP bus, self-increases the write address of the second cache space according to the size of the transmitted data, after receiving the interrupt signal, the PS terminal sends a write enable signal to the PL terminal again through the GP bus, simultaneously, the storage unit 2 is provided with folders which are in one-to-one correspondence with the acquisition equipment 101, and file attributes are set, and the data stored in the second cache space is stored in the corresponding folders.

Step S3) of this embodiment, if there are too many collection devices 101 and the data rate of each collection device 101 is low, it may be considered to combine several of them into one channel of the HP bus. A single HP bus channel may be split into independent sub-channels, and when a back-end disk is saved, files are separately stored according to each sub-channel, that is, collected data are respectively stored for different collection devices 101, but the total transmission rate of the combined collection devices 101 is up to 1200MB/s, so that the selection of the channel in the HP bus as the corresponding first channel by the PS terminal according to the number of the collection devices 101 specifically includes: if the number of the acquisition devices 101 is less than or equal to the number of the channels in the HP bus, selecting one channel in the HP bus as a corresponding first channel for each acquisition device 101; if the number of the acquisition devices 101 is greater than the number of the channels in the HP bus, the data rates of all the acquisition devices 101 are counted and grouped, the sum of the data rates of each group of the acquisition devices 101 is less than or equal to the rate of a single channel in the HP bus, and a channel in the HP bus is configured for each group of the acquisition devices 101 to serve as a corresponding first channel.

Similarly, the step S4) of selecting the second channel corresponding to the playback device 103 in the HP bus is also that the PS selects the channel in the HP bus as the corresponding second channel according to the number of the playback devices 103, and specifically includes: if the number of the playback devices 103 is less than or equal to the number of the channels in the HP bus, selecting a channel in the HP bus as a corresponding second channel for each playback device 103; if the number of the playback devices 103 is greater than the number of channels in the HP bus, grouping is performed after counting the data rates of all the playback devices 103, the sum of the data rates of each group of playback devices 103 is less than or equal to the rate of a single channel in the HP bus, and a channel in the HP bus is configured as a corresponding second channel for each group of playback devices 103.

In this embodiment, the SRIO bus supports priority control, and may directly define the priority of each channel in the SRIO bus, thereby ensuring that data of the main channel is stored. The single channel rate of the SRIO bus can reach 6.25Gbs, according to the application requirement, if the input data rate is greater than the highest rate of the channel in the SRIO bus, the data storage priority of the channel of the SRIO bus needs to be controlled, and the control mode can be directly controlled through input of the acquisition equipment or a channel priority instruction is received.

Therefore, step S3) in this embodiment further includes a step of sending data according to the priority, which specifically includes: if the rate of a single channel of the SRIO bus is less than the data rate input by the acquisition device 101, configuring the priority of each channel of the SRIO bus and sending the priority to the PS terminal, where the PS terminal sends the priority to the PL terminal through the GP bus, and the PL terminal sequentially writes the data of each channel of the SRIO bus into a first cache space corresponding to the acquisition device 101 in the first cache unit 4 according to the sequence of the priorities from large to small;

or, if the single channel rate of the SRIO bus is less than the data rate input by the acquisition device 101, the acquisition device 101 sequentially sends corresponding data to the PL end through the SRIO bus according to a preset priority and in a descending order, and the PL end sequentially writes each data into the first cache space corresponding to the acquisition device 101 in the first cache unit 4.

In this embodiment, the channels in the acquisition device 101, the playback device 103, and the SRIO bus are in one-to-one correspondence, and the first cache space in the PL side DDR4 may be switched by a circular proximity switching method, so that the channels in the SRIO bus to which the external device and the acquisition and playback board card are connected can simultaneously perform data acquisition and playback operations. In an initial state, the default is an acquisition mode, and a first cache space and a corresponding channel in an HP bus are selected as a first channel to realize data acquisition and cache at the same time; when a playback instruction is issued, whether a free first cache space exists at present is monitored, if yes, a channel in the HP bus corresponding to the free first cache space serves as a second channel, meanwhile, data is cached through the free first cache space, and then the data is played back to the playback device 103 through a channel number corresponding to the playback device 103 in the SRIO bus.

In the cyclic near switching method in this embodiment, each channel in the SRIO bus and the first buffer space in the PL side DDR4 are numbered from 0, and the specific control process is as follows:

1. defaulting to an idle mode, wherein all first cache spaces are idle;

2. in the acquisition mode, acquiring a channel number in an SRIO bus corresponding to the device 101, and selecting a first cache space with the number greater than or equal to the number as a corresponding cache space; if the first cache spaces with the numbers larger than or equal to the numbers are in a busy state, selecting the first cache space which is free and has the smallest number as the corresponding cache space;

3. in a playback mode, the PL terminal detects a first cache space in an idle state, and searches for the first cache space with a serial number larger than a channel serial number in an SRIO bus corresponding to the current playback equipment 103 and a smallest difference value between the serial number and the first cache space as a corresponding cache space; if the first cache spaces with the numbers larger than the channel numbers in the SRIO bus corresponding to the current playback device 103 are all in a busy state, selecting the first cache space with the idle number and the minimum number as the corresponding cache space;

4. if the first buffer space is not free during acquisition, stopping the first buffer space with the lowest priority for playback;

5. the priority of the first buffer space is gradually decreased from number 0.

In this embodiment, there are two playback modes, the first mode is that in step S4), when the playback device 103 is specified to perform playback, the upper computer 104 or other external interfaces send a playback instruction, the PS end selects a channel in the HP bus as a corresponding second channel according to the number of the playback devices 103, and specifies data to be played back, the PS end reads a corresponding folder in the Sata disc to obtain the data to be played back, and sends the data to the playback device 103 through the corresponding second channel for playback. In the second case, as in step S4), when the user end 102 is specified to perform playback, the user end 102 connects the acquisition storage playback card through the gigabit network, and can access the SATA hard disk for data playback through three modes, i.e., the browser IP access mode, the NAS network disk shared unloading mode mount mode, or the upper computer mode. The two modes can realize simultaneous acquisition and playback without mutual interference, and great convenience is brought to the operation of a user.

In this embodiment, Flash is further provided on the HP interface-based multi-channel data acquisition, storage and playback, and an online update function is also provided. By combining the complexity and confidentiality of the board application scene, the online program updating function is required for batch equipment. It uses a Multiboot method. According to the method, a plurality of images can be stored in the same Flash according to requirements. The scheme uses two mirrors, namely a G mirror and an M mirror. The G image is used as a permanent image and stored in a base address, and is never erased actively. And erasing and replacing the M mirror image in the Flash when the program is updated every time. After electrification, the FPGA loads the M mirror image, after configuration is completed, if the configuration is successful, the M mirror image is operated, and if the configuration is failed, the G mirror image is reloaded. The method avoids that when the updating fails or the loading fails due to reasons such as power failure, the FPGA can still automatically realize the active loading of the program from the G mirror image, thereby ensuring the normal work of the system and simultaneously requesting the secondary updating of the program. In the invention, a multi-mirror loading mode is firstly configured, the storage and loading addresses of the M mirror are preset, and the M mirror is configured to be loaded preferentially. A user can transmit a program needing to be updated to a PS (packet switched) end through a client or a gigabit network, the PS end analyzes and judges the data type, then checks the data in DDR4, writes the data into an address designated by Flash in a QSPI (quad Small form-factor pluggable) mode after the check is passed, reads the content of the Flash after the programming is finished, compares the content with the data in DDR4 again, and uploads an update finishing instruction after the Flash is correct.

Therefore, step S1) is preceded by a step of updating the program online, which specifically includes:

A1) configuring storage and loading addresses of a G mirror image and an M mirror image in FLASH;

A2) the PS end of the FPGA unit 1 receives the updating program sent by the user end 102 through the network connection unit 3, analyzes and judges the data type, stores the data of the updating program in a second cache unit (5) for verification, and writes the data of the updating program into the storage address of the M mirror image through a QSPI mode to update the M mirror image after the verification is passed;

A3) the PS terminal of the FPGA unit 1 reads the data of the M mirror image from the storage address of the M mirror image and compares the data with the data in the second cache unit 5, and if the data are consistent, an update completion report is sent to the user terminal 102 through the network connection unit 3;

A4) and the PS end of the FPGA unit 1 loads the M mirror image according to the loading address of the M mirror image, if the loading is successful, the M mirror image is operated, and otherwise, the G mirror image is loaded according to the loading address of the G mirror image and operated.

In this embodiment, the PS end of the FPGA unit 1 runs a linux operating system, runs a standard Sata protocol, sets file attributes, reads and writes a Sata disk, and data acquired by each channel is stored in a respective folder, so that a user can manually set the size of a file to be stored each time, thereby realizing continuous storage of data at different times in the same file, and facilitating file management. Meanwhile, corresponding upper computer software is adopted in the embodiment, so that the channel acquisition enabling and priority can be controlled, and the state of the acquisition and storage board card can be monitored. Through embedding linux operating system, realize the humanized management to the sata file, the user can pass through the network, realize with different operating system's connection, the user can be through the remote control mode, operate host computer software, realize gathering, instruction operation such as playback, in addition can be at the manual single or the circulation playback that sets up different files of host computer, and set for the passageway of playback, the route of playback, the file of the different time quantum collection of playback, bring very big facility for practical application.

The foregoing is considered as illustrative of the preferred embodiments of the invention and is not to be construed as limiting the invention in any way. Although the present invention has been described with reference to the preferred embodiments, it is not intended to be limited thereto. Therefore, any simple modification, equivalent change and modification made to the above embodiments according to the technical spirit of the present invention should fall within the protection scope of the technical scheme of the present invention, unless the technical spirit of the present invention departs from the content of the technical scheme of the present invention.

Claims (10)

1. The multi-channel data acquisition, storage and playback card based on the HP interface is characterized by comprising an FPGA unit (1) and a storage unit (2), wherein the FPGA unit (1) comprises a programmable logic component and a processor system, the programmable logic component is connected with the storage unit (2) through the processor system, the programmable logic component is further connected with external acquisition equipment, an HP bus used for transmitting data is arranged between the programmable logic component and the processor system, a first HP interface of the programmable logic component is in one-to-one correspondence with a second HP interface of the processor system, a part of the first HP interfaces and the corresponding second HP interfaces are connected to form a first channel used for transmitting acquired data in the HP bus, and a part of the first HP interfaces and the corresponding second HP interfaces are connected to form a second channel used for transmitting played back data.

2. The HP interface-based multi-channel data acquisition, storage and playback card according to claim 1, further comprising a network connection unit (3), wherein the network connection unit (3), the processor system and the storage unit (2) are sequentially connected to form a third channel for playing back data in the storage unit (2).

3. The HP interface-based multi-channel data acquisition, storage and playback card according to claim 1, further comprising a first buffer unit (4) and a second buffer unit (5), wherein the programmable logic component is connected to the first buffer unit (4) so that data to be sent to the processor system or an external acquisition device is buffered, and the processor system is connected to the second buffer unit (5) so that data to be sent to the programmable logic component or the storage unit (2) is buffered.

4. The HP interface-based multi-channel data acquisition, storage and playback card according to claim 3, wherein the first cache unit (4) and the second cache unit (5) are DDR4 memories, the processor system includes a third cache unit (6) and a fourth cache unit (7), and the DDR4 memory, the third cache unit (6), the fourth cache unit (7) and the storage unit (2) corresponding to the processor system are connected in sequence, so that the read-write speeds of the DDR4 memory and the storage unit (2) corresponding to the processor system are matched.

5. A multi-channel data acquisition, storage and playback system based on an HP interface is characterized by comprising acquisition equipment (101), an acquisition, storage and playback card, a user terminal (102), playback equipment (103) and an upper computer (104) used for issuing acquisition and playback instructions, wherein the acquisition, storage and playback card is the multi-channel data acquisition, storage and playback card based on the HP interface according to any one of claims 1 to 4, the acquisition equipment (101), the playback equipment (103) and the upper computer (104) are respectively connected with the acquisition, storage and playback card, the user terminal (102) is connected with a network connection unit (3) of the acquisition, storage and playback card, each first channel respectively corresponds to at least one acquisition equipment (101), the acquisition equipment (101) is connected with the corresponding first channel through a programmable logic component, each second channel respectively corresponds to at least one playback equipment (103), the playback device (103) is connected with the corresponding second channel through a programmable logic component.

6. A multi-channel data acquisition, storage and playback method based on an HP interface is applied to the multi-channel data acquisition, storage and playback system based on the HP interface, and is characterized by comprising the following steps:

s1) dividing the first cache unit (4) to obtain a first cache space, dividing the second cache unit (5) to obtain a second cache space, wherein the first cache space and the second cache space correspond to the channels in the HP bus one by one;

s2) the processor system of the FPGA unit (1) receives the instruction of the upper computer (104) through the programmable logic component, if the instruction is the acquisition instruction, the step S3 is skipped, and if the instruction is the playback instruction, the step S4 is skipped;

s3) selecting a first channel corresponding to the acquisition device (101) in the HP bus, acquiring data from the acquisition device (101) by the programmable logic component, caching the data in a corresponding first cache space, sending the cached data to the processor system through the corresponding first channel, caching the received data in a corresponding second cache space in a second cache unit (5) by the processor system, configuring a corresponding folder in the storage unit (2), storing the cached data in the corresponding folder, and returning to the step S2);

s4) if the playback instruction specifies that the playback device (103) plays back, the processor system acquires data in a folder specified by the playback instruction from the storage unit 2, selects a second channel corresponding to the playback device (103) in the HP bus, caches the data in a corresponding second cache space, sends the cached data to the programmable logic component through the corresponding second channel, the programmable logic component caches the received data in a first cache space corresponding to the second channel, sends the cached data to the playback device (103), and returns to the step S2; if the playback instruction specifies playback through the user terminal (102), the processor system acquires the data in the folder specified by the playback instruction from the storage unit (2) and transmits the acquired data to the user terminal (102) through the network connection unit (3), returning to step S2.

7. The HP interface-based multi-channel data acquisition, storage and playback method according to claim 6, wherein step S1) is preceded by a step of updating the program online, specifically comprising:

A1) configuring storage and loading addresses of a G mirror image and an M mirror image in FLASH;

A2) a processor system of the FPGA unit (1) receives an updating program sent by a user terminal (102) through a network connection unit (3), analyzes and judges the data type, stores the data of the updating program in a second cache unit (5) for verification, and writes the data of the updating program into a storage address of an M mirror image through a QSPI mode to update the M mirror image after the verification is passed;

A3) the processor system of the FPGA unit (1) reads the data of the M mirror image from the storage address of the M mirror image and compares the data with the data in the second cache unit (5), and if the data are consistent, an update completion report is sent to the user end (102) through the network connection unit (3);

A4) and the processor system of the FPGA unit (1) loads the M mirror image according to the loading address of the M mirror image, if the loading is successful, the M mirror image is operated, otherwise, the G mirror image is loaded according to the loading address of the G mirror image and operated.

8. The HP interface-based multi-channel data acquisition, storage and playback method according to claim 6, wherein the specific steps of step S3) include:

the processor system selects the channels in the HP bus as corresponding first channels according to the number of the acquisition devices (101), sends write enable signals, the starting address of a second cache space and the length of single transmission data to the programmable logic assembly, the programmable logic assembly generates write instructions after acquiring the write enable signals and sends the write instructions to the first cache unit (4), waits for and acquires data transmitted by the acquisition devices (101), stores the data in the corresponding first cache space, sends the data stored in the first cache space to the corresponding starting address of the second cache space through the corresponding first channel after the data reaches the threshold value, sends the data to the programmable logic assembly through the GP bus after the sent data reaches the length of single transmission data, completes the interruption to the processor system, and increases the write addresses of the second cache space according to the size of the transmitted data, and after receiving the interrupt signal, the processor system sends a write enable signal to the programmable logic component again through the GP bus, simultaneously, folders which are in one-to-one correspondence with the acquisition equipment (101) are set in the storage unit (2), file attributes are set, and data stored in the second cache space are stored in the corresponding folders.

9. The HP interface-based multi-channel data acquisition, storage and playback method according to claim 8, wherein the selecting, by the processor system, the channel in the HP bus as the corresponding first channel according to the number of the acquisition devices (101) specifically comprises: if the number of the acquisition equipment (101) is less than or equal to the number of the channels in the HP bus, selecting one channel in the HP bus as a corresponding first channel for each acquisition equipment (101); if the number of the acquisition devices (101) is larger than the number of the channels in the HP bus, grouping the acquisition devices (101) after counting the data rates of all the acquisition devices (101), wherein the sum of the data rates of each group of the acquisition devices (101) is smaller than or equal to the rate of a single channel in the HP bus, and configuring one channel in the HP bus as a corresponding first channel for each group of the acquisition devices (101).

10. The HP interface-based multi-channel data acquisition, storage and playback method according to claim 6, wherein the acquisition device (101) is connected with the acquisition, storage and playback card through an SRIO bus, and step S3) further includes a step of sending data according to priority, specifically including: if the single channel rate of the SRIO bus is smaller than the data rate input by the acquisition equipment (101), configuring the priority of each channel of the SRIO bus and sending the priority to the processor system, sending the priority to the programmable logic component by the processor system through the GP bus, and sequentially writing the data of each channel of the SRIO bus into the corresponding first cache space by the programmable logic component according to the sequence of the priorities from large to small;

or, if the single channel rate of the SRIO bus is less than the data rate input by the acquisition device (101), the acquisition device (101) sequentially sends the corresponding data to the programmable logic component through the SRIO bus according to a preset priority and a descending order, and the programmable logic component sequentially writes each data into the corresponding first cache space.

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