CN115509974A - Optical fiber data receiving and transmitting processing method based on FPGA - Google Patents
Optical fiber data receiving and transmitting processing method based on FPGA Download PDFInfo
- Publication number
- CN115509974A CN115509974A CN202210927124.9A CN202210927124A CN115509974A CN 115509974 A CN115509974 A CN 115509974A CN 202210927124 A CN202210927124 A CN 202210927124A CN 115509974 A CN115509974 A CN 115509974A
- Authority
- CN
- China
- Prior art keywords
- data
- optical fiber
- recording
- fiber data
- module
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/16—Handling requests for interconnection or transfer for access to memory bus
- G06F13/1668—Details of memory controller
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The invention discloses a method for receiving and transmitting fiber data based on an FPGA (field programmable gate array), and relates to the technical field of high-speed interfaces of computers. The specific implementation mode comprises the following steps: the CPU controls the recording module and the plurality of auroraIPs to enter a receiving preparation state according to a data recording instruction sent by a first user; a plurality of auroraips respectively receive the optical fiber data to be recorded of each path and send the optical fiber data to the recording module; the recording module analyzes the multi-path optical fiber data to be recorded to obtain target recording data and sends the target recording data to a DDR memory for caching; and the CPU acquires target record data from the DDR memory and sends the target record data to the memory card for storage. The embodiment can realize the simultaneous receiving of the multi-path optical fiber data by combining the CPU and the FPGA and utilizing a plurality of auroraIPs, the recording module and the DDR memory of the FPGA; and the playback module of the FPGA and the plurality of auroraIPs are utilized to realize the simultaneous transmission of the multi-path optical fiber data, meet the short-time receiving and transmitting requirement of the high-speed data, improve the transmission efficiency of the optical fiber data and ensure the rapid and complete transmission of the optical fiber data.
Description
Technical Field
The invention belongs to the technical field of high-speed interfaces of computers, and particularly relates to an optical fiber data receiving and transmitting processing method based on an FPGA (field programmable gate array).
Background
On one hand, the transmission rate is low due to the limitation of the transmission rate of a hardware interface; on the other hand, the conventional data transceiving mode only supports single-channel data transceiving, and cannot simultaneously perform multi-channel data transceiving, so that the conventional data transceiving mode cannot meet the short-time transceiving requirement of high-speed transmission data.
Disclosure of Invention
In view of the above, the present invention provides a method for receiving and transmitting optical fiber data based on FPGA, which can combine with FPGA through CPU, and is controlled by CPU, and simultaneously receives multiple paths of optical fiber data by using multiple auroraips, recording modules and DDR memories of FPGA; and then, the playback module of the FPGA and the plurality of auroraIPs are utilized to simultaneously transmit the multi-path optical fiber data, so that the short-time transceiving requirements of high-speed data such as large file volume, multiple data and the like are met, the high-bandwidth communication requirement during the transmission of high-speed equipment is met, the problem that effective data cannot be completely recorded due to the transmission rate is solved, the transmission efficiency of the optical fiber data is greatly improved, and the rapid and complete transmission of the optical fiber data is ensured.
The technical scheme for realizing the invention is as follows:
a method for receiving and sending fiber data based on FPGA is executed by utilizing reactance recording equipment, wherein the reactance recording equipment comprises a main control board, a storage card and a back board, and the main control board and the storage card carry out data transmission through the back board; the main control board comprises a CPU, an FPGA and a DDR memory; the FPGA comprises a plurality of auroraIPs and a recording module; the method comprises the following steps:
the CPU controls the recording module and the plurality of auroraIPs to enter a receiving preparation state according to a data recording instruction sent by a first user; the data transmission instruction comprises optical fiber data to be recorded, and the optical fiber data to be recorded is multi-path optical fiber data;
the plurality of auroraips respectively receive the optical fiber data to be recorded of each path and send the optical fiber data to the recording module; wherein, 1 path of optical fiber data corresponds to 1 aurora IP, and the number of the paths of the optical fiber data to be recorded is less than or equal to that of the aurora IP;
the recording module analyzes the multi-path optical fiber data to be recorded to obtain target recording data and sends the target recording data to the DDR memory for caching;
and the CPU acquires the target record data from the DDR memory and sends the target record data to the memory card for storage.
Optionally, the analyzing, by the recording module, the multiple paths of optical fiber data to be recorded to obtain target recorded data includes:
performing clock domain crossing processing on the optical fiber data to be recorded by using the FIFOIP of the recording module, and determining intermediate recording data according with the clock frequency of the DDR memory;
and arbitrating the intermediate recorded data, determining the data type and the optical fiber path identifier of the intermediate recorded data, and generating the target recorded data.
Optionally, before the CPU controls the recording module and the plurality of auroraips to enter the reception ready state, the method further includes:
and determining whether the recording parameters of the data transmission instruction meet the recording requirements, and if not, rejecting the data transmission instruction.
Optionally, the FPGA further comprises a playback module; further comprising:
the CPU receives a data playback instruction sent by a second user, and controls the playback module and the plurality of auroraIPs to enter a sending preparation state; the data playback instruction indicates a storage address of optical fiber data to be played back and a third user corresponding to the optical fiber data to be played back;
the CPU obtains the optical fiber data to be played back from the memory card according to the memory address and sends the optical fiber data to be played back to the playback module;
and a plurality of the auroraips acquire target playback optical fiber data from the playback module and send the target playback optical fiber data to the third user.
Optionally, before the plurality of auroraips obtain target playback fiber data from the playback module, the method further includes:
and performing clock domain crossing processing on the optical fiber data to be played back by using the FIFOIP of the playback module, and determining target playback data according with the clock frequency of the auroraIP.
Optionally, the CPU and the DDR memory, and the CPU and the playback module communicate with each other through a PCIE interface.
Optionally, before sending the optical fiber data to be played back to the playback module, the method further includes:
and the CPU inquires whether the cache space of the playback module has a storage space through the PCIE interface, if not, the transmission of the optical fiber data to be played back to the playback module is suspended, and the release of the cache space of the playback module is waited.
Optionally, the number of the AuroraIP is 8, and the number of the optical fiber data paths is 8.
Has the beneficial effects that:
(1) By using the AuroraIP, the method for simultaneously recording and playing back the multi-channel optical fiber data realizes the short-time receiving or sending of a large amount of data, meets the high-bandwidth communication requirements of high-speed equipment (such as the conditions of short-time data flow, high speed of equipment data, large file volume and the like), and prevents effective data from being incompletely recorded in a record carrier due to the rate problem.
(2) The CPU is combined with the FPGA and is used for controlling, and a plurality of auroraIPs, a recording module and a DDR memory of the FPGA are used for receiving the multi-path optical fiber data at the same time; and then, the playback module of the FPGA and the plurality of auroraIPs are utilized to simultaneously transmit the multi-path optical fiber data, so that the short-time receiving and transmitting requirements of high-speed data such as large file volume, multiple data and the like are met, the problem that effective data cannot be completely recorded due to the problem of transmission rate is prevented, the transmission efficiency of the optical fiber data is greatly improved, and the optical fiber data is ensured to be quickly and completely transmitted.
(3) The function of high-speed data receiving and transmitting is realized through the FPGA and the ARUORA protocol.
(4) The reactance recording equipment adopts a DDR memory 2123 as a high-speed data cache, can cache target recorded data, provides sufficient data acquisition time for a CPU, ensures efficient, complete and accurate transmission of optical fiber data, and ensures the integrity of the optical fiber data.
Drawings
Fig. 1 is a schematic diagram of a main flow of a method for receiving and transmitting fiber data based on an FPGA according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of the composition of a reactance recording device according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of the FPGA according to the embodiment of the present invention.
Fig. 4 is a schematic diagram illustrating a main flow of a method for determining recording parameters of a data recording command according to an embodiment of the present invention.
Fig. 5 is a schematic diagram illustrating a main flow of a method for determining target record data according to an embodiment of the present invention.
Fig. 6 is a schematic diagram of a main flow of a data playback method based on FPGA fiber data according to an embodiment of the present invention.
200-reactance recording equipment, 210-a main control board, 211-a CPU, 212-an FPGA,2121-auroraIP, 2122-a recording module, 2123-a DDR memory, 2124-a playback module, 2125-a PCIE interface, 2126-a clock module, 2127-a reset management module, 2128-a UART, 2129-a control module, 220-a memory card, 230-a backboard and 240-a power supply.
Detailed Description
The noun explains:
FPGA: the Field Programmable Gate Array refers to a product developed based on Programmable devices such as PAL (Programmable Array Logic) and GAL (general Array Logic). The circuit is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), not only overcomes the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited.
Aurora: is an extensible lightweight link layer protocol for moving data between point-to-point serial links. This provides a transparent interface to the physical layer, allowing the proprietary protocol or industry standard protocol upper layers to conveniently use the high speed transceiver. Aurora is widely used in applications requiring connections between backplanes, circuit boards, and chips, and is widely used in wired communication, storage, servers, test and measurement, industry, consumption, and medical care.
SDRAM: synchronous Dynamic Random-access Memory, which is a Dynamic Random-access Memory with a Synchronous interface, is referred to as SDRAM for short.
DDR memory: double Data Rate SDRAM, referred to as Double Data Rate SDRAM, DDR SDRAM for short.
The invention is described in detail below by way of example with reference to the accompanying drawings.
The invention provides a method for receiving and transmitting fiber data based on FPGA (field programmable gate array), which comprises the following steps of:
In the embodiment of the present invention, the method for receiving and sending the optical fiber data based on the FPGA of the present invention is executed by using a reactance recording device, and the reactance recording device is a CPU + FPGA-based multifunctional data recording device, as shown in fig. 2, the reactance recording device 200 of the present invention includes a main control board 210, a memory card 220, and a back board 230, and the main control board 210 and the memory card 220 communicate through the back board 230 to implement data transmission. The main control board 210 includes a CPU211 and an FPGA212, and is configured to perform data processing, including receiving and sending data. The memory card 220 is a storage carrier for valid data, and is used for storing data.
Further, as shown in fig. 2, the reactance recording device 200 also includes a power supply 240.
In the embodiment of the present invention, as shown in fig. 3, the FPGA212 of the present invention includes a plurality of aurora ips 2121, a recording module 2122, a DDR memory 2123, a playback module 2124, a PCIE interface 2125, a clock module 2126, a reset management module 2127, a UART2128 (Universal Asynchronous Receiver/Transmitter), and a control module 2129. The aurora IP2121 is used for realizing the receiving and sending of optical fiber data; the recording module 2122 is configured to receive the optical fiber data sent by the AuroraIP2121 and cache the optical fiber data in the DDR memory 2123; DDR memory 2123 is used for high-speed data caching; the playback module 2124 is configured to send the fiber data to the target user through the AuroraIP 2121; the PCIE interface 2125 is used for communication between the FPGA212 and the CPU211, and may be an X8 PCIE interface; the clock module 2126 is used for clock management of the FPGA 212; the reset management module 2127 is used for restarting, resetting and other operations of the FPGA 212; the UART2128 is a serial communication interface; the control module 2129 may interact with the CPU211 for monitoring the operational status of various modules within the FPGA 212.
Further, the operating state of the AuroraIP2121 includes on, receive ready, start receiving, receiving in progress, receiving completed, transmit ready, start transmitting, transmitting in progress, transmitting completed, closing, etc., the operating state of the recording module 2122 includes on, receive ready, start recording, recording in progress, recording completed, closing, etc., and the operating state of the playback module 2124 includes on, transmit ready, start playback, playback in progress, playback completed, closing, etc.
In the embodiment of the present invention, the optical fiber data refers to data transmitted/communicated using an optical fiber as a channel. After the CPU211, the FPGA212, and the DDR memory 2123 are powered on and initialized and the link connection is enabled, the CPU starts receiving a data transmission instruction.
In the embodiment of the present invention, before the CPU211 controls the recording module 2122 and the plurality of auroraips 2121 to enter the reception ready state, the method further includes:
In the embodiment of the present invention, the recording parameter includes a transmission protocol, and the like, for example, if the recording parameter is a transmission protocol and the recording requirement is a TCP/UDP protocol, it is determined whether the transmission protocol of the data transmission instruction is the TCP/UDP protocol, and the like.
In the embodiment of the present invention, the CPU211 sends a recording start instruction to the multiple aurora ips 2121 and the recording module 2122 of the FPGA212 through the PCIE interface 2125 of the FPGA212, the multiple aurora ips 2121 and the recording module 2122 enter a receiving preparation state after receiving the recording start instruction, the recording module 2122 and the aurora ip2121 of the corresponding path are opened, and optical fiber data to be recorded is ready to be received and recorded.
In this embodiment of the present invention, alternatively, the CPU211 may send a recording start instruction to the control module 2129 of the FPGA212 through the PCIE interface 2125, so that the control module 2129 controls the plurality of auroraips 2121 and the recording module 2122 to enter a reception ready state.
At step 403, the data transmission command is rejected.
102, respectively receiving each path of optical fiber data to be recorded by a plurality of auroraips, and sending the optical fiber data to a recording module; wherein, 1 path of optical fiber data corresponds to 1 aurora IP, and the number of the paths of the optical fiber data to be recorded is less than or equal to that of the aurora IP.
In the embodiment of the invention, the method for processing the fiber data receiving and transmitting based on the FPGA mainly realizes the function of receiving and transmitting the high-speed data through the FPGA and the ARUORA protocol, is limited by the number of high-speed data channels of the FPGA, is exemplified by taking the number of the aurora IP as 8, and is exemplified by taking the number of the optical fiber data as 8 paths, and 1 aurora IP independently receives 1 path of optical fiber data. It should be noted that the number of paths of the optical fiber data may be less than or equal to the number of AuroraIP, so as to ensure a complete record of the optical fiber data in an actual usage scenario.
And 103, analyzing the multi-path optical fiber data to be recorded by the recording module to obtain target recorded data, and sending the target recorded data to the DDR memory for caching.
In the embodiment of the present invention, the reactance recording device 200 uses the DDR memory 2123 as a high-speed data cache to ensure efficient and accurate transmission of the optical fiber data and ensure the integrity of the optical fiber data.
In the embodiment of the present invention, as shown in fig. 5, the method for determining target record data of the present invention includes the following steps:
In the embodiment of the present invention, the aurora ip2121 and the DDR memory 2123 have different clock frequencies, and it is necessary to perform clock domain crossing processing on the optical fiber data to be recorded sent by the aurora ip2121 by using the FIFOIP21221 of the recording module 2122, so as to ensure that the DDR memory 2123 can accurately and completely receive the target recorded data. For example, the clock frequency of AuroraIP2121 is a frequency a, the clock frequency of DDR memory 2123 is a frequency B, and the optical fiber data to be recorded sent by AuroraIP2121 needs to be processed into intermediate recording data with the frequency B, so that the intermediate recording data meets the clock frequency requirement of DDR memory 2123.
In the embodiment of the present invention, the recording module 2122 arbitrates the intermediate recording data, determines the data type of the intermediate recording data and the fiber path identifier of the AuroraIP2121 corresponding to the path source of the intermediate recording data, and constructs a correspondence between the fiber path identifier, the data type, and the data details to generate target recording data.
And step 104, the CPU acquires the target record data from the DDR memory and sends the target record data to the memory card for storage.
In this embodiment of the present invention, after the aurora ip2121 starts receiving and the recording module 2122 starts recording, the CPU211 acquires target record data from the DDR memory 2123 through the PCIE interface 2125, and sends the target record data to the memory card 220 for storage.
Further, when the CPU211 acquires the target record data from the DDR memory 2123 through the PCIE interface 2125, the target record data is processed across clock domains again to obtain the target record data meeting the clock frequency of the PCIE interface 2125.
In the embodiment of the present invention, when the CPU211 stores the target record data in the memory card 220, the target record data may be stored according to the storage address of the memory card 220, and the corresponding relationship between the target record data and the storage address is stored in a database (for example, mySQL database), so that when data playback is performed in a later period, the database may be searched, and the storage address may be determined to obtain corresponding optical fiber data.
In the embodiment of the present invention, as shown in fig. 6, the data playback method based on the FPGA fiber data includes the following steps:
In the embodiment of the invention, the first user, the second user and the third user can be the same or different, and the determination is carried out according to actual needs.
In the embodiment of the present invention, the CPU211 searches the database according to the data playback instruction, and determines the storage address of the optical fiber data to be played back.
In this embodiment of the present invention, the CPU211 sends a playback start instruction to the multiple aurora ips 2121 and the playback modules 2124 of the FPGA212 through the PCIE interface 2125 of the FPGA212, the multiple aurora ips 2121 and the playback modules 2124 enter a sending preparation state after receiving the playback start instruction, the playback module 2124 and the aurora ip2121 of the corresponding path are started, and optical fiber data to be played back is prepared for playback and sent.
In this embodiment of the present invention, alternatively, the CPU211 may send a playback start instruction to the control module 2129 of the FPGA212 through the PCIE interface 2125, so that the control module 2129 controls the multiple auroraips 2121 and the playback module 2124 to enter the sending preparation state.
In this embodiment of the present invention, the CPU211 sends the optical fiber data to be played back to the playback module 2124 through the PCIE interface 2125 of the FPGA 212.
Further, the fifofip of the playback module 2124 performs clock domain crossing processing on the optical fiber data to be played back, and determines target playback data that conforms to the clock frequency of AuroraIP.
Because the clock frequencies of the PCIE interface 2125 and the aurora ip2121 are different, the FIFOIP21221 of the playback module 2124 needs to perform clock domain crossing processing on the optical fiber data to be played back, which is sent by the PCIE interface 2125, so as to ensure that the aurora ip2121 can accurately and completely send target playback data. For example, the clock frequency of the PCIE interface 2125 is C frequency, the clock frequency of the aurora ip2121 is D frequency, and the to-be-played optical fiber data sent by the PCIE interface 2125 needs to be processed into target playback data with D frequency, so that the target playback data meets the clock frequency requirement of the aurora ip 2121.
In this embodiment of the present invention, before the CPU211 sends the optical fiber data to be played back to the playback module 2124 through the PCIE interface 2125, the CPU211 may query the buffer space of the playback module 2124 through the PCIE interface 2125, determine whether the buffer space of the playback module 2124 has a storage space, and if yes, send the optical fiber data to be played back to the playback module 2124; if not, the transmission of the optical fiber data to be played back to the playback module 2124 is suspended, the release of the cache space of the playback module 2124 is waited, and the optical fiber data to be played back is transmitted to the cache space of the playback module 2124 after the cache space of the playback module 2124 is determined to have the storage space.
In the embodiment of the present invention, multiple auroraips obtain target playback fiber data that meets the clock frequency of the playback module 2124, and send the target playback fiber data to a corresponding third user, so that the target playback fiber data is played back to the third user through a fiber interface.
In summary, the above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A method for receiving and sending fiber data based on FPGA is characterized in that the method is executed by using reactance recording equipment, wherein the reactance recording equipment comprises a main control board, a storage card and a back board, and the main control board and the storage card carry out data transmission through the back board; the main control board comprises a CPU, an FPGA and a DDR memory; the FPGA comprises a plurality of auroraIPs and a recording module; the method comprises the following steps:
the CPU controls the recording module and the plurality of auroraIPs to enter a receiving preparation state according to a data recording instruction sent by a first user; the data transmission instruction comprises optical fiber data to be recorded, and the optical fiber data to be recorded is multi-path optical fiber data;
the plurality of auroraips respectively receive the optical fiber data to be recorded of each path and send the optical fiber data to the recording module; wherein, 1 path of optical fiber data corresponds to 1 aurora IP, and the number of the paths of the optical fiber data to be recorded is less than or equal to that of the aurora IP;
the recording module analyzes the multi-path optical fiber data to be recorded to obtain target recording data, and sends the target recording data to the DDR memory for caching;
and the CPU acquires the target record data from the DDR memory and sends the target record data to the memory card for storage.
2. The method of claim 1, wherein the analyzing the plurality of paths of the optical fiber data to be recorded by the recording module to obtain target recording data comprises:
performing clock domain crossing processing on the optical fiber data to be recorded by using the FIFOIP of the recording module, and determining intermediate recording data according with the clock frequency of the DDR memory;
and arbitrating the intermediate recorded data, determining the data type and the optical fiber path identifier of the intermediate recorded data, and generating the target recorded data.
3. The method of claim 1, before the CPU controls the logging module and the plurality of auroraips to enter a receive ready state, further comprising:
and determining whether the recording parameters of the data transmission instruction meet the recording requirements, and if not, rejecting the data transmission instruction.
4. The method of claim 1, wherein the FPGA further comprises a playback module; further comprising:
the CPU receives a data playback instruction sent by a second user, and controls the playback module and the plurality of auroraIPs to enter a sending preparation state; the data playback instruction indicates a storage address of optical fiber data to be played back and a third user corresponding to the optical fiber data to be played back;
the CPU obtains the optical fiber data to be played back from the storage card according to the storage address and sends the optical fiber data to be played back to the playback module;
and a plurality of the auroraips acquire target playback optical fiber data from the playback module and send the target playback optical fiber data to the third user.
5. The method of claim 4, wherein prior to said plurality of said auroraips obtaining target playback fiber data from said playback module, further comprising:
and performing clock domain crossing processing on the optical fiber data to be played back by using the FIFOIP of the playback module, and determining target playback data according with the clock frequency of the auroraIP.
6. The method of any of claims 1-5, wherein the CPU and the DDR memory, the CPU and the playback module communicate over a PCIE interface.
7. The method of claim 6, wherein before the sending the fiber data to be played back to the playback module, further comprising:
and the CPU inquires whether the cache space of the playback module has a storage space through the PCIE interface, if not, the transmission of the optical fiber data to be played back to the playback module is suspended, and the release of the cache space of the playback module is waited.
8. The method of claim 1, wherein the number of the AuroraIP is 8, and the number of the fiber data paths is 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210927124.9A CN115509974B (en) | 2022-08-03 | 2022-08-03 | Method for receiving and transmitting optical fiber data based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202210927124.9A CN115509974B (en) | 2022-08-03 | 2022-08-03 | Method for receiving and transmitting optical fiber data based on FPGA |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN115509974A true CN115509974A (en) | 2022-12-23 |
| CN115509974B CN115509974B (en) | 2023-06-20 |
Family
ID=84502479
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202210927124.9A Active CN115509974B (en) | 2022-08-03 | 2022-08-03 | Method for receiving and transmitting optical fiber data based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN115509974B (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117555837A (en) * | 2024-01-10 | 2024-02-13 | 成都领目科技有限公司 | Ultra-wideband high-speed playback data flow control method and system |
Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103428115A (en) * | 2013-07-25 | 2013-12-04 | 浙江大学 | Inter-board multicast optical interconnection network constructing method based on development boards |
| CN107817217A (en) * | 2017-10-31 | 2018-03-20 | 武汉精测电子集团股份有限公司 | A kind of image suitable for LCM automatic optics inspections accelerates processing system |
| CN207166493U (en) * | 2017-08-24 | 2018-03-30 | 中北大学 | A kind of LVDS-optical fiber interface converter |
| CN108429904A (en) * | 2018-06-11 | 2018-08-21 | 山东超越数控电子股份有限公司 | A kind of video optical multiplexer clock circuitry |
| WO2019085605A1 (en) * | 2017-10-31 | 2019-05-09 | 武汉精测电子集团股份有限公司 | Automatic optical detection system based on cpu+gpu+fpga architecture |
| CN112866836A (en) * | 2020-12-31 | 2021-05-28 | 华中光电技术研究所（中国船舶重工集团公司第七一七研究所） | Information exchange device based on VPX architecture |
| CN213338710U (en) * | 2020-11-02 | 2021-06-01 | 北京太速科技股份有限公司 | Heterogeneous computing server based on full connection of multiple FPGA board cards |
| CN113590528A (en) * | 2021-07-20 | 2021-11-02 | 湖南艾科诺维科技有限公司 | Multi-channel data acquisition, storage and playback card, system and method based on HP interface |
| CN113986130A (en) * | 2021-10-27 | 2022-01-28 | 成都旋极历通信息技术有限公司 | High-capacity high-speed multichannel data playback equipment and method |
| CN114297121A (en) * | 2021-12-10 | 2022-04-08 | 北京遥测技术研究所 | Method for realizing bidirectional high-speed data transmission between chips based on FPGA |
| CN216751965U (en) * | 2021-12-08 | 2022-06-14 | 成都恩菲特科技有限公司 | ARINC818 video data compression and decompression processing device based on FPGA |
-
2022
- 2022-08-03 CN CN202210927124.9A patent/CN115509974B/en active Active
Patent Citations (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103428115A (en) * | 2013-07-25 | 2013-12-04 | 浙江大学 | Inter-board multicast optical interconnection network constructing method based on development boards |
| CN207166493U (en) * | 2017-08-24 | 2018-03-30 | 中北大学 | A kind of LVDS-optical fiber interface converter |
| CN107817217A (en) * | 2017-10-31 | 2018-03-20 | 武汉精测电子集团股份有限公司 | A kind of image suitable for LCM automatic optics inspections accelerates processing system |
| WO2019085605A1 (en) * | 2017-10-31 | 2019-05-09 | 武汉精测电子集团股份有限公司 | Automatic optical detection system based on cpu+gpu+fpga architecture |
| CN108429904A (en) * | 2018-06-11 | 2018-08-21 | 山东超越数控电子股份有限公司 | A kind of video optical multiplexer clock circuitry |
| CN213338710U (en) * | 2020-11-02 | 2021-06-01 | 北京太速科技股份有限公司 | Heterogeneous computing server based on full connection of multiple FPGA board cards |
| CN112866836A (en) * | 2020-12-31 | 2021-05-28 | 华中光电技术研究所（中国船舶重工集团公司第七一七研究所） | Information exchange device based on VPX architecture |
| CN113590528A (en) * | 2021-07-20 | 2021-11-02 | 湖南艾科诺维科技有限公司 | Multi-channel data acquisition, storage and playback card, system and method based on HP interface |
| CN113986130A (en) * | 2021-10-27 | 2022-01-28 | 成都旋极历通信息技术有限公司 | High-capacity high-speed multichannel data playback equipment and method |
| CN216751965U (en) * | 2021-12-08 | 2022-06-14 | 成都恩菲特科技有限公司 | ARINC818 video data compression and decompression processing device based on FPGA |
| CN114297121A (en) * | 2021-12-10 | 2022-04-08 | 北京遥测技术研究所 | Method for realizing bidirectional high-speed data transmission between chips based on FPGA |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN117555837A (en) * | 2024-01-10 | 2024-02-13 | 成都领目科技有限公司 | Ultra-wideband high-speed playback data flow control method and system |
Also Published As
| Publication number | Publication date |
|---|---|
| CN115509974B (en) | 2023-06-20 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US9996491B2 (en) | Network interface controller with direct connection to host memory | |
| CN106294239B (en) | A kind of peripheral bus APB bus bridge | |
| CN109165178B (en) | Rapid IO-based high-speed communication method between SoC (system on a chip) chips of system on missile | |
| CN107168644B (en) | High-speed high capacity broadband I/Q data loggers based on SFP optical fiber interfaces | |
| CN104021102A (en) | CPCI serial port plate based on state machine and on-chip bus and working method of CPCI serial port plate | |
| CN112540952B (en) | System on chip with on-chip parallel interface | |
| CN115509974A (en) | Optical fiber data receiving and transmitting processing method based on FPGA | |
| CN107766266B (en) | High-speed data acquisition and storage system based on FPGA and PCIe | |
| WO2016095435A1 (en) | Multi-chip cascading method, chip and device, and storage medium | |
| CN112306146B (en) | Device and method for synchronizing output waveforms of AWG board cards in multi-PXIE chassis | |
| Guo et al. | FPGA implementation of VLC communication technology | |
| CN114443170B (en) | FPGA dynamic parallel loading and unloading system | |
| CN105356988A (en) | PCIe based full duplex DMA transmission method | |
| US8260994B2 (en) | Interface for prototyping integrated systems | |
| CN110673021B (en) | NoC-based boundary scan test control method and controller interface | |
| CN113611102B (en) | Multi-channel radar echo signal transmission method and system based on FPGA | |
| CN207764789U (en) | Bridge for seismic detector master station CPU and peripheral data transmission | |
| CN110309086A (en) | A kind of multichannel low speed mouth and single channel high speed port data interactive method | |
| CN110704349B (en) | SpaceWire node device for reliable data transmission | |
| CN112557886B (en) | Protocol conversion bridge circuit and system-on-chip | |
| CN111614551A (en) | PCIE gigabit Ethernet MAC layer controller and driving method | |
| TW202215254A (en) | Low-latency optical connection for cxl for a server cpu | |
| US8913527B2 (en) | Multiple die communication system | |
| CN106980474A (en) | A kind of data logger based on PCIE interfaces | |
| CN104008076A (en) | Bus data signal transmitting method and device capable of supporting DVFS |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |