CN207764789U - Bridge for seismic detector master station CPU and peripheral data transmission - Google Patents

Abstract

It includes cpu i/f module that the utility model discloses a kind of for seismic detector master station CPU and the bridge of peripheral data transmission, ethernet interface module, ADC interface module, Data Integration packetization module, command analysis module and data buffer, data buffer includes peripheral data buffer, adc data buffer and integral data buffer, ethernet interface module is connect with peripheral data buffer, ADC interface module is connect with adc data buffer, peripheral data buffer, adc data buffer is connect by Data Integration packetization module with integral data buffer, integral data buffer, command analysis module is connect with cpu i/f module.The utility model makes the CPU of master station only need to connect with bridge, without and each peripheral hardware and ADC chip direct communications, communication frequency is greatly decreased between CPU and peripheral hardware, and system execution efficiency is greatly improved.

Description

Bridge for seismic detector master station CPU and peripheral data transmission

Technical field

It is specifically a kind of for seismic detector master station CPU and outer the utility model is related to geophysical prospecting equipment field If the bridge of data transmission.

Background technology

Most common instrument is seismic detector in field of geophysical exploration, and distributed seismic instrument is usually by acquisition station, intersection It stands and master station is constituted.In general master station needs to summarize the data and the ADC of its own that the cross-station on both sides uploads（Number Mode converter）These data are passed to computer by the reference signal of acquisition by general-purpose interface together.In CN102628957A It is by two cross-station data by two gigabit Ethernet physical layer transceivers（PHY）It is directly connected to CPU, and is born on master station The ADC of duty acquisition reference signal is generally required under this configuration passes through SPI（Serial device interconnects）Bus is connected on CPU. The shortcomings that this method is that all devices are all directly coupled on cpu bus, and when peripheral hardware increases, CPU efficiency can be remarkably decreased, and Peripheral hardware as ADC does not support DMA transfer due to not having to cache, and CPU needs are just once transmitted every a sampling time, It is extremely inefficient.Master station in another aspect CN102628957A（Root node）It needs to use multichannel ethernet switch hub, intersect Also ICP/IP protocol must be run plus cpu system on standing, equipment power dissipation is big, complicated to be unfavorable for field construction.In order to The PHY reduced on system complexity cross-station and master station can not run ICP/IP protocol, its physical layer only be used only, in object The transport protocol of privatization is established on reason layer.PHY is even more that cannot be connected directly to CPU in this case.In order to solve this A problem needed between CPU and PHY use a kind of bridging device, this bridging device should summarize all peripheral datas then with Unified mode and CPU communications, it should be noted that this bridging device is not general-purpose device, is needed exclusively for seismic detector master Control station is customized according to CPU models and peripheral type.Referred in CN103631179B between a kind of CPU and peripheral hardware by FPGA（Field programmable gate array）Either CPLD is come the method that is communicated, however actually peripheral hardware is still straight herein In succession on the data/address bus of CPU, FPGA only therefrom plays the role of controlling the signals such as the piece choosing of peripheral hardware, play not yet It is bridge joint effect, it is less efficient, and it requires the type of peripheral hardware, it is necessary to and all it is the universal serial bus using same protocol Equipment or traditional parallel data bus line equipment.Can not also solve our demand in this way.

Utility model content

The technical problem to be solved by the present invention is to provide one kind to transmit for seismic detector master station CPU and peripheral data Bridge so that the CPU of master station only needs to connect with bridge, without and each peripheral hardware and ADC chip direct communications, CPU Communication frequency is greatly decreased between peripheral hardware, and system execution efficiency is greatly improved.

The technical solution of the utility model is：

Include that cpu i/f module, Ethernet connect for the bridge of seismic detector master station CPU and peripheral data transmission Mouth mold block, ADC interface module, Data Integration packetization module, command analysis module and data buffer, the data buffer Include that peripheral data buffer, adc data buffer and integral data buffer, peripheral apparatus pass through ethernet interface module It being connect with peripheral data buffer, the ADC chips of seismic detector master station are connect by ADC interface module with adc data buffer, The peripheral data buffer, adc data buffer are connect by Data Integration packetization module with integral data buffer, Integral data buffer, command analysis module are connect with cpu i/f module, and integral data buffer is for the number after integrating It is sent to CPU according to by cpu i/f module, command analysis module is for handling the command number that CPU is sent to cpu i/f module According to, and control according to the command number and command parameter made an appointment the running parameter of ADC chips and peripheral apparatus.

The peripheral apparatus is cross-station, and there are two cross-station, two cross-stations for connection on each seismic detector master station It is connect with peripheral data buffer by ethernet interface module.

The Data Integration packetization module is the singlechip chip being packaged for Data Integration.

The command analysis module is for ADC chips and peripheral apparatus work to be parsed and controlled to order data Make the microcontroller chip of parameter.

The advantages of the utility model：

The bridge of the utility model so that the ethernet transceiver being connected with cross-station on seismic detector master station need not ICP/IP protocol is run, and uses the proprietary protocol simplified, this makes need not be exclusively with support multichannel Ethernet on master station CPU so that cpu system is eliminated on cross-station, it is possible to reduce system component and power consumption.The utility model makes peripheral apparatus With the data of ADC chips without being immediately sent to CPU, can be buffered in bridge wait for have accumulated certain amount after again together It is transferred to CPU by dma mode, is greatly improved CPU operational efficiency.

Description of the drawings

Fig. 1 is the structure chart that the utility model is applied to that master station CPU is connect with peripheral apparatus, ADC chips.

Specific implementation mode

The following will be combined with the drawings in the embodiments of the present invention, carries out the technical scheme in the embodiment of the utility model Clearly and completely describe, it is clear that the described embodiments are only a part of the embodiments of the utility model, rather than whole Embodiment.Based on the embodiments of the present invention, those of ordinary skill in the art are without making creative work The every other embodiment obtained, shall fall within the protection scope of the present invention.

See Fig. 1, for the bridge of seismic detector master station CPU and peripheral data transmission, include cpu i/f module 11, Ethernet interface module 12, ADC interface module 13, Data Integration packetization module 14, command analysis module 15 and data buffer, Data buffer includes peripheral data buffer 16, adc data buffer 17 and integral data buffer 18, peripheral apparatus 2 It is connect with peripheral data buffer 16 by ethernet interface module 12, the ADC chips 3 of seismic detector master station pass through ADC interface Module 13 is connect with adc data buffer 17, and peripheral data buffer 16, adc data buffer 17 are beaten by Data Integration Packet module 14 is connect with integral data buffer 18, integral data buffer 18, command analysis module 15 with cpu i/f module 11 connections, integral data buffer 18 are used to the data after integrating being sent to CPU 4, order solution by cpu i/f module 11 Analysis module 15 for handling the order data that CPU 4 is sent to cpu i/f module 11, and according to the command number made an appointment with Command parameter controls the running parameter of ADC chips 3 and peripheral apparatus 2.

Wherein, peripheral apparatus 2 is cross-station, and there are two cross-station, two cross-stations for connection on each seismic detector master station It is connect with peripheral data buffer 16 by ethernet interface module 12；Data Integration packetization module 14 is for Data Integration The singlechip chip of packing；Command analysis module 15 is for being parsed to order data and controlling ADC chips and peripheral hardware The microcontroller chip of equipment parameters.

The data transmission method of bridge, has specifically included following steps：

（1）, the 3 collected data of ADC chips on master station be converted into 32 by ADC interface module 13 by spi bus Bit parallel data is buffered in the queue FIFO1 of adc data buffer 17, and the data that cross-station 2 uploads are by Ethernet interface Module 12 is buffered in the queue FIFO2 and FIFO3 of peripheral data buffer 16；

（2）, Data Integration module 14 snoop queue FIFO1, FIFO2 and FIFO3, wherein any one queue depth reaches When 256 byte, Data Integration module 14 just starts this FIFO process of reading, and continuously reads 256 bytes, it is judged whether there is after running through His queue depth reaches 256 bytes, other queues is read if any being then switched to, as entered idle state without if；

（3）, all data read of Data Integration module 14 be sent to the queue FIFO4 of integral data buffer 18 In, when cpu i/f module 11 detects that FIFO4 depth reaches the several times of 8192 bytes, DMA request can be sent to CPU 4, CPU 4 starts read procedure after responding, and the chip selection signal and output enable signal of CPU 4 can start effectively；

（4）, CPU 4 drive module need to complete following work to support bridge read operation：Drive module is in kernel Be loaded into kernel after startup, initialization function completes the setting of DMA transfer parameters, it is main include specified DMA channel, Call back function is set, source address, destination address and the conveying length that setting is transmitted；Then after bridge sends out DMA request, bridge The data for connecing device can be by DMA transfer to pre-set Circular buffer, this buffer circle 64MB in total, with single DMA For transmitting 8192 bytes, then 8192 units are shared in buffering area, Circular buffer is equipped with read pointer and write pointer, and kernel is every Secondary DMA transfer can call the call back function pre-set, call back function that can write pointer be added 1 automatically after completing, and refer to when writing Needle can turn back after being added to 8192 to 0；The parameters that last call back function can update the next DMA transfer of setting wait for DMA The arrival of request, so moves in circles；And when the read operation of client layer application call bridging device, kernel-driven module The difference that can judge write pointer at this time and read pointer then reads and successfully returns immediately if it is larger than or equal to the data volume of user demand, Otherwise process can enter sleep state until the arrival of next DMA request has enough data that can read, and so far bridge is complete At the bridge joint process of whole equipment digital independent

（5）, order data issues：Write operation is directly converted into the physical address corresponding to bridge by CPU 4 Write operation data, then the chip selection signal line of CPU 4 and write enable signal line start effectively, bridge captures data/address bus accordingly On data, then data be sent to command analysis module 15 and handled, command analysis module 15 is according to command number and life It enables parameter determine the parameter of the sample rate and peripheral apparatus 2 of ADC chips 3, and then can start and ADC interface module 13 and ether The write operation for the spi bus that network interface module 12 connects, ADC cores are sent respectively to by newer sampling rate score and parameter values Piece 3 and peripheral apparatus 2.

While there has been shown and described that the embodiments of the present invention, for the ordinary skill in the art, It is appreciated that can these embodiments be carried out with a variety of variations in the case where not departing from the principles of the present invention and spirit, repaiied Change, replace and modification, the scope of the utility model are defined by the appended claims and the equivalents thereof.

Claims (4)

1. the bridge for seismic detector master station CPU and peripheral data transmission, it is characterised in that：Include cpu i/f module, Ethernet interface module, ADC interface module, Data Integration packetization module, command analysis module and data buffer, the number Include that peripheral data buffer, adc data buffer and integral data buffer, peripheral apparatus pass through Ethernet according to buffer Interface module is connect with peripheral data buffer, and the ADC chips of seismic detector master station are slow by ADC interface module and adc data Storage connects, and the peripheral data buffer, adc data buffer are slow by Data Integration packetization module and integral data Storage connects, and integral data buffer, command analysis module are connect with cpu i/f module, and integral data buffer is used for will Data after integration are sent to CPU by cpu i/f module, and command analysis module is sent to cpu i/f module for handling CPU Order data, and control according to the command number and command parameter made an appointment the work of ADC chips and peripheral apparatus Parameter.

2. the bridge according to claim 1 for seismic detector master station CPU and peripheral data transmission, feature exists In：The peripheral apparatus is cross-station, is connected on each seismic detector master station there are two cross-station, two cross-stations pass through Ethernet interface module is connect with peripheral data buffer.

3. the bridge according to claim 1 for seismic detector master station CPU and peripheral data transmission, feature exists In：The Data Integration packetization module is the singlechip chip being packaged for Data Integration.

4. the bridge according to claim 1 for seismic detector master station CPU and peripheral data transmission, feature exists In：The command analysis module is for ADC chips and peripheral apparatus work ginseng to be parsed and controlled to order data Several microcontroller chips.