CN207166493U

CN207166493U - A kind of LVDS-optical fiber interface converter

Info

Publication number: CN207166493U
Application number: CN201721064961.4U
Authority: CN
Inventors: 王红亮
Original assignee: North University of China
Current assignee: North University of China
Priority date: 2017-08-24
Filing date: 2017-08-24
Publication date: 2018-03-30
Anticipated expiration: 2027-08-24

Abstract

It the utility model is related to optical fiber communication technology, more particularly to a kind of LVDS-optical fiber interface converter, solve LVDS interface and SFP optical mode data transmission problems, including LVDS interface chip, FPGA, DDR3 cache chip, SFP optical modules, MDR interface modules, SFP optical fiber interfaces and peripheral circuit, the LVDS interface chip is connected by MDR interface modules with LVDS equipment, the FPGA is connected with LVDS interface chip, DDR3 cache chips, SFP optical modules respectively, and the SFP optical modules are connected by SFP optical fiber interfaces with SFP high-speed processing apparatus.The utility model can realize LVDS interface and SFP optical fiber interface interactive communications, can be widely applied to field of data communication.

Description

A kind of LVDS-optical fiber interface converter

Technical field

The utility model belongs to technical field of optical fiber communication, more particularly to a kind of LVDS-optical fiber interface converter.

Background technology

With the popularization of Fibre Optical Communication Technology, and SFP（Small Form-Factor Pluggable Optical）Light Building block technique is constantly progressive, and fiber optic data communication interface circuit can realize km level long range, the high speed number of gigabit transmission bandwidth According to transmission, while do not disturbed by complex electromagnetic environment, therefore Modern High-Speed storage test equipment majority is all developed based on SFP Fiber optic data communication interface.At present, most spectrum analyzer communication interfaces are still high speed LVDS（Low Voltage Differential Signaling）Interface, therefore the high speed storing test equipment based on SFP modules and most LVDS interfaces Frequency spectrograph can not direct communication progress data storage analysis.Therefore, it is necessary to which designing a kind of converter makes LVDS interface and SFP optical fiber Interactive interfacing communicates.

The content of the invention

In order to solve LVDS interface and SFP optical mode data transmission problems, the utility model provides a kind of LVDS-optical fiber and connect Mouth converter.

The utility model adopts the following technical scheme that completion：

A kind of LVDS-optical fiber interface converter, it is characterised in that：Including LVDS interface chip, FPGA, DDR3 caching core Piece, SFP optical modules, MDR interface modules, SFP optical fiber interfaces and peripheral circuit, the LVDS interface chip pass through MDR interface moulds Block is connected with LVDS equipment, and the FPGA is connected with LVDS interface chip, DDR3 cache chips, SFP optical modules respectively, described SFP optical modules are connected by SFP optical fiber interfaces with SFP high-speed processing apparatus.

The LVDS interface chip includes LVDS data transmission chip and LVDS data receiver chips；

The FPGA includes LVDS and sends control module and LVDS receive and control modules, DDR3 Read-write Catrols module, FIFO Cache module, reset special clock module, reseting module, data transmit-receive module, Aurora fiber optic communication control modules；

The LVDS data receivers chip is connected by LVDS receive and control modules with DDR3 Read-write Catrol modules, described DDR3 Read-write Catrols module sends control module by LVDS and is connected with LVDS data transmission chips, the DDR3 Read-write Catrols mould Block is connected with the DDR3 cache chips and FIFO cache modules, the data transmit-receive module and the FIFO cache modules and institute The connection of Aurora fiber optic communications control module is stated, the Aurora fiber optic communications control module is connected by the SFP optical modules； The reset special clock module is connected with the reseting module, DDR3 Read-write Catrols module, data transmit-receive module, the reset Module is connected with the Aurora fiber optic communications control module.

The FPGA is XC7K325T chips.

The SFP optical modules model AGL10104A, centre wavelength 850nm.

The LVDS data transmission chip is DS90CR485, and LVDS data receivers chip is DS90CR486.

The LVDS equipment is spectrum analyzer.

Compared with prior art, the beneficial effects of the utility model are：The utility model can realize LVDS interface and SFP Communication between optical fiber interface；, can automatic identification transmission link work by judging whether each interface Back end data FIFO is sky Make state；Using in FPGA GTX transceivers realize the high-speed light port communications based on Aurora agreements, can be privately owned upper-layer protocol or Standard upper-layer protocol provides transparent bottom serial interconnection agreement, realizes that numerous high-speed datas pass by context encapsulation operation Defeated standard；On the basis of hardware circuit is not changed, it is only necessary to adjust hardware logic can and receive or send different pieces of information bag form Data, it is possible to meet distinct device communication requirement.

Brief description of the drawings

Fig. 1 is the utility model structure diagram；

Fig. 2 is the utility model hardware structure diagram；

Fig. 3 is formed inside the utility model Aurora IP kernels

Fig. 4 is the utility model LVDS interface connection diagram；

Fig. 5 is the utility model optical fiber interface transmitting-receiving connection diagram.

Embodiment

Below in conjunction with accompanying drawing, the utility model is described in further detail.

As shown in figure 1, a kind of LVDS-optical fiber interface converter, including LVDS interface chip, FPGA, DDR3 caching core Piece, SFP optical modules, MDR interface modules, SFP optical fiber interfaces and peripheral circuit, the LVDS interface chip pass through MDR interface moulds Block is connected with LVDS equipment, and the FPGA is connected with LVDS interface chip, DDR3 cache chips, SFP optical modules respectively, described SFP optical modules are connected by SFP optical fiber interfaces with SFP high-speed processing apparatus.

Wherein, the LVDS interface chip includes LVDS data transmission chip and LVDS data receiver chips；Such as Fig. 2 institutes Show, the FPGA includes LVDS and sends control module and LVDS receive and control modules, DDR3 Read-write Catrols module, FIFO caching moulds Block, reset special clock module, reseting module, data transmit-receive module, Aurora fiber optic communication control modules；The LVDS data Reception chip is connected by LVDS receive and control modules with DDR3 Read-write Catrol modules, and the DDR3 Read-write Catrols module passes through LVDS sends control module and is connected with LVDS data transmission chips, the DDR3 Read-write Catrols module and the DDR3 cache chips Connected with FIFO cache modules, the data transmit-receive module controls with the FIFO cache modules and the Aurora fiber optic communications Module is connected, and the Aurora fiber optic communications control module is connected by the SFP optical modules；The reset special clock module It is connected with the reseting module, DDR3 Read-write Catrols module, data transmit-receive module, the reseting module and the Aurora optical fiber Communication control module connects.

The FPGA is XC7K325T chips.

The SFP optical modules model AGL10104A, centre wavelength 850nm.

The LVDS equipment is spectrum analyzer.

The reset special clock, upon power-up of the system, for initialization data transceiver module and DDR3 module for reading and writing.

The reseting module utilizes the clock signal driving Aurora fiber optic communication control modules for resetting special clock offer In high-speed transceiver GTX initialized.

The GTX differential clocks be used to providing high-speed transceiver GTX stringizations in Aurora fiber optic communication control modules with The reference clock to unstring.

The FIFO cache modules are used to judge interfaces state, and LVDS data receiver chips are in running order and light Fine interface does not have data input, then it is assumed that current operation mode is LVDS interface to optical fiber interface；At LVDS data transmission chips In working condition, while optical fiber interface has data output, then it is assumed that current operation mode is optical fiber interface to LVDS interface.

As shown in figure 3, the Aurora fiber optic communications control module uses Aurora IP kernels to be based on for design basis The full duplex frame format of Locallink bus forms, Aurora IP kernels include high-speed transceiver link logical, global logic, connect By user interface, send user interface, high-speed transceiver GTX；High-speed transceiver link logical is used to initialize high-speed transceiver GTX, and complete data encoding, data decoding and error detection；Global logic is each for combining, verifying and initializing Link and the encapsulation for completing Aurora agreements, transmitting-receiving user interface are used to control AuroraIP cores to read and write data, complete number of links According to transmitting-receiving.When sending data, Locallink buses deliver to UDP message bag valid data GTX PCS sublayers（Physical Coding Sublayer Physical Coding Sublayers）, encode according to 8B/10B coding forms, send out data by GTX after the completion of coding Sending end is sent.It is similar with data are sent when receiving data, GTX transmitting terminal and receiving terminal functional independence, therefore fiber data is first GTX receiving terminals are introduced into, are decoded subsequently into PCS sublayers, most data are uploaded to storage device at last.

As shown in figure 4, LVDS interface chip is connected with MDR interfaces by 8 pairs of differential datas to form, MDR interfaces are one Kind specialized high-speed difference docking port, in order to ensure that signal integrity realizes high-speed-differential to data transfer, by each pair differential impedance Control as 100 Ω.As shown in figure 4, wherein, LVDS data transmission chips DS90CR485 pin TXP, TXN are used to send difference Data, pin TXCLK_P, TXCLK_N are used to send corresponding channel associated clock signal；LVDS data receiver chips DS90CR485 Pin RXP, RXN be used to receive differential data, RXCLK_P, RXCLK_N are used to receive corresponding channel associated clock signal.

As shown in figure 5, optical fiber interface optical module uses the AGL10104A type SFP optical modules of Avago companies.In the module Cardiac wave long 850nm, maximum transmission distance 500m, peak transfer rate 10Gbps.FPGA passes through controlling switch SFP_TX_ DISABLE controls SFP optical module communication patterns, by pin IIC_SDA_SFP and IIC_SCL_SFP and SFP optical modules Portion's controller communication.

In order to match LVDS interface and optical fiber interface data rate, while in order to improve system efficiency of transmission to greatest extent, Data buffer storage is carried out using DDR3.DDR3-SDRAM Read-write Catrols employ the MIG IP kernels of Xilinx companies offer, MIG IP Core mainly completes data buffer storage by the MCB stones in fpga chip and outside SDRAM chips.

A kind of operation principle of LVDS-optical fiber interface converter of the present utility model is as follows：Data pass through in LVDS interface MDR is interfaced to LVDS interface chip, is unstringed by LVDS data receiver chips DS90CR486, and DDR3 Read-write Catrols module is using table tennis Data after pang caching technology will unstring write DDR3 cache chips, and data in DDR3 cache chips are sequential read out and write Into FIFO cache modules, the data in DDR3 cache chips are sent to Aurora fiber optic communications by data transmit-receive module and controlled Module carries out the processing such as string, coding, error detection and encapsulation, while GTX differential clocks module provides stringization clock, then will Data after encapsulation are sent to SFP optical modules, and SFP high-speed processing apparatus is uploaded to finally by optical fiber；Data in optical fiber interface Similar to LVDS interface process, data are sent to FPGA Aurora fiber optic communication control modules by optical fiber interface by data flow, Aurora fiber optic communication control modules are unpacked, while GTX differential clocks module provides the clock that unstrings, then by data transmit-receive mould Block is sent into FIFO cache modules, and data in FIFO cache modules are sequential read out and write by DDR3 Read-write Catrols module Into DDR3 cache chips, LVDS sends control module and reads the data cached in DDR3 cache chips simultaneously, then by LVDS It is sent to after data transmission chip DS90CR485 stringizations on LVDS cable, data are to LVDS equipment after finally uploading stringization.

Claims

A kind of 1. LVDS-optical fiber interface converter, it is characterised in that：Including LVDS interface chip, FPGA, DDR3 cache chip, SFP optical modules, MDR interface modules, SFP optical fiber interfaces and peripheral circuit, the LVDS interface chip by MDR interface modules with LVDS equipment is connected, and the FPGA is connected with LVDS interface chip, DDR3 cache chips, SFP optical modules respectively, the SFP light Module is connected by SFP optical fiber interfaces with SFP high-speed processing apparatus.
A kind of 2. LVDS-optical fiber interface converter according to claim 1, it is characterised in that：

The LVDS interface chip includes LVDS data transmission chip and LVDS data receiver chips；

The FPGA includes LVDS and sends control module and LVDS receive and control modules, DDR3 Read-write Catrols module, FIFO cachings Module, reset special clock module, reseting module, data transmit-receive module, Aurora fiber optic communication control modules；

The LVDS data receivers chip is connected by LVDS receive and control modules with DDR3 Read-write Catrol modules, and the DDR3 is read Write control module to be connected with LVDS data transmission chips by LVDS transmissions control module, the DDR3 Read-write Catrols module and institute State DDR3 cache chips to connect with FIFO cache modules, the data transmit-receive module and the FIFO cache modules and described Aurora fiber optic communications control module is connected, and the Aurora fiber optic communications control module is connected by the SFP optical modules；Institute State reset special clock module to be connected with the reseting module, DDR3 Read-write Catrols module, data transmit-receive module, the reset mould Block is connected with the Aurora fiber optic communications control module.
3. LVDS according to claim 1-optical fiber interface converter, it is characterised in that：The FPGA is XC7K325T cores Piece.
4. LVDS according to claim 1-optical fiber interface converter, it is characterised in that：The SFP optical modules model AGL10104A, centre wavelength 850nm.
5. LVDS according to claim 2-optical fiber interface converter, it is characterised in that：The LVDS data transmission chip For DS90CR485, LVDS data receivers chip is DS90CR486.
6. LVDS according to claim 1-optical fiber interface converter, it is characterised in that：The LVDS equipment is frequency spectrum point Analyzer.