CN105763258A - FPGA-based digital processing and control system - Google Patents
FPGA-based digital processing and control system Download PDFInfo
- Publication number
- CN105763258A CN105763258A CN201610154943.9A CN201610154943A CN105763258A CN 105763258 A CN105763258 A CN 105763258A CN 201610154943 A CN201610154943 A CN 201610154943A CN 105763258 A CN105763258 A CN 105763258A
- Authority
- CN
- China
- Prior art keywords
- optical fiber
- data
- module
- interface
- rocketi
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/25—Arrangements specific to fibre transmission
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B10/00—Transmission systems employing electromagnetic waves other than radio-waves, e.g. infrared, visible or ultraviolet light, or employing corpuscular radiation, e.g. quantum communication
- H04B10/27—Arrangements for networking
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Electromagnetism (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Computing Systems (AREA)
- Optical Communication System (AREA)
- Communication Control (AREA)
Abstract
The invention discloses an FPGA-based digital processing and control system, comprising a signal collection module, a data transmission module and a signal processing module, wherein the data transmission module comprises an optical fiber data transmission board, an optical fiber backboard 1, and an optical fiber backboard 2; the optical fiber data transmission board comprises an FPGA, an optical fiber interface 1, an optical fiber interface 2, an optical fiber interface 3 and an optical fiber interface 4; the signal processing module comprises a DSP board 1 and a DSP board 2; the signal collection module is in connection with the data transmission module through a PMC interface, and is used for collecting 48 paths of complex baseband signals; the data transmission module is in bidirectional connection with the signal processing module through the PMC interface, and is used for transmitting echo data transmitted by the signal collection module among boards through the PMC interface and an optical fiber channel; the optical fiber data transmission board is in connection with the optical fiber backboard 1 by optical fibers through the optical fiber interface 1 and the optical fiber interface 2, is in connection with the optical fiber backboard 2 by optical fibers through the optical fiber interface 3 and the optical fiber interface 4, and is responsible for system signal concrete transmission; the signal processing module is used for data signal processing.
Description
Technical field
The invention belongs to the concrete application of digital processing field, particularly relate to a kind of digital processing based on FPGA and control system.
Background technology
In modern digital signal processing field, the transmission quantity of data is doubled and redoubled, and the requirement of real-time is more and more higher.Then data transmission at a high speed just becomes the key component realizing real-time digital signal processing system, it does not have the guarantee of high speed data transfer, cannot enter data into process system timely, and then cannot realize real-time signal processing.Carrying out data exchange frequently by various high speed interconnection structure between digital signal processing module, the high speed interconnection structure that current industry is conventional is varied, is respectively arranged with its pluses and minuses and the occasion being suitable for.It seems that at present, the developing direction of high speed data transfer is that point-to-point transmission replaces conventional bus, ultrahigh speed serial transmission to replace parallel transmission, optical fiber to replace copper cash.And why optical fiber replaces copper cash to be based on the series of advantages of optical fiber transmission technique: bandwidth, transmission capacity are big, loss is little, electromagnetism interference is good and long transmission distance.
In high-speed digital video camera system, particularly in radar process system, constantly promote with speed and the appearance of multi-processor structure along with the function of primary processor constantly strengthens, the requirement of message transmission rate is also more and more higher.No matter it is the data exchange between system, or the data exchange between system inner treater chip and peripheral components, it is desirable that at a high speed data transfer mode reliably.In recent years, digital signal processor (abbreviation DSP) achieved and developed rapidly, and its operating frequency is more and more higher, and disposal ability is more and more stronger.For the C6455 signal processor that TI company releases, its operating frequency reaches 1GHz, and monolithic disposal ability reaches 8000MIPS.The raising at full speed of processor working frequency so that external bus speed is increasingly becoming the bottleneck of whole signal processing system.Data can be provided timely and effectively for process at high speed, just become the key that can whole real time processing system realize.Therefore, studying the high-speed data treatment technology that current industry is widely used, select suitable Highspeed Data Transmission Technology according to the demand of system, the realization for whole real-time system is very important.
Traditional optical-fiber network achieves internodal entirely photochemical, but still adopts electrical part at network node place, limits the further raising of current communication network main line total capacity.All-optical network replaces electrical nodes with optical node, is also entirely photochemical between node, and information is transmitted and exchange all the time in the form of light, and the process of user profile is no longer undertaken by switch by bit, but determines route according to its wavelength.The present invention is based on all optical network technology, there is the feature of the good transparency, opening, compatibility, reliability, extensibility, and it is provided that huge bandwidth, vast capacity, high processing speed, the relatively low bit error rate, network structure is simple, networking is very flexible, it is possible to increase new node at any time without exchange and the equipment of process of installing signal.
Summary of the invention
In order to promote the message transmission rate of communication equipment further.It is an object of the invention to provide a kind of digital processing based on FPGA and control system, this invention has the feature of the good transparency, opening, compatibility, reliability, extensibility, and it is provided that huge bandwidth, vast capacity, high processing speed, the relatively low bit error rate, network structure is simple, networking is very flexible, it is possible to increase new node at any time without exchange and the equipment of process of installing signal.
In order to realize said system, the present invention adopts the technical scheme that:
A kind of digital processing based on FPGA and control system, it is characterized in that this hardware is made up of signal acquisition module, data transmission module, signal processing module, wherein data transmission module includes: fiber count passes plate, optical fiber backboard 1, optical fiber backboard 2, fiber count passes plate and includes: FPGA, optical fiber interface 1, optical fiber interface 2, optical fiber interface 3, optical fiber interface 4, and signal processing module includes: DSP processes plate 1, DSP processes plate 2；Concrete, signal acquisition module is according to the corresponding 48 tunnel baseband complex signal of timing sequence collection, then each 24 tunnels of upper and lower wave beam are divided the data into again, wherein optical fiber backboard 1 is passed on 24 tunnels at the high elevation angle, optical fiber backboard 2 is passed on 24 tunnels at the low elevation angle, last two pieces of optical fiber backboards both pass through PN3 transmit data to dsp board carry out keystone, pulse pressure process；FPGA processes plate by link mouth or EMIFB or pci interface controller with DSP and carries out data exchange, receive passage and first pass through the data that RocketIO reception status control module reception is sent by optical fiber, what then data carried out predetermined format unpacks process, first it is remove frame head and trailer information recovers data, data buffer storage is entered FIFO in sheet again, carry out rate-matched and data buffering, transfer data to DSP eventually through the path on PMC connector and process plate；Sendaisle first receives motherboard data, carries out buffer memory and rate-matched with FIFO in sheet, then packs in a pre-defined format, sends status control module finally by RocketIO and data are sent into optical-fibre channel.
In this digital processing and control system, described data transmission module is passed plate by fiber count, optical fiber backboard 1, optical fiber backboard 2 are constituted；Fiber count passes plate and adopts the DSPEED FIBRE_Q2000 plate based on PMC agreement, its composition includes: FPGA, optical fiber interface 1, optical fiber interface 2, optical fiber interface 3, optical fiber interface 4, fiber count passes plate and adopts four tunnel optical-fibre channels to carry out high speed data transfer by optical fiber, and every paths transmits I, Q two-way of upper and lower wave beam respectively；Four road universal optical fibre numbers pass plate, are based on the standard PMC backboard of extensive FPGA and four road able to programme optical fiber interface.Can providing the pci interface of the highest 64bit/66MHz, the link mouth of four road 75MB/s, and the EMIFB mouth of 266MB/s, for the high-speed interconnection of data with motherboard and whole system.Wherein, FPGA adopts the VertexIIPro chip of Xilinx company, the RocketIO HSSI High-Speed Serial Interface of its advanced person can directly drive bidirectional optical fiber transceiver module, single-path optical fiber module is up to 1Gbit/s, four roads work up to 4Gbit/s simultaneously, each road can full duplex work, and FPGA carries out data exchange by link mouth or EMIFB or pci interface controller with motherboard (C6455 plate), and FPGA comprises logic module in sheet, sendaisle and reception passage；Described data transmission module may be used for the interconnection between high speed, remote plate, between cabinet, the such as interconnection between multiple CPCI cabinets, the interconnection of process system and external optical fiber interface disk battle array, maximum interconnection distance up to 400～500 meters, have efficiently, at a high speed, reliable advantage.
nullIn this digital processing and control system，Described DSP processes plate and adopts DSPEED_Q6455 general signal processing module，Veneer configures four TI company up-to-date dsp chip-TMS320C6455，Peak value disposal ability is 4 × 8000MIPS/9600MIPS，Interconnection between DSP passes at a high speed speed agreement-SRIO(SerialRapidIO based on novel serial point to point) agreement，In plate, the continuous transmission effective bandwidth between DSP is 1.72GB/s(full duplex)，Each DSP at most can external 512MBDDRII-SDRAM，Continuous access speed reaches as high as 1.8GB/s，The EMIFA of each DSP meets 4MBFlash、8MBSBSRAM，And with 64 bit synchronous mode and FPGA interface，32 of each DSP、The pci interface of 33/66MHz is interconnected by cpci bus and mutual with main frame；DSP processes also has two PMC daughterboard interface on plate, wherein PCI part is 32,33/66MHz pattern, and defines 20 couples of difference IO respectively on JN3 and JN4, if pressing FPDP protocol transmission with the source method of synchronization, each PMC total bandwidth is up to 3.2GB/s.Described DSP processes plate outbound data coffret three kinds: the first is SRIO, and on J3, the SRIO interface of 44 passages of definition, is operable with 1.25Gbps, and continuous transmission bandwidth is 640MB/s(full duplex)；The second is to realize interconnection at a high speed by the self-defined IO of the J4/J5 of CPCI, has 160 single-ended IO or 80 couples of difference IO, if pressing FPDP protocol transmission with the source method of synchronization, total bandwidth is up to 6.4GB/s；The third is the gigabit ethernet interface on front panel, and continuous transmission speed can arrive 120MB/s.
In this digital processing and control system, in described FPGA sheet, logic module includes: control module that RocketI/O initializes control module, RocketI/O resets, RocketI/O transmitting terminal status control module, RocketI/O receiving-end state control FIFO in module, sheet and control module；Wherein, RocketI/O initialization controls module and has been used for the working method of RocketI/O kernel and the setting of pattern；It is the requirement to reset signal according to RocketI/O transmitting terminal and receiving terminal that RocketI/O reset controls the function of module, produces receiving terminal reset signal and the transmitting terminal reset signal of RocketI/O respectively；The function of RocketI/O transmitting terminal status control module has: (1) tranmitting data register verification sequence, (2) constantly detection sends and enables signal, determine whether that data require over fiber-optic transfer, (3) if data need to send, RocketI/O sends the data that status control module then sons and younger brothers then reads in FPGA sheet in FIFO automatically, and data are added frame head, and write data into the transmitting terminal of RocketI/O, (4) according to data effective marker position, send the data volume of this transmission, finally, frame end mark is added for data；RocketIO receiving-end state controls the function of module: the data that RocketIO receiving terminal is received by (1) detect, if be detected that frame head mark (condition code 0xFBFB), then RocketIO receiving-end state controls module by FIFO in the sheet of the effectively transmission data write FPGA received, (2) detection frame end mark (condition code 0xFDFD), judge the end once transmitted, and send this reception end signal REC_COMPLETE.
In this digital processing and control system, described RocketI/O transmitting terminal status control module, it is characterised in that the transmission State Transferring flow process of described RocketI/O transmitting terminal status control module is as follows:
Step 1, reset；
Step 2, tranmitting data register checking sequence condition code 0xBC0；
Step 3, judging SEND_ENA value, SEND_ENA=1 then forwards step 4 to, and SEND_ENA=0 then forwards step 2 to；
Step 4, interpolation frame head mark 1 condition code 0xFBFB；
Step 5, interpolation frame head mark 2 condition code 0xFBFB；
Step 6, transmission transmission data；
Step 7, send last data；
Step 8, interpolation postamble mark 1 condition code 0xFDFD；
Step 9, interpolation postamble mark 2 condition code 0xFDFD；
Step 10, tranmitting data register checking sequence condition code 0xBC50, forward step 2 to.
In this digital processing and control system, described RocketI/O receiving-end state controls module, it is characterised in that described receiving-end state flow path switch is as follows:
Step 1, reset；
Step 2, detection receive data:
Step 3, removing frame head mark condition code 0xFBFB；
Step 4, reception transmission data；
Step 5, reception done state, forward step 2 to.
The invention has the beneficial effects as follows:
A kind of digital processing based on FPGA and control system, it is characterized in that, this system is made up of signal acquisition module, data transmission module, signal processing module, wherein data transmission module includes: fiber count passes plate, optical fiber backboard 1, optical fiber backboard 2, fiber count passes plate and includes: FPGA, optical fiber interface 1, optical fiber interface 2, optical fiber interface 3, optical fiber interface 4, and signal processing module includes: DSP processes plate 1, DSP processes plate 2；The present invention adopts optical fiber data transferring technology, adopt the VirtexIIPro Series FPGA design of Xilinx company, the serial transceiver RocketIO of this FPGA Embedded can realize the high-speed serial data transmission between plate, carry out the design of coffret module, including Interface design and the realization of the ddr mode between EMIF Interface design and the FPGA between FPGA and DSP.The present invention has simple in construction, and image is clear, and interactivity is good, the feature that intelligence degree is high.The present invention is based on all optical network technology, there is the feature of the good transparency, opening, compatibility, reliability, extensibility, and it is provided that huge bandwidth, vast capacity, high processing speed, the relatively low bit error rate, network structure is simple, networking is very flexible, it is possible to increase new node at any time without exchange and the equipment of process of installing signal.
Accompanying drawing explanation
Below in conjunction with the drawings and specific embodiments, the present invention is further explained.
Fig. 1 is based on digital processing and the Control system architecture block diagram of FPGA；
Fig. 2 is DSPEED_Q6455 board structure block diagram；
Fig. 3 is optical fiber backboard structured flowchart；
Fig. 4 is the transmission State Transferring flow chart of RocketI/O transmitting terminal status control module；
Fig. 5 is that RocketI/O receiving-end state controls module status flow path switch figure；
Fig. 6 is the physical connection figure of source sync cap；
Fig. 7 is inter-board interface system block diagram.
Detailed description of the invention
The specific embodiment of the present invention is: described a kind of digital processing based on FPGA and control system, signal acquisition module is connected by PMC interface with data transmission module, data transmission module is bi-directionally connected with the logical PMC interface of signal processing module, fiber count is passed plate and is connected with optical fiber backboard 1 by optical fiber interface 1, optical fiber interface 2 by optical fiber, optical fiber be bi-directionally connected with optical fiber backboard 2 by optical fiber interface 3, optical fiber interface 4；Concrete, signal acquisition module is according to the corresponding 48 tunnel baseband complex signal of timing sequence collection, then each 24 tunnels of upper and lower wave beam are divided the data into again, wherein optical fiber backboard 1 is passed on 24 tunnels at the high elevation angle, optical fiber backboard 2 is passed on 24 tunnels at the low elevation angle, last two pieces of optical fiber backboards both pass through PN3 transmit data to dsp board carry out keystone, pulse pressure process；FPGA processes plate by link mouth or EMIFB or pci interface controller with DSP and carries out data exchange, receive passage and first pass through the data that RocketIO reception status control module reception is sent by optical fiber, what then data carried out predetermined format unpacks process, first it is remove frame head and trailer information recovers data, data buffer storage is entered FIFO in sheet again, carry out rate-matched and data buffering, transfer data to DSP eventually through the path on PMC connector and process plate；Sendaisle first receives motherboard data, carries out buffer memory and rate-matched with FIFO in sheet, then packs in a pre-defined format, sends status control module finally by RocketIO and data are sent into optical-fibre channel.
Fig. 1 is based on digital processing and the Control system architecture block diagram of FPGA, this system is made up of signal acquisition module, data transmission module, signal processing module, wherein data transmission module includes: fiber count passes plate, optical fiber backboard 1, optical fiber backboard 2, fiber count passes plate and includes: FPGA, optical fiber interface 1, optical fiber interface 2, optical fiber interface 3, optical fiber interface 4, and signal processing module includes: DSP processes plate 1, DSP processes plate 2；Signal acquisition module is connected by PMC interface with data transmission module, for gathering 48 road complex baseband signals, data transmission module and signal processing module are bi-directionally connected by PMC interface, echo data for signal acquisition module being transmitted is undertaken transmitting between plate by PMC and optical-fibre channel, fiber count is passed plate and is connected with optical fiber backboard 1 by optical fiber interface 1, optical fiber interface 2 by optical fiber, being bi-directionally connected with optical fiber backboard 2 by optical fiber interface 3, optical fiber interface 4 by optical fiber, that is responsible for system signal specifically transmits work；Signal processing module is for the processing of data signal.
nullFig. 2 is DSPEED_Q6455 board structure block diagram，Described DSP processes plate and adopts DSPEED_Q6455 general signal processing module，Veneer configures four TI company up-to-date dsp chip-TMS320C6455，Peak value disposal ability is 4 × 8000MIPS/9600MIPS，Interconnection between DSP passes at a high speed speed agreement-SRIO(SerialRapidIO based on novel serial point to point) agreement，In plate, the continuous transmission effective bandwidth between DSP is 1.72GB/s(full duplex)，Each DSP at most can external 512MBDDRII-SDRAM，Continuous access speed reaches as high as 1.8GB/s，The EMIFA of each DSP meets 4MBFlash、8MBSBSRAM，And with 64 bit synchronous mode and FPGA interface，32 of each DSP、The pci interface of 33/66MHz is interconnected by cpci bus and mutual with main frame；DSP processes also has two PMC daughterboard interface on plate, wherein PCI part is 32,33/66MHz pattern, and defines 20 couples of difference IO respectively on JN3 and JN4, if pressing FPDP protocol transmission with the source method of synchronization, each PMC total bandwidth is up to 3.2GB/s.Described DSP processes plate outbound data coffret three kinds: the first is SRIO, and on J3, the SRIO interface of 44 passages of definition, is operable with 1.25Gbps, and continuous transmission bandwidth is 640MB/s(full duplex)；The second is to realize interconnection at a high speed by the self-defined IO of the J4/J5 of CPCI, has 160 single-ended IO or 80 couples of difference IO, if pressing FPDP protocol transmission with the source method of synchronization, total bandwidth is up to 6.4GB/s；The third is the gigabit ethernet interface on front panel, and continuous transmission speed can arrive 120MB/s.
Fig. 3 is optical fiber backboard structured flowchart, and described data transmission module is passed plate by fiber count, optical fiber backboard 1, optical fiber backboard 2 are constituted；Fiber count passes plate and adopts the DSPEED FIBRE_Q2000 plate based on PMC agreement, its composition includes: FPGA, optical fiber interface 1, optical fiber interface 2, optical fiber interface 3, optical fiber interface 4, fiber count passes plate and adopts four tunnel optical-fibre channels to carry out high speed data transfer by optical fiber, and every paths transmits I, Q two-way of upper and lower wave beam respectively；Four road universal optical fibre numbers pass plate, are based on the standard PMC backboard of extensive FPGA and four road able to programme optical fiber interface.Can providing the pci interface of the highest 64bit/66MHz, the link mouth of four road 75MB/s, and the EMIFB mouth of 266MB/s, for the high-speed interconnection of data with motherboard and whole system.Wherein, FPGA adopts the VertexIIPro chip of Xilinx company, the RocketIO HSSI High-Speed Serial Interface of its advanced person can directly drive bidirectional optical fiber transceiver module, single-path optical fiber module is up to 1Gbit/s, four roads work up to 4Gbit/s simultaneously, each road can full duplex work, and FPGA carries out data exchange by link mouth or EMIFB or pci interface controller with motherboard (C6455 plate), and FPGA comprises logic module in sheet, sendaisle and reception passage；Described data transmission module may be used for the interconnection between high speed, remote plate, between cabinet, the such as interconnection between multiple CPCI cabinets, the interconnection of process system and external optical fiber interface disk battle array, maximum interconnection distance up to 400～500 meters, have efficiently, at a high speed, reliable advantage.
Fig. 4 is the transmission State Transferring flow chart of RocketI/O transmitting terminal status control module, and the transmission State Transferring flow process of described RocketI/O transmitting terminal status control module is as follows:
Step 1, reset；
Step 2, tranmitting data register checking sequence condition code 0xBC0；
Step 3, judging SEND_ENA value, SEND_ENA=1 then forwards step 4 to, and SEND_ENA=0 then forwards step 2 to；
Step 4, interpolation frame head mark 1 condition code 0xFBFB；
Step 5, interpolation frame head mark 2 condition code 0xFBFB；
Step 6, transmission transmission data；
Step 7, send last data；
Step 8, interpolation postamble mark 1 condition code 0xFDFD；
Step 9, interpolation postamble mark 2 condition code 0xFDFD；
Step 10, tranmitting data register checking sequence condition code 0xBC50, forward step 2 to..
Fig. 5 is that RocketI/O receiving-end state controls module status flow path switch figure, and described receiving-end state flow path switch is as follows:
Step 1, reset；
Step 2, detection receive data:
Step 3, removing frame head mark condition code 0xFBFB；
Step 4, reception transmission data；
Step 5, reception done state, forward step 2 to.
Fig. 6 be the physical connection of the high speed data transfer between physical connection figure, the FPGA of source sync cap has data, with data clock sent along and data instruction frame signal, wherein the bit wide of data can be customized by user.Host-host protocol is self-defining, realizes being properly received data by the instruction frame signal sent in company with data one piece, it is achieved get up fairly simple.Wherein signal transmits with LVDS differential lines, and suffix is the N end for differential lines of No. #.TCLK and TCLK# is tranmitting data register, and RCLK and RCLK# is for receiving clock；TFRAME and TFRAME# is the data instruction frame signal sent, and RFRAME and RFRAME# is the data instruction frame signal received；TDATA [N-1:0] and TDATA# [N-1:0] is the N position datawire sent, and RDATA [N-1:0] and RDATA# [N-1:0] is the N position datawire received.Principle according to source synchronous transfer, will reach the delay that clock is identical with data, and in the design of PCB, the cabling of each group of data transmission path to ensure strict conformance.
Fig. 7, signal acquiring system adopts the differential source method of synchronization to realize to the high speed data transfer of Optical Fiber Timing plate, host-host protocol is according to the transmission requirement of the system of process, physical connection has echo data, indicates frame signal data wire with road clock and data, because LVDS has the feature of high speed, low-power and good in anti-interference performance, it is very suitable for as the standard of data transmission interface between plate, so all signals all transmit with LVDS differential lines.
General technical staff of the technical field of the invention also will readily appreciate that in addition to the foregoing, illustrates at this and the specific embodiment of diagram can change combination further.Illustrate although the present invention gives diagram with regard to its preferred embodiment, but person skilled in the art it is recognized that in the spirit and scope of invention defined in the attached claims, also can make multiple change and variation to the present invention.
Claims (6)
1. the digital processing based on FPGA and control system, it is characterized in that this system is made up of signal acquisition module, data transmission module, signal processing module, wherein data transmission module includes: fiber count passes plate, optical fiber backboard 1, optical fiber backboard 2, fiber count passes plate and includes: FPGA, optical fiber interface 1, optical fiber interface 2, optical fiber interface 3, optical fiber interface 4, and signal processing module includes: DSP processes plate 1, DSP processes plate 2；Concrete, signal acquisition module is according to the corresponding 48 tunnel baseband complex signal of timing sequence collection, then each 24 tunnels of upper and lower wave beam are divided the data into again, wherein optical fiber backboard 1 is passed on 24 tunnels at the high elevation angle, optical fiber backboard 2 is passed on 24 tunnels at the low elevation angle, last two pieces of optical fiber backboards both pass through PN3 transmit data to dsp board carry out keystone, pulse pressure process；Within the system, signal acquisition module is connected by PMC interface with data transmission module, data transmission module and signal processing module are bi-directionally connected by PMC interface, fiber count is passed plate and is connected with optical fiber backboard 1 by optical fiber interface 1, optical fiber interface 2 by optical fiber, optical fiber be bi-directionally connected with optical fiber backboard 2 by optical fiber interface 3, optical fiber interface 4.
2. the digital processing based on FPGA as claimed in claim 1 and control system, it is levied and is in that, described data transmission module is passed plate by fiber count, optical fiber backboard 1, optical fiber backboard 2 are constituted；Fiber count passes plate and adopts the DSPEED-FIBRE_Q2000 plate based on PMC agreement, its composition includes: FPGA, optical fiber interface 1, optical fiber interface 2, optical fiber interface 3, optical fiber interface 4, fiber count passes plate and adopts four tunnel optical-fibre channels to carry out high speed data transfer by optical fiber, and every paths transmits I, Q two-way of upper and lower wave beam respectively；Wherein, FPGA adopts the VertexIIPro chip of Xilinx company, the RocketIO HSSI High-Speed Serial Interface of its advanced person can directly drive bidirectional optical fiber transceiver module, single-path optical fiber module is up to 1Gbit/s, four roads work up to 4Gbit/s simultaneously, each road can full duplex work, and FPGA carries out data exchange by link mouth or EMIFB or pci interface controller with motherboard (C6455 plate), and FPGA comprises logic module in sheet, sendaisle and reception passage.
null3. DSP as claimed in claim 1 processes plate and adopts DSPEED_Q6455 general signal processing module，Veneer configures four TI company up-to-date dsp chip-TMS320C6455，Peak value disposal ability is 4 × 8000MIPS/9600MIPS，Interconnection between DSP passes at a high speed speed agreement-SRIO(SerialRapidIO based on novel serial point to point) agreement，In plate, the continuous transmission effective bandwidth between DSP is 1.72GB/s(full duplex)，Each DSP at most can external 512MBDDRII-SDRAM，Continuous access speed reaches as high as 1.8GB/s，The EMIFA of each DSP meets 4MBFlash、8MBSBSRAM，And with 64 bit synchronous mode and FPGA interface，32 of each DSP、The pci interface of 33/66MHz is interconnected by cpci bus and mutual with main frame；DSP processes also has two PMC daughterboard interface on plate, wherein PCI part is 32,33/66MHz pattern, and defines 20 couples of difference IO respectively on JN3 and JN4, if pressing FPDP protocol transmission with the source method of synchronization, each PMC total bandwidth is up to 3.2GB/s.
4. in FPGA sheet as claimed in claim 2, logic module includes: control module that RocketI/O initializes control module, RocketI/O resets, RocketI/O transmitting terminal status control module, RocketI/O receiving-end state control FIFO in module, sheet and control module；Wherein, RocketI/O initialization controls module and has been used for the working method of RocketI/O kernel and the setting of pattern；It is the requirement to reset signal according to RocketI/O transmitting terminal and receiving terminal that RocketI/O reset controls the function of module, produces receiving terminal reset signal and the transmitting terminal reset signal of RocketI/O respectively；The function of RocketI/O transmitting terminal status control module has: (1) tranmitting data register verification sequence, (2) constantly detection sends and enables signal, determine whether that data require over fiber-optic transfer, (3) if data need to send, RocketI/O sends the data that status control module then sons and younger brothers then reads in FPGA sheet in FIFO automatically, and data are added frame head, and write data into the transmitting terminal of RocketI/O, (4) according to data effective marker position, send the data volume of this transmission, finally, frame end mark is added for data；RocketIO receiving-end state controls the function of module: the data that RocketIO receiving terminal is received by (1) detect, if be detected that frame head mark (condition code 0xFBFB), then RocketIO receiving-end state controls module by FIFO in the sheet of the effectively transmission data write FPGA received, (2) detection frame end mark (condition code 0xFDFD), judge the end once transmitted, and send this reception end signal REC_COMPLETE.
5. RocketI/O transmitting terminal status control module as claimed in claim 4, it is characterised in that the transmission State Transferring flow process of described RocketI/O transmitting terminal status control module is as follows:
Step 1, reset；
Step 2, tranmitting data register checking sequence condition code 0xBC0；
Step 3, judging SEND_ENA value, SEND_ENA=1 then forwards step 4 to, and SEND_ENA=0 then forwards step 2 to；
Step 4, interpolation frame head mark 1 condition code 0xFBFB；
Step 5, interpolation frame head mark 2 condition code 0xFBFB；
Step 6, transmission transmission data；
Step 7, send last data；
Step 8, interpolation postamble mark 1 condition code 0xFDFD；
Step 9, interpolation postamble mark 2 condition code 0xFDFD；
Step 10, tranmitting data register checking sequence condition code 0xBC50, forward step 2 to.
6. RocketI/O receiving-end state as claimed in claim 4 controls module, it is characterised in that described receiving-end state flow path switch is as follows:
Step 1, reset；
Step 2, detection receive data:
Step 3, removing frame head mark condition code 0xFBFB；
Step 4, reception transmission data；
Step 5, reception done state, forward step 2 to.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610154943.9A CN105763258A (en) | 2016-03-18 | 2016-03-18 | FPGA-based digital processing and control system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610154943.9A CN105763258A (en) | 2016-03-18 | 2016-03-18 | FPGA-based digital processing and control system |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN105763258A true CN105763258A (en) | 2016-07-13 |
Family
ID=56333451
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610154943.9A Pending CN105763258A (en) | 2016-03-18 | 2016-03-18 | FPGA-based digital processing and control system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN105763258A (en) |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107632357A (en) * | 2017-10-19 | 2018-01-26 | 东莞中子科学中心 | A kind of multimode fibre signal is fanned out to mechanism |
| CN107643989A (en) * | 2016-07-22 | 2018-01-30 | 北京中科信电子装备有限公司 | One kind is based on pci bus agreement dual fiber ring road redundancy structure Communication Card |
| CN109617607A (en) * | 2018-12-19 | 2019-04-12 | 贵州航天电子科技有限公司 | A kind of template phased array target seeker digital beam froming processor |
| CN109842443A (en) * | 2019-01-31 | 2019-06-04 | 北京无线电测量研究所 | A kind of high speed fibre transmission method and system based on FPGA |
| CN110166127A (en) * | 2019-04-30 | 2019-08-23 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | The method of high speed fibre backboard general purpose processing block optical link |
| CN111147522A (en) * | 2020-01-08 | 2020-05-12 | 中国船舶重工集团公司第七二四研究所 | Multi-channel RocktIO protocol and FC protocol real-time conversion method |
| CN111176619A (en) * | 2019-12-24 | 2020-05-19 | 广东高云半导体科技股份有限公司 | FPGA execution flow control method and device, computer equipment and storage medium |
| CN111614401A (en) * | 2020-05-20 | 2020-09-01 | 中车株洲电力机车研究所有限公司 | Power unit communication expansion device |
| CN112946580A (en) * | 2021-01-14 | 2021-06-11 | 无锡国芯微电子系统有限公司 | Multiprocessor cooperative radiation source frequency parameter estimation device and method |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101102197A (en) * | 2007-08-10 | 2008-01-09 | 北京理工大学 | Scalable DSPEED-DSP_Q6455 signal processing board based on switcher |
| CN101969378A (en) * | 2010-10-26 | 2011-02-09 | 北京理工大学 | Switchboard based extensible DSPEED-DSP (Digital Signal Processor)_Q6474 signal processing board |
| CN103078650A (en) * | 2013-01-06 | 2013-05-01 | 中国电子科技集团公司第十研究所 | High speed data transmission receiver |
-
2016
- 2016-03-18 CN CN201610154943.9A patent/CN105763258A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101102197A (en) * | 2007-08-10 | 2008-01-09 | 北京理工大学 | Scalable DSPEED-DSP_Q6455 signal processing board based on switcher |
| CN101969378A (en) * | 2010-10-26 | 2011-02-09 | 北京理工大学 | Switchboard based extensible DSPEED-DSP (Digital Signal Processor)_Q6474 signal processing board |
| CN103078650A (en) * | 2013-01-06 | 2013-05-01 | 中国电子科技集团公司第十研究所 | High speed data transmission receiver |
Non-Patent Citations (4)
| Title |
|---|
| ZHANGXK: "PMC四通道光纤数传板DSPEED-QFIBRE_Q2000", 《新浪博客：HTTP://BLOG.SINA.COM.CN/S/BLOG_562538D20100HPR1.HTML》 * |
| ZHANGXK: "四C6455高速信号处理板DSPEED-DSP_Q6455", 《新浪博客：HTTP://BLOG.SINA.COM.CN/S/BLOG_562538D20100HNC9.HTML》 * |
| 杨欣然等: "多通道实时阵列信号处理系统的设计", 《电子设计工程》 * |
| 江培华等: "基于RocketI/O的光纤数传板设计", 《微计算机信息》 * |
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN107643989A (en) * | 2016-07-22 | 2018-01-30 | 北京中科信电子装备有限公司 | One kind is based on pci bus agreement dual fiber ring road redundancy structure Communication Card |
| CN107643989B (en) * | 2016-07-22 | 2022-05-10 | 北京中科信电子装备有限公司 | Dual-optical-fiber loop redundancy structure communication board card based on PCI bus protocol |
| CN107632357A (en) * | 2017-10-19 | 2018-01-26 | 东莞中子科学中心 | A kind of multimode fibre signal is fanned out to mechanism |
| CN107632357B (en) * | 2017-10-19 | 2019-08-02 | 东莞中子科学中心 | A kind of multimode fibre signal is fanned out to mechanism |
| CN109617607A (en) * | 2018-12-19 | 2019-04-12 | 贵州航天电子科技有限公司 | A kind of template phased array target seeker digital beam froming processor |
| CN109842443A (en) * | 2019-01-31 | 2019-06-04 | 北京无线电测量研究所 | A kind of high speed fibre transmission method and system based on FPGA |
| CN110166127A (en) * | 2019-04-30 | 2019-08-23 | 西南电子技术研究所（中国电子科技集团公司第十研究所） | The method of high speed fibre backboard general purpose processing block optical link |
| CN111176619A (en) * | 2019-12-24 | 2020-05-19 | 广东高云半导体科技股份有限公司 | FPGA execution flow control method and device, computer equipment and storage medium |
| CN111147522A (en) * | 2020-01-08 | 2020-05-12 | 中国船舶重工集团公司第七二四研究所 | Multi-channel RocktIO protocol and FC protocol real-time conversion method |
| CN111614401A (en) * | 2020-05-20 | 2020-09-01 | 中车株洲电力机车研究所有限公司 | Power unit communication expansion device |
| CN111614401B (en) * | 2020-05-20 | 2021-08-24 | 中车株洲电力机车研究所有限公司 | Power unit communication expansion device |
| CN112946580A (en) * | 2021-01-14 | 2021-06-11 | 无锡国芯微电子系统有限公司 | Multiprocessor cooperative radiation source frequency parameter estimation device and method |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105763258A (en) | FPGA-based digital processing and control system | |
| US6862293B2 (en) | Method and apparatus for providing optimized high speed link utilization | |
| KR920002900B1 (en) | Data link extension for data communication networks | |
| JPH025665A (en) | Adaptor | |
| CN109120624A (en) | A kind of more plane loose coupling high band wide data exchange systems | |
| CN102253914B (en) | Data transmitting and processing method and device and equipment interface | |
| CN103970704A (en) | Optical fiber bus hardware system based on Rapid IO protocol | |
| CN103942014A (en) | FC-AE-1553 protocol interface card storage mapping device and storage mapping method | |
| US6483849B1 (en) | Network transceiver having a LED interface operable in parallel and serial modes | |
| CN207780553U (en) | A kind of PXIe controller remote control systems based on optical fiber | |
| CN105281783A (en) | Signal decoding unit based on FPGA (Field Programmable Gate Array) and DSP (Digital Signal Processor) and realization method for signal decoding unit based on FPGA and DSP | |
| CN105262789A (en) | FPGA (Field Programmable Gate Array)-based MAC (Media Access Control) layer to MAC layer communication system and control method | |
| CN114442514A (en) | USB3.0/3.1 control system based on FPGA | |
| CN107943733A (en) | The interconnected method of parallel bus between a kind of veneer | |
| CN104660989A (en) | Optical fiber-to-full configuration type Camera link real-time image optical transceiver based on FPGA | |
| CN101106504A (en) | Distributed communication system for intelligent independent robot based on CAN bus | |
| CN102983998A (en) | Novel data acquiring system SuperCAP | |
| CN205304857U (en) | 10, 000, 000, 000 light network switch | |
| CN107168045A (en) | A kind of communication redundancy control system based on EtherCAT | |
| CN112653638B (en) | Device for switching routes of multiple paths of intermediate frequencies and baseband at high speed and communication method thereof | |
| US20040078709A1 (en) | System, method, and product for providing a test mechanism within a system area network device | |
| CN111614533B (en) | POWERLINK slave station module capacity expansion system and interaction method of slave station and bus master node | |
| CN104639898B (en) | A kind of multifunctional service transmitting device based on Rapidio exchange networks | |
| WO2016141724A1 (en) | Real-time bus and implementation method therefor | |
| CN105488010B (en) | A kind of backboard real-time synchronization interface protocol |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20160713 |