WO2016141724A1 - Real-time bus and implementation method therefor - Google Patents

Real-time bus and implementation method therefor Download PDF

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WO2016141724A1
WO2016141724A1 PCT/CN2015/093681 CN2015093681W WO2016141724A1 WO 2016141724 A1 WO2016141724 A1 WO 2016141724A1 CN 2015093681 W CN2015093681 W CN 2015093681W WO 2016141724 A1 WO2016141724 A1 WO 2016141724A1
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bus
boards
board
downlink
buses
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PCT/CN2015/093681
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French (fr)
Chinese (zh)
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吕建新
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烽火通信科技股份有限公司
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04LTRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L12/00Data switching networks
    • H04L12/28Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
    • H04L12/40Bus networks

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  • the present invention relates to the field of communications technologies, and in particular, to a real-time bus and an implementation method thereof.
  • Some large-scale electronic devices in the communication field usually consist of multiple boards that are inserted into the backplane.
  • the boards are interconnected through the backplane connection, especially in large-capacity optical transmission equipment.
  • the number of boards is usually more than 30. It is very difficult to use one bus to communicate between all boards, especially for some information with low information and high real-time requirements.
  • the existing bus technology has the following problems:
  • the technical problem to be solved by the invention is to solve the complex and real-time implementation of the existing bus technology protocol.
  • Low cost, high backplane and connector cost to reduce the number and cost of signal interconnections between large numbers of boards in large devices, and to meet the real-time requirements of signals between boards.
  • the technical solution adopted by the present invention is to provide a real-time bus, including an uplink bus, a downlink bus, a system clock, and a data forwarding unit.
  • the uplink bus is composed of a plurality of first buses, each of which is connected to a plurality of boards, and each of the first buses determines a transmission rate and a time slot according to the number of boards connected thereto, and adopts Time-division multiplexing is used to transfer data of each board connected to the public board.
  • the downlink bus is composed of a plurality of second buses having the same transmission rate and content, and the second bus is in one-to-one correspondence with the first bus, and is respectively connected to the boards on the first bus;
  • the time slot of the second bus is divided according to the number of all the boards;
  • the system clock is used for synchronizing and sampling data of the bus, and is composed of a frame positioning clock and a sampling clock. Each board uses a sampling clock to transmit and receive data. The time slot segments of different boards are positioned by a frame positioning clock.
  • the data forwarding unit is located on the public board, and receives the information sent by the board on the uplink bus, and the received information is summarized and forwarded to the corresponding time slot of each board on the downlink bus. on.
  • each of the first buses is connected with m-blocks, the rate of the first bus is 1/n sampling clock frequency, n is the total number of device boards/m; the second bus The rate is equal to the sampling clock frequency.
  • the number of boards connected to each of the first buses is different, the rate of the first bus is 1/n sampling clock frequency, n is the total number of device boards / the connection on the first bus The number of boards; the rate of the second bus is equal to the sampling clock frequency.
  • each board In the real-time bus, each board outputs the information of the board in the corresponding time slot segment, and is transmitted to the data forwarding unit on the public board through each uplink bus, and the remaining period is high impedance; the data is The forwarding unit forwards the downlink data of all the boards to the downlink bus, and each board receives the corresponding downlink data in the time slot corresponding to the downlink bus.
  • the invention also provides a real-time bus implementation method, the implementation method comprising the following steps:
  • Step 201 The uplink bus is composed of a plurality of first buses, and the first bus is connected to a plurality of boards and connected to a common board;
  • Step 202 The downlink bus is composed of a plurality of second buses having the same transmission rate and content, and the second bus is in one-to-one correspondence with the first bus, and the second bus is respectively connected to a plurality of boards and The public board is connected;
  • Step 203 The boards output the information of the board in the corresponding time slot segments, and transmit the information to the data forwarding unit on the public board through the uplink bus, and the other periods are high-resistance;
  • Step 204 The data forwarding unit forwards the received information to the time slot segment corresponding to each board on the downlink bus, and forwards the downlink data of all the boards to the downlink bus. Each board receives corresponding downlink data in a time slot corresponding to the downlink bus.
  • the real-time bus synchronizes and samples the data through the system clock, and each board uses the sampling clock to perform data transmission and reception sampling, and the time slot segments of different boards are positioned by the frame positioning clock.
  • the data forwarding unit is located on the public board, receives information sent by the board on the uplink bus, and summarizes the received information and forwards the information to the downlink bus.
  • the slot segment corresponding to the board.
  • the number of boards connected to each of the first buses is different, the rate of the first bus is 1/n sampling clock frequency, n is the total number of device boards / the connection on the first bus The number of boards; the rate of the second bus is equal to the sampling clock frequency.
  • each of the first buses determines a transmission rate and a time slot division according to the number of boards connected thereto, and transmits data of each board connected to the public board in a time division multiplexing manner;
  • the time slot of each of the second buses is divided according to the number of all boards.
  • the bus is applied to complex electronic devices, in particular large-capacity communication devices.
  • the information of all the boards can be interconnected.
  • the utility model has the advantages of simple structure, simple protocol, low cost, strong real-time performance, and a large number of connected boards, which greatly simplifies the number of lines interconnected by the back board and reduces the back. Board and connector costs increase equipment reliability.
  • FIG. 1 is a structural diagram of a real-time bus according to an embodiment of the present invention
  • FIG. 2 is a flowchart of a method for implementing a real-time bus according to an embodiment of the present invention.
  • the embodiment of the invention provides a real-time bus, as shown in FIG. 1 , including an uplink bus, a downlink bus, a system clock, and a data forwarding unit.
  • the uplink bus is composed of a plurality of first buses, each of which is connected to a plurality of boards, and each of the first buses determines a transmission rate and a time slot according to the number of boards connected thereto, and adopts Time-division multiplexing transfers data from each board connected to the public board.
  • the downlink bus is composed of a plurality of second buses having the same transmission rate and content, and the second bus is in one-to-one correspondence with the first bus, and is respectively connected to the boards on the first bus;
  • the time slots of the second bus are divided according to the number of all boards.
  • Each of the first buses is connected with an m-block, the rate of the first bus is 1/n sampling clock frequency, n is the total number of device boards/m; the rate of the second bus is equal to the sampling clock frequency. .
  • the number of the boards connected to the first bus is different, the rate of the first bus is 1/n sampling clock frequency, and n is the total number of device boards/the number of boards connected to the first bus;
  • the rate of the second bus is equal to the sampling clock frequency.
  • the system clock is used for synchronizing and data sampling of the bus, and is composed of a frame positioning clock and a sampling clock.
  • Each board uses a sampling clock for data transmission and reception sampling, and the time slot segments of different boards are positioned by a frame positioning clock.
  • the data forwarding unit is located on the public board, and receives the information sent by the board on the uplink bus, and the received information is summarized and forwarded to the corresponding time slot of each board on the downlink bus. on.
  • Each board outputs the information of the board in the corresponding time slot segment, and is transmitted to the data forwarding unit on the public board through the uplink bus, and the remaining time period is high resistance; the data forwarding unit will all the boards.
  • the downlink data is forwarded to the downlink bus, and each board receives corresponding downlink data in a time slot corresponding to the downlink bus.
  • the optical transmission device is generally composed of a control board, a cross-connect board, and a service processing board.
  • the control board is a mandatory board in the device and is responsible for the management and control of the entire device. Configuration. Assume that there are 40 services, cross-boards and two control boards in the device.
  • the real-time bus of this solution can be divided into four buses according to the single-board arrangement and the driving capability of the single-board bus interface, that is, four uplink buses and four.
  • the root downlink bus, at this time n 4, hangs 10 boards on each bus.
  • the bus structure is shown in Figure 1. If the sampling clock frequency of the device is 19.44MHz, the rate of each uplink bus is 1/4 sampling clock.
  • the frequency which is 4.86 Mb/s, is equal to the sampling clock frequency, which is 19.44 Mb/s.
  • Each uplink bus is connected to 10 boards, that is, divided into 10 time slot segments, and the total number of boards connected to the downlink bus is 40, that is, divided into 40 time slot segments (excluding 2 control boards), or 42 time slot segments. (including 2 control panels).
  • the optical transmission device generally has a system clock of 19.44 MHz and a frame positioning clock of 19.44 MHz, which can be used as a synchronous clock and a frame positioning clock of the real-time bus, and a frame positioning clock is used to locate a data slot.
  • the bus is applied to a complex electronic device, in particular, a large-capacity communication device, which can realize interworking of information between all boards, has a simple structure, simple implementation protocol, low cost, strong real-time performance, and connection.
  • the number of boards is large, which greatly simplifies the number of lines interconnected by the backplane, reduces the cost of the backplane and connectors, and improves the reliability of the equipment.
  • the embodiment of the invention further provides a real-time bus implementation method. As shown in FIG. 2, the implementation method includes the following steps:
  • Step 201 The uplink bus is composed of a plurality of first buses, and the first bus is separately connected. Connect a number of boards and connect them to the public board;
  • Step 202 The downlink bus is composed of a plurality of second buses having the same transmission rate and content, and the second bus is in one-to-one correspondence with the first bus, and the second bus is respectively connected to a plurality of boards and The public board is connected;
  • Step 203 The boards output the information of the board in the corresponding time slot segments, and transmit the information to the data forwarding unit on the public board through the uplink bus, and the other periods are high-resistance;
  • Step 204 The data forwarding unit forwards the received information to the time slot segment corresponding to each board on the downlink bus, and forwards the downlink data of all the boards to the downlink bus. Each board receives corresponding downlink data in a time slot corresponding to the downlink bus.

Abstract

Disclosed are a real-time bus and an implementation method therefor. The method comprises the following steps: an uplink bus is composed of a plurality of first buses, and the first buses are connected to a plurality of single boards and is connected to a common single board; a downlink bus is composed of a plurality of second buses having identical transmission rates and contents, the second buses one-to-one correspond to the first buses, and the second buses are connected to a plurality of single boards separately and are connected to the common single board; each single board outputs information within a corresponding timeslot and transmits the information to a data forwarding unit, via the uplink bus, for receiving, and other time periods are high in resistance; and the data forwarding unit collects the received information, forwards the information to a timeslot corresponding to each single board on the downlink bus, and forwards downlink data of all the single boards to the downlink bus, and each single board receives the downlink data within the corresponding timeslot. The present invention has the advantages of simple structure, low cost, strong real-time performance, large quantity of connected single boards and the like, decreases the quantity of interconnected wires of a backboard, reduces the costs of the backboard and a connector, and improves the reliability of a device. The inventor shall check it carefully.

Description

一种实时总线及其实现方法Real-time bus and implementation method thereof 技术领域Technical field
本发明涉及通信技术领域,具体涉及一种实时总线及其实现方法。The present invention relates to the field of communications technologies, and in particular, to a real-time bus and an implementation method thereof.
背景技术Background technique
通信领域的一些大型电子设备,通常由多块单板组成,这些单板插装在背板,单板之间通过背板连线进行信号互连,特别是在大容量光传输设备中,单板数量通常多达30块以上,采用一根总线实现所有单板之间的通信非常困难,尤其是对于一些信息量不大、实时性要求较高的信息。Some large-scale electronic devices in the communication field usually consist of multiple boards that are inserted into the backplane. The boards are interconnected through the backplane connection, especially in large-capacity optical transmission equipment. The number of boards is usually more than 30. It is very difficult to use one bus to communicate between all boards, especially for some information with low information and high real-time requirements.
现有的总线技术很多,如CAN(Controller Area Network,控制器局域网)总线和I2C总线等,这些技术在工业电子、通信设备等领域都已广泛应用,但是,存在实现协议复杂、实时性较低、背板和连接器的成本较高的缺点,对一些互连信息量不大、实时性要求高等的场合,不是很适合。通信设备中单板数量很多,要求各单板之间实时通告在位和告警等信息,通过单板之间点对点互连,连线数量太多,显然难以实现,采用CAN和I2C总线等技术互连,又存在协议复杂,实时性难以保证等问题,所以现有的总线技术不适合大数量单板之间的通信。There are many existing bus technologies, such as CAN (Controller Area Network) bus and I2C bus. These technologies have been widely used in industrial electronics, communication equipment, etc. However, there are complex implementation protocols and low real-time performance. The disadvantages of high cost of the backplane and the connector are not suitable for occasions where the amount of interconnection information is small and the real-time requirements are high. There are a large number of boards in a communication device. It is required to notify the in-position and alarm information in real time between boards. The point-to-point interconnection between boards is too much. It is obviously difficult to implement. It uses technologies such as CAN and I2C bus. Even the existing protocol is not suitable for communication between a large number of boards.
综上所述,现有的总线技术存在如下问题:In summary, the existing bus technology has the following problems:
(1)实现协议复杂;(1) The implementation of the protocol is complex;
(2)实时性较低;(2) low real-time performance;
(3)背板和连接器的成本较高。(3) The cost of the backboard and connectors is high.
发明内容Summary of the invention
本发明所要解决的技术问题是解决现有的总线技术实现协议复杂、实时 性较低、背板和连接器的成本较高的问题,以降低大型设备中大数量单板之间信号互连线的数量和成本,满足单板之间信号的实时性要求。The technical problem to be solved by the invention is to solve the complex and real-time implementation of the existing bus technology protocol. Low cost, high backplane and connector cost, to reduce the number and cost of signal interconnections between large numbers of boards in large devices, and to meet the real-time requirements of signals between boards.
为了解决上述技术问题,本发明所采用的技术方案是提供一种实时总线,包括上行总线、下行总线、系统时钟和数据转发单元,In order to solve the above technical problem, the technical solution adopted by the present invention is to provide a real-time bus, including an uplink bus, a downlink bus, a system clock, and a data forwarding unit.
所述上行总线由多根第一总线组成,每根所述第一总线分别连接若干块单板,每根所述第一总线根据与其连接的单板数量确定传输速率以及时隙划分,并采用时分复用的方式将与其连接的各单板的数据传输给公共单板;The uplink bus is composed of a plurality of first buses, each of which is connected to a plurality of boards, and each of the first buses determines a transmission rate and a time slot according to the number of boards connected thereto, and adopts Time-division multiplexing is used to transfer data of each board connected to the public board.
所述下行总线由传输速率和内容完全相同的多根第二总线组成,所述第二总线与所述第一总线一一对应,并分别与所述第一总线上的单板连接;每根所述第二总线的时隙根据所有单板的数量划分;The downlink bus is composed of a plurality of second buses having the same transmission rate and content, and the second bus is in one-to-one correspondence with the first bus, and is respectively connected to the boards on the first bus; The time slot of the second bus is divided according to the number of all the boards;
所述系统时钟用于对总线进行同步和数据采样,由帧定位时钟和采样时钟组成,各单板采用采样时钟进行数据发送和接收采样,不同单板的时隙段采用帧定位时钟定位;The system clock is used for synchronizing and sampling data of the bus, and is composed of a frame positioning clock and a sampling clock. Each board uses a sampling clock to transmit and receive data. The time slot segments of different boards are positioned by a frame positioning clock.
所述数据转发单元位于所述公共单板上,接收所述上行总线上的单板发送的信息,并将接收到的信息汇总在一起转发到所述下行总线上各单板对应的时隙段上。The data forwarding unit is located on the public board, and receives the information sent by the board on the uplink bus, and the received information is summarized and forwarded to the corresponding time slot of each board on the downlink bus. on.
在上述实时总线中,每根所述第一总线上连接有m块单板,所述第一总线的速率为1/n采样时钟频率,n为设备单板总数/m;所述第二总线的速率等于采样时钟频率。In the above-mentioned real-time bus, each of the first buses is connected with m-blocks, the rate of the first bus is 1/n sampling clock frequency, n is the total number of device boards/m; the second bus The rate is equal to the sampling clock frequency.
在上述实时总线中,每根所述第一总线上连接的单板数量不同,所述第一总线的速率为1/n采样时钟频率,n为设备单板总数/所述第一总线上连接的单板数量;所述第二总线的速率等于采样时钟频率。In the above real-time bus, the number of boards connected to each of the first buses is different, the rate of the first bus is 1/n sampling clock frequency, n is the total number of device boards / the connection on the first bus The number of boards; the rate of the second bus is equal to the sampling clock frequency.
在上述实时总线中,各单板在各自对应的时隙段输出本单板的信息,并经各上行总线传输给所述公共单板上的数据转发单元接收,其余时段高阻;所述数据转发单元将所有单板的下行数据一并转发到所述下行总线,各单板在下行总线对应的时隙段接收相应的下行数据。 In the real-time bus, each board outputs the information of the board in the corresponding time slot segment, and is transmitted to the data forwarding unit on the public board through each uplink bus, and the remaining period is high impedance; the data is The forwarding unit forwards the downlink data of all the boards to the downlink bus, and each board receives the corresponding downlink data in the time slot corresponding to the downlink bus.
本发明还提供了一种实时总线的实现方法,所述实现方法包括以下步骤:The invention also provides a real-time bus implementation method, the implementation method comprising the following steps:
步骤201、所述上行总线由多根第一总线组成,将所述第一总线分别连接若干单板并与公共单板进行连接;Step 201: The uplink bus is composed of a plurality of first buses, and the first bus is connected to a plurality of boards and connected to a common board;
步骤202、所述下行总线由传输速率和内容完全相同的多根第二总线组成,所述第二总线与所述第一总线一一对应,将所述第二总线分别连接若干单板并于公共单板进行连接;Step 202: The downlink bus is composed of a plurality of second buses having the same transmission rate and content, and the second bus is in one-to-one correspondence with the first bus, and the second bus is respectively connected to a plurality of boards and The public board is connected;
步骤203、各单板在各自对应的时隙段输出本单板的信息,并经各所述上行总线传输给所述公共单板上的数据转发单元接收,其余时段高阻;Step 203: The boards output the information of the board in the corresponding time slot segments, and transmit the information to the data forwarding unit on the public board through the uplink bus, and the other periods are high-resistance;
步骤204、所述数据转发单元将接收到的信息汇总在一起转发到所述下行总线上各单板对应的时隙段上,并将所有单板的下行数据一并转发到所述下行总线,各单板在下行总线对应的时隙段接收相应的下行数据。Step 204: The data forwarding unit forwards the received information to the time slot segment corresponding to each board on the downlink bus, and forwards the downlink data of all the boards to the downlink bus. Each board receives corresponding downlink data in a time slot corresponding to the downlink bus.
在上述实现方法中,所述实时总线通过系统时钟对总线进行同步和数据采样,各单板采用采样时钟进行数据发送和接收采样,不同单板的时隙段采用帧定位时钟定位。In the above implementation method, the real-time bus synchronizes and samples the data through the system clock, and each board uses the sampling clock to perform data transmission and reception sampling, and the time slot segments of different boards are positioned by the frame positioning clock.
在上述实现方法中,所述数据转发单元位于所述公共单板上,接收所述上行总线上的单板发送的信息,并将接收到的信息汇总在一起转发到所述下行总线上各单板对应的时隙段上。In the above implementation method, the data forwarding unit is located on the public board, receives information sent by the board on the uplink bus, and summarizes the received information and forwards the information to the downlink bus. The slot segment corresponding to the board.
在上述实现方法中,每根所述第一总线上连接的单板数量不同,所述第一总线的速率为1/n采样时钟频率,n为设备单板总数/所述第一总线上连接的单板数量;所述第二总线的速率等于采样时钟频率。In the above implementation method, the number of boards connected to each of the first buses is different, the rate of the first bus is 1/n sampling clock frequency, n is the total number of device boards / the connection on the first bus The number of boards; the rate of the second bus is equal to the sampling clock frequency.
在上述实现方法中,每根所述第一总线根据与其连接的单板数量确定传输速率以及时隙划分,并采用时分复用的方式将与其连接的各单板的数据传输给公共单板;每根所述第二总线的时隙根据所有单板的数量划分。In the above implementation method, each of the first buses determines a transmission rate and a time slot division according to the number of boards connected thereto, and transmits data of each board connected to the public board in a time division multiplexing manner; The time slot of each of the second buses is divided according to the number of all boards.
本发明,所述总线应用于复杂的电子设备上,特别是大容量的通信设备 上,可以实现所有单板之间信息的互通,具有结构简单、实现协议简单、成本低、实时性强、连接单板数量多等优点,大大简化了背板互连的线数量,降低了背板和连接器成本,提高了设备的可靠性。According to the invention, the bus is applied to complex electronic devices, in particular large-capacity communication devices. The information of all the boards can be interconnected. The utility model has the advantages of simple structure, simple protocol, low cost, strong real-time performance, and a large number of connected boards, which greatly simplifies the number of lines interconnected by the back board and reduces the back. Board and connector costs increase equipment reliability.
附图说明DRAWINGS
图1为本发明实施例提供的实时总线结构图;FIG. 1 is a structural diagram of a real-time bus according to an embodiment of the present invention;
图2为本发明实施例提供的一种实时总线的实现方法流程图。FIG. 2 is a flowchart of a method for implementing a real-time bus according to an embodiment of the present invention.
具体实施方式detailed description
下面结合说明书附图和具体实施方式对本发明做出详细的说明。The present invention will be described in detail below with reference to the drawings and specific embodiments.
本发明实施例提供了一种实时总线,如图1所示,包括上行总线、下行总线、系统时钟和数据转发单元,The embodiment of the invention provides a real-time bus, as shown in FIG. 1 , including an uplink bus, a downlink bus, a system clock, and a data forwarding unit.
所述上行总线由多根第一总线组成,每根所述第一总线分别连接若干块单板,每根所述第一总线根据与其连接的单板数量确定传输速率以及时隙划分,并采用时分复用的方式将与其连接的各单板的数据传输给公共单板。The uplink bus is composed of a plurality of first buses, each of which is connected to a plurality of boards, and each of the first buses determines a transmission rate and a time slot according to the number of boards connected thereto, and adopts Time-division multiplexing transfers data from each board connected to the public board.
所述下行总线由传输速率和内容完全相同的多根第二总线组成,所述第二总线与所述第一总线一一对应,并分别与所述第一总线上的单板连接;每根所述第二总线的时隙根据所有单板的数量划分。The downlink bus is composed of a plurality of second buses having the same transmission rate and content, and the second bus is in one-to-one correspondence with the first bus, and is respectively connected to the boards on the first bus; The time slots of the second bus are divided according to the number of all boards.
每根所述第一总线上连接有m块单板,所述第一总线的速率为1/n采样时钟频率,n为设备单板总数/m;所述第二总线的速率等于采样时钟频率。Each of the first buses is connected with an m-block, the rate of the first bus is 1/n sampling clock frequency, n is the total number of device boards/m; the rate of the second bus is equal to the sampling clock frequency. .
每根所述第一总线上连接的单板数量不同,所述第一总线的速率为1/n采样时钟频率,n为设备单板总数/所述第一总线上连接的单板数量;所述第二总线的速率等于采样时钟频率。The number of the boards connected to the first bus is different, the rate of the first bus is 1/n sampling clock frequency, and n is the total number of device boards/the number of boards connected to the first bus; The rate of the second bus is equal to the sampling clock frequency.
所述系统时钟用于对总线进行同步和数据采样,由帧定位时钟和采样时钟组成,各单板采用采样时钟进行数据发送和接收采样,不同单板的时隙段采用帧定位时钟定位。 The system clock is used for synchronizing and data sampling of the bus, and is composed of a frame positioning clock and a sampling clock. Each board uses a sampling clock for data transmission and reception sampling, and the time slot segments of different boards are positioned by a frame positioning clock.
所述数据转发单元位于所述公共单板上,接收所述上行总线上的单板发送的信息,并将接收到的信息汇总在一起转发到所述下行总线上各单板对应的时隙段上。The data forwarding unit is located on the public board, and receives the information sent by the board on the uplink bus, and the received information is summarized and forwarded to the corresponding time slot of each board on the downlink bus. on.
各单板在各自对应的时隙段输出本单板的信息,并经各上行总线传输给所述公共单板上的数据转发单元接收,其余时段高阻;所述数据转发单元将所有单板的下行数据一并转发到所述下行总线,各单板在下行总线对应的时隙段接收相应的下行数据。Each board outputs the information of the board in the corresponding time slot segment, and is transmitted to the data forwarding unit on the public board through the uplink bus, and the remaining time period is high resistance; the data forwarding unit will all the boards. The downlink data is forwarded to the downlink bus, and each board receives corresponding downlink data in a time slot corresponding to the downlink bus.
下面以光传输设备举例说明,光传输设备一般由控制板、交叉板和业务处理板组成,控制板是设备中的必配单板,负责整个设备的管理和控制,其余单板可根据业务需求配置。假设设备中有40块业务、交叉单板和2块控制板,采用本方案的实时总线,可以依据单板排列和单板总线接口的驱动能力,分4根总线,即4根上行总线和4根下行总线,此时n=4,在每根总线上挂10块单板,总线结构如图1所示,如设备采样时钟频率为19.44MHz,则每根上行总线速率为1/4采样时钟频率,即4.86Mb/s,下行总线速率等于采样时钟频率,即19.44Mb/s。每根上行总线连接10块单板,即分成10个时隙段,下行总线连接的单板总数为40,即分成40个时隙段(不包括2块控制板),或42个时隙段(包括2块控制板)。光传输设备一般有系统时钟19.44MHz和帧定位时钟19.44MHz,可作为本实时总线的同步时钟和帧定位时钟,帧定位时钟用于定位数据时隙段。The following is an example of an optical transmission device. The optical transmission device is generally composed of a control board, a cross-connect board, and a service processing board. The control board is a mandatory board in the device and is responsible for the management and control of the entire device. Configuration. Assume that there are 40 services, cross-boards and two control boards in the device. The real-time bus of this solution can be divided into four buses according to the single-board arrangement and the driving capability of the single-board bus interface, that is, four uplink buses and four. The root downlink bus, at this time n=4, hangs 10 boards on each bus. The bus structure is shown in Figure 1. If the sampling clock frequency of the device is 19.44MHz, the rate of each uplink bus is 1/4 sampling clock. The frequency, which is 4.86 Mb/s, is equal to the sampling clock frequency, which is 19.44 Mb/s. Each uplink bus is connected to 10 boards, that is, divided into 10 time slot segments, and the total number of boards connected to the downlink bus is 40, that is, divided into 40 time slot segments (excluding 2 control boards), or 42 time slot segments. (including 2 control panels). The optical transmission device generally has a system clock of 19.44 MHz and a frame positioning clock of 19.44 MHz, which can be used as a synchronous clock and a frame positioning clock of the real-time bus, and a frame positioning clock is used to locate a data slot.
本发明,所述总线应用于复杂的电子设备上,特别是大容量的通信设备上,可以实现所有单板之间信息的互通,具有结构简单、实现协议简单、成本低、实时性强、连接单板数量多等优点,大大简化了背板互连的线数量,降低了背板和连接器成本,提高了设备的可靠性。According to the present invention, the bus is applied to a complex electronic device, in particular, a large-capacity communication device, which can realize interworking of information between all boards, has a simple structure, simple implementation protocol, low cost, strong real-time performance, and connection. The number of boards is large, which greatly simplifies the number of lines interconnected by the backplane, reduces the cost of the backplane and connectors, and improves the reliability of the equipment.
本发明实施例还提供了一种实时总线的实现方法,如图2所示,所述实现方法包括以下步骤:The embodiment of the invention further provides a real-time bus implementation method. As shown in FIG. 2, the implementation method includes the following steps:
步骤201、所述上行总线由多根第一总线组成,将所述第一总线分别连 接若干单板并与公共单板进行连接;Step 201: The uplink bus is composed of a plurality of first buses, and the first bus is separately connected. Connect a number of boards and connect them to the public board;
步骤202、所述下行总线由传输速率和内容完全相同的多根第二总线组成,所述第二总线与所述第一总线一一对应,将所述第二总线分别连接若干单板并与公共单板进行连接;Step 202: The downlink bus is composed of a plurality of second buses having the same transmission rate and content, and the second bus is in one-to-one correspondence with the first bus, and the second bus is respectively connected to a plurality of boards and The public board is connected;
步骤203、各单板在各自对应的时隙段输出本单板的信息,并经各所述上行总线传输给所述公共单板上的数据转发单元接收,其余时段高阻;Step 203: The boards output the information of the board in the corresponding time slot segments, and transmit the information to the data forwarding unit on the public board through the uplink bus, and the other periods are high-resistance;
步骤204、所述数据转发单元将接收到的信息汇总在一起转发到所述下行总线上各单板对应的时隙段上,并将所有单板的下行数据一并转发到所述下行总线,各单板在下行总线对应的时隙段接收相应的下行数据。Step 204: The data forwarding unit forwards the received information to the time slot segment corresponding to each board on the downlink bus, and forwards the downlink data of all the boards to the downlink bus. Each board receives corresponding downlink data in a time slot corresponding to the downlink bus.
本发明不局限于上述最佳实施方式,任何人应该得知在本发明的启示下作出的结构变化,凡是与本发明具有相同或相近的技术方案,均落入本发明的保护范围之内。 The present invention is not limited to the above-described preferred embodiments, and any one skilled in the art should be aware of the structural changes made in the light of the present invention. Any technical solutions having the same or similar to the present invention fall within the protection scope of the present invention.

Claims (9)

  1. 一种实时总线,包括上行总线、下行总线、系统时钟和数据转发单元,其特征在于,A real-time bus includes an uplink bus, a downlink bus, a system clock, and a data forwarding unit, wherein
    所述上行总线由多根第一总线组成,每根所述第一总线分别连接若干块单板,每根所述第一总线根据与其连接的单板数量确定传输速率以及时隙划分,并采用时分复用的方式将与其连接的各单板的数据传输给公共单板;The uplink bus is composed of a plurality of first buses, each of which is connected to a plurality of boards, and each of the first buses determines a transmission rate and a time slot according to the number of boards connected thereto, and adopts Time-division multiplexing is used to transfer data of each board connected to the public board.
    所述下行总线由传输速率和内容完全相同的多根第二总线组成,所述第二总线与所述第一总线一一对应,并分别与所述第一总线上的单板连接;每根所述第二总线的时隙根据所有单板的数量划分;The downlink bus is composed of a plurality of second buses having the same transmission rate and content, and the second bus is in one-to-one correspondence with the first bus, and is respectively connected to the boards on the first bus; The time slot of the second bus is divided according to the number of all the boards;
    所述系统时钟用于对总线进行同步和数据采样,由帧定位时钟和采样时钟组成,各单板采用采样时钟进行数据发送和接收采样,不同单板的时隙段采用帧定位时钟定位;The system clock is used for synchronizing and sampling data of the bus, and is composed of a frame positioning clock and a sampling clock. Each board uses a sampling clock to transmit and receive data. The time slot segments of different boards are positioned by a frame positioning clock.
    所述数据转发单元位于所述公共单板上,接收所述上行总线上的单板发送的信息,并将接收到的信息汇总在一起转发到所述下行总线上各单板对应的时隙段上。The data forwarding unit is located on the public board, and receives the information sent by the board on the uplink bus, and the received information is summarized and forwarded to the corresponding time slot of each board on the downlink bus. on.
  2. 如权利要求1所述的实时总线,其特征在于,每根所述第一总线上连接有m块单板,所述第一总线的速率为1/n采样时钟频率,n为设备单板总数/m;所述第二总线的速率等于采样时钟频率。The real-time bus of claim 1, wherein each of the first buses is connected with an m-block, the rate of the first bus is 1/n sampling clock frequency, and n is the total number of device boards. /m; The rate of the second bus is equal to the sampling clock frequency.
  3. 如权利要求1所述的实时总线,其特征在于,每根所述第一总线上连接的单板数量不同,所述第一总线的速率为1/n采样时钟频率,n为设备单板总数/所述第一总线上连接的单板数量;所述第二总线的速率等于采样时钟频率。The real-time bus according to claim 1, wherein the number of boards connected to each of the first buses is different, the rate of the first bus is 1/n sampling clock frequency, and n is the total number of boards of the device. / number of boards connected to the first bus; the rate of the second bus is equal to the sampling clock frequency.
  4. 如权利要求1所述的实时总线,其特征在于,The real time bus of claim 1 wherein:
    各单板在各自对应的时隙段输出本单板的信息,并经各上行总线传输给所述公共单板上的数据转发单元接收,其余时段高阻;所述数据转发单元将所有单板的下行数据一并转发到所述下行总线,各单板在下行总线对应的时 隙段接收相应的下行数据。Each board outputs the information of the board in the corresponding time slot segment, and is transmitted to the data forwarding unit on the public board through the uplink bus, and the remaining time period is high resistance; the data forwarding unit will all the boards. The downlink data is forwarded to the downlink bus, and each board is corresponding to the downlink bus. The slot receives the corresponding downlink data.
  5. 一种实时总线的实现方法,其特征在于,所述实现方法包括以下步骤:A method for realizing a real-time bus, characterized in that the implementation method comprises the following steps:
    步骤201、所述上行总线由多根第一总线组成,将所述第一总线分别连接若干单板并与公共单板进行连接;Step 201: The uplink bus is composed of a plurality of first buses, and the first bus is connected to a plurality of boards and connected to a common board;
    步骤202、所述下行总线由传输速率和内容完全相同的多根第二总线组成,所述第二总线与所述第一总线一一对应,将所述第二总线分别连接若干单板并与公共单板进行连接;Step 202: The downlink bus is composed of a plurality of second buses having the same transmission rate and content, and the second bus is in one-to-one correspondence with the first bus, and the second bus is respectively connected to a plurality of boards and The public board is connected;
    步骤203、各单板在各自对应的时隙段输出本单板的信息,并经各所述上行总线传输给所述公共单板上的数据转发单元接收,其余时段高阻;Step 203: The boards output the information of the board in the corresponding time slot segments, and transmit the information to the data forwarding unit on the public board through the uplink bus, and the other periods are high-resistance;
    步骤204、所述数据转发单元将接收到的信息汇总在一起转发到所述下行总线上各单板对应的时隙段上,并将所有单板的下行数据一并转发到所述下行总线,各单板在下行总线对应的时隙段接收相应的下行数据。Step 204: The data forwarding unit forwards the received information to the time slot segment corresponding to each board on the downlink bus, and forwards the downlink data of all the boards to the downlink bus. Each board receives corresponding downlink data in a time slot corresponding to the downlink bus.
  6. 如权利要求5所述的实现方法,其特征在于,所述实时总线通过系统时钟对总线进行同步和数据采样,各单板采用采样时钟进行数据发送和接收采样,不同单板的时隙段采用帧定位时钟定位。The implementation method of claim 5, wherein the real-time bus synchronizes and samples the data through the system clock, and each board uses a sampling clock to perform data transmission and reception sampling, and the time slot segments of different boards are used. Frame positioning clock positioning.
  7. 如权利要求5所述的实现方法,其特征在于,所述数据转发单元位于所述公共单板上,接收所述上行总线上的单板发送的信息,并将接收到的信息汇总在一起转发到所述下行总线上各单板对应的时隙段上。The implementation method of claim 5, wherein the data forwarding unit is located on the public board, receives information sent by a board on the uplink bus, and forwards the received information together. Go to the slot segment corresponding to each board on the downlink bus.
  8. 如权利要求5所述的实现方法,其特征在于,每根所述第一总线上连接的单板数量不同,所述第一总线的速率为1/n采样时钟频率,n为设备单板总数/所述第一总线上连接的单板数量;所述第二总线的速率等于采样时钟频率。The implementation method of claim 5, wherein the number of boards connected to each of the first buses is different, the rate of the first bus is 1/n sampling clock frequency, and n is the total number of boards of the device. / number of boards connected to the first bus; the rate of the second bus is equal to the sampling clock frequency.
  9. 如权利要求5所述的实现方法,其特征在于,每根所述第一总线根据与其连接的单板数量确定传输速率以及时隙划分,并采用时分复用的方式将与其连接的各单板的数据传输给公共单板;每根所述第二总线的时隙根据 所有单板的数量划分。 The implementation method of claim 5, wherein each of the first buses determines a transmission rate and a time slot division according to the number of boards connected thereto, and uses the time division multiplexing manner to connect the boards connected thereto. The data is transmitted to the public board; the time slots of each of the second buses are based on The number of all boards is divided.
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