CN208386577U - Communication system based on M-LVDS how main high-speed bus in real time - Google Patents
Communication system based on M-LVDS how main high-speed bus in real time Download PDFInfo
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- CN208386577U CN208386577U CN201820225476.9U CN201820225476U CN208386577U CN 208386577 U CN208386577 U CN 208386577U CN 201820225476 U CN201820225476 U CN 201820225476U CN 208386577 U CN208386577 U CN 208386577U
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Abstract
The utility model relates to a kind of communication systems based on M-LVDS how main high-speed bus in real time, the communication system includes: system A, system B and M-LVDS bus, the system A and system B respectively includes several nodes, is interconnected between the node inside the system A or system B by backboard and PCB trace；Pass through M-LVDS bus interconnection between node between the system A and system B.The prior art is compared, and the utility model has many advantages, such as high speed, real-time, isolation, flexible networking.
Description
Technical field
The utility model relates to be based on M-LVDS how main high-speed bus in real time more particularly, to one kind in bus communication field
Communication system.
Background technique
In security system design, bus communication needs to meet several big basic demands: electrical isolation, difference between different nodes
Fault tolerance and Fault Isolation between real time communication, different nodes between high-speed communication between node, different nodes.
In the field of business there are a variety of bus mechanism, but cannot all fully meet these requirements, such as
1, the parallel bus of high speed can satisfy requirement of real-time, but the insulation request being unable to satisfy between different nodes；
2, network communication can satisfy insulation request, but not be able to satisfy requirement of real-time；
3, CAN bus meets isolation and the requirement of real-time, but cannot achieve high-speed communication again.
By retrieval, China Patent Publication No. is that disclose a kind of integrated CN based on SOC technology total by CN107317734A
Line node chip structure, the node chip are made of master controller, CAN bus protocol controller unit, transmission circuit unit,
Master controller is for realizing the register configuration to CAN bus protocol controller and completes the reading and write-in of data；CAN is total
Wire protocol controller unit is for realizing CAN bus data link layer content, including data framing, error detection and examination filter
Wave；CAN transmission circuit unit realizes CAN bus physical layer content, completes the conversion of physical bus level and logic level, the reality
With the design of node of novel simplified CAN bus communication system, design and the debugging for reducing CAN bus Communication System Design personnel are difficult
Degree, improves the Stability and dependability of system.But the utility model is directed to CAN bus communication, due to own limitations, nothing
Method realizes high-speed communication.
Utility model content
The purpose of this utility model is exactly to provide a kind of based on M- to overcome the problems of the above-mentioned prior art
The communication system of LVDS how main high-speed bus in real time.
The purpose of this utility model can be achieved through the following technical solutions:
A kind of communication system based on M-LVDS how main high-speed bus in real time, which is characterized in that the communication system includes: to be
Unite A, system B and M-LVDS bus, and the system A and system B respectively include several nodes, in the system A or be
It is interconnected between node inside system B by backboard and PCB trace；Pass through M- between node between the system A and system B
LVDS bus interconnection.
Preferably, the M-LVDS bus is twisted-pair cable.
Preferably, each node of the system A and system B includes an independent embedded board, described
It include processor, memory and M-LVDS bus control unit inside board.
Preferably, the M-LVDS bus control unit is FPGA.
Preferably, it is equipped with register, sending module, receiving module and link state in the FPGA and monitors module, institute
The register stated is connect with processor, sending module, receiving module respectively, the link state monitor module respectively with transmission
Module, receiving module connection, the M-LVDS bus are connect with sending module, receiving module respectively.
Preferably, data FIFO buffer area is equipped in the sending module.
Preferably, the clock for being sampled to the data in M-LVDS bus is equipped in the receiving module.
Preferably, the clock includes 4 clocks that phase successively differs 90 °.
Compared with prior art, the utility model has the advantage that
1, flexibility: M-LVDS bus haves no need to change the related hardware of any node, so that it may directly add in bus
Add new node, i.e. supporting node being dynamically added or exiting；
2, the transmission of bus frame is by the way of pair net, and the physics and function of double nets all keep independent, respectively using repeating transmission
Mechanism, to guarantee data validity.
Detailed description of the invention
Fig. 1 is the communication structure topological structure schematic diagram of the utility model；
Fig. 2 is the M-LVDS bus control unit structural schematic diagram of the utility model.
Specific embodiment
Below by the technical scheme in the utility model embodiment is clearly and completely described, it is clear that described
Embodiment is a part of the embodiment of the utility model, rather than whole embodiments.Based on the embodiments of the present invention, originally
Field those of ordinary skill every other embodiment obtained without making creative work all should belong to this
The range of utility model protection.
As shown in Figure 1, a kind of communication system based on M-LVDS how main high-speed bus in real time, which includes: to be
Unite A, system B and M-LVDS bus, and the M-LVDS bus is twisted-pair cable, and the system A and system B are respectively included
Several nodes are interconnected between the node inside the system A or system B by backboard and PCB trace；It is in described
It is interconnected between node between system A and system B by twisted-pair cable.
When the M-LVDS bus, which is taken in, to be had multiple nodes while having driving request, it is necessary to carry out bus arbitration:
When a new node is added in M-LVDS bus, which cannot drive M-LVDS bus, and it is total can only to receive M-LVDS
Signal on line；When M-LVDS bus is in idle condition, the node can just arbitrate the M-LVDS bus right to use；Institute
The node stated sends data after obtaining the M-LVDS bus arbitration right to use.
The rule of the M-LVDS bus arbitration is: the node sends data 0, but the data received are 1, are said
There are other nodes simultaneously in driving M-LVDS bus in bright M-LVDS bus, and priority is higher than oneself, which stops current
Transmission operation.
Each node of the system A and system B are an independent embedded boards, packet inside the board
Processor, memory and M-LVDS bus control unit are included, the M-LVDS bus control unit is FPGA.
As shown in Fig. 2, the FPGA includes: mlvds_regs register submodule, mlvds_tx_queue transmission team
Column submodule, mlvds_transmitter sending submodule, mlvds_sample receive sampling submodule, mlvds_rx_
Queue receiving queue submodule and mlvds_link_monitor link state monitoring submodule.
The mlvds_regs register submodule is equipped with the interface with processor, and the mlvds_regs is posted
Storage submodule is separately connected mlvds_tx_queue transmit queue submodule and mlvds_rx_queue receiving queue submodule,
Programmable register in the mlvds_regs register submodule maintenance M-LVDS bus control unit, comprising: control is posted
Storage, status register, interrupt register.
Data FIFO buffer area is equipped with inside the mlvds_tx_queue transmit queue submodule, it is described
Mlvds_tx_queue transmit queue submodule connects mlvds_transmitter sending submodule, when a whole frame is written
When to data FIFO, it will request to send data to mlvds_transmitter.
The mlvds_transmitter sending submodule is separately connected M-LVDS bus and mlvds_link_
Monitor link state monitoring submodule, the module be responsible for arbitrate M-LVDS bus the right to use, node send data it
Before, it is necessary to it first passes through bus arbitration and obtains the bus right to use.It, could be by the data frame of this node after only obtaining the bus right to use
It is sent in bus.
The mlvds_sample receives sampling submodule and is separately connected M-LVDS bus and mlvds_link_
Monitor link state monitoring submodule, it includes that phase successively differs 90 ° that the mlvds_sample, which receives sampling submodule,
4 clocks, 4 clocks simultaneously sample the data in M-LVDS bus, so that it is guaranteed that wherein at least there is 1
Clock sampling has arrived correct data frame.
The mlvds_rx_queue receiving queue submodule is separately connected mlvds_sample and receives sampling submodule
With mlvds_regs register submodule, the mlvds_rx_queue receiving queue submodule is received in MLVDS bus
Data frame, and inspection is filtered to the data frame received, judge whether the reception filtering rule for meeting local node, simultaneously
Wrong status information in receive process can be fed back to CPU.
The current state of the mlvds_link_monitor link state monitoring submodule monitoring link, including it is described
M-LVDS bus whether connected and M-LVDS bus whether be in idle condition.
The utility model is applied to the exploitation of safety computer platform CVC-200, according to the difference of application environment,
CVC-200 is divided to for two kinds of configurations, respectively CVC-200C and CVC-200T.CVC-200C is vehicle-mounted type, flat based on CVC-200C
Platform can form the vehicle-mounted product that iCC, CTCS-KA await a subway with state iron.CVC-200T is trackside type, flat based on CVC-200T
Platform can form the tracksides products such as interlocking, column control, ZC, LC, RBC, TSRS, CCS.
Above description is only a specific implementation of the present invention, but the protection scope of the utility model is not limited to
In this, anyone skilled in the art within the technical scope disclosed by the utility model, can be readily occurred in various
Equivalent modifications or substitutions, these modifications or substitutions should be covered within the scope of the utility model.Therefore, this is practical
Novel protection scope should be subject to the protection scope in claims.
Claims (8)
1. a kind of communication system based on M-LVDS how main high-speed bus in real time, which is characterized in that the communication system includes: system
A, system B and M-LVDS bus, the system A and system B respectively include several nodes, in the system A or system B
It is interconnected between internal node by backboard and PCB trace；Pass through M- between node between the system A and system B
LVDS bus interconnection.
2. a kind of communication system based on M-LVDS how main high-speed bus in real time according to claim 1, which is characterized in that
The M-LVDS bus is twisted-pair cable.
3. a kind of communication system based on M-LVDS how main high-speed bus in real time according to claim 1, which is characterized in that
Each node of the system A and system B include an independent embedded board, include processing inside the board
Device, memory and M-LVDS bus control unit.
4. a kind of communication system based on M-LVDS how main high-speed bus in real time according to claim 3, which is characterized in that
The M-LVDS bus control unit is FPGA.
5. a kind of communication system based on M-LVDS how main high-speed bus in real time according to claim 4, which is characterized in that
Register is equipped in the FPGA, sending module, receiving module and link state monitor module, the register respectively with
Processor, sending module, receiving module connection, the link state are monitored module and are connected respectively with sending module, receiving module
It connects, the M-LVDS bus is connect with sending module, receiving module respectively.
6. a kind of communication system based on M-LVDS how main high-speed bus in real time according to claim 5, which is characterized in that
Data FIFO buffer area is equipped in the sending module.
7. a kind of communication system based on M-LVDS how main high-speed bus in real time according to claim 5, which is characterized in that
The clock for being sampled to the data in M-LVDS bus is equipped in the receiving module.
8. a kind of communication system based on M-LVDS how main high-speed bus in real time according to claim 7, which is characterized in that
The clock includes 4 clocks that phase successively differs 90 °.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820225476.9U CN208386577U (en) | 2018-02-08 | 2018-02-08 | Communication system based on M-LVDS how main high-speed bus in real time |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201820225476.9U CN208386577U (en) | 2018-02-08 | 2018-02-08 | Communication system based on M-LVDS how main high-speed bus in real time |
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| CN208386577U true CN208386577U (en) | 2019-01-15 |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112100112A (en) * | 2020-09-18 | 2020-12-18 | 中车株洲电力机车研究所有限公司 | Full duplex bus and train |
| CN116094867A (en) * | 2023-04-10 | 2023-05-09 | 湖南鲸瓴智联信息技术有限公司 | Time-sensitive network control protocol design method based on MLVDS bus |
-
2018
- 2018-02-08 CN CN201820225476.9U patent/CN208386577U/en active Active
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112100112A (en) * | 2020-09-18 | 2020-12-18 | 中车株洲电力机车研究所有限公司 | Full duplex bus and train |
| CN116094867A (en) * | 2023-04-10 | 2023-05-09 | 湖南鲸瓴智联信息技术有限公司 | Time-sensitive network control protocol design method based on MLVDS bus |
| CN116094867B (en) * | 2023-04-10 | 2023-06-16 | 湖南鲸瓴智联信息技术有限公司 | Time-sensitive network control protocol design method based on MLVDS bus |
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