CN205004841U - Intelligence substation equipment and data transmission system thereof - Google Patents
Intelligence substation equipment and data transmission system thereof Download PDFInfo
- Publication number
- CN205004841U CN205004841U CN201520759243.3U CN201520759243U CN205004841U CN 205004841 U CN205004841 U CN 205004841U CN 201520759243 U CN201520759243 U CN 201520759243U CN 205004841 U CN205004841 U CN 205004841U
- Authority
- CN
- China
- Prior art keywords
- message
- transmission system
- data transmission
- equipment
- goose
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Abstract
The utility model discloses an intelligence substation equipment and data transmission system thereof, this intelligence substation equipment's data transmission system sets up on equipment, incorporation equipment and intelligent terminal are observed and controled in intelligent substation equipment's protection, protection observing and controlling equipment passes through data transmission system is used for receiving SV message and receiving and dispatching GOOSE message, incorporation equipment passes through data transmission system is used for sending the SV message, intelligent terminal passes through data transmission system is used for receiving and dispatching the GOOSE message, wherein, data transmission system includes FPGA data acquisition expansion board and CPU core package board, the FPGA data acquisition expansion board with CPU core package board is connected through PCI -E backplane bus for transmission DMA data, receiving and dispatching SV and GOOSE message and encoding and decoding. Consequently, through implementing the utility model discloses can high efficiency realize the transmission of SV and GOOSE message.
Description
Technical field
The utility model relates to intelligent converting equipment, particularly the intelligent converting equipment of one and data transmission system thereof.
Background technology
At present; intelligent substation is a kind of up-to-date transformer substation construction pattern; adopt smart machine that is advanced, reliable, integrated and environmental protection; be standardized as basic demand with information digitalization of entirely standing, communications platform networking, information sharing, automatically complete the basic functions such as information gathering, measurement, control, protection, metering and detection.Meanwhile, the transformer station supporting the Premium Features such as electrical network control automatically in real time, Intelligent adjustment, on-line analysis decision-making and collaborative interaction is possessed.
But, owing to being also several times change from pilot in 2007 to present implementation, and different producer's implementations is not quite similar, most producer adopts FPGA (Field-ProgrammableGateArray, i.e. field programmable gate array) realize SV (SampledValues, sampled value) and the transmitting-receiving process of GOOSE (GenericObjectOrientedsubstationevent, the transformer substation case towards general object) message.Wherein, the feature of SV message is that data format is fixed, and packet sending intervals is fixed, and message sends interval 250 microsecond, and it is 1 delicate to require interval error to be less than.The feature of GOOSE message is once the data item of message data collection changes, and just needs to send fast, and inverse time-lag interval sends afterwards, finally presses Fixed Time Interval (heartbeat) and sends.SV and GOOSE message need process in real time, and SV message time period is short and be likely that many group messages are received and dispatched, so claimed apparatus has processing speed quickly simultaneously.
But, the data-interface of existing FPGA and CPU adopts LOCAL (local) parallel bus or PCI (PeripheralComponentInterconnect mostly, external components interconnection interface) bus, although it is relatively low that Localbus and pci bus technology realize difficulty, these Bus Speeds are low.Such as, pci bus flank speed is only 66M, causes data transmission efficiency low because speed is low, cause CPU can the number for the treatment of S V and GOOSE message limited, the many devices of outlet are connected for bus differential protection etc. and are just difficult to realize.And bus number many (PCI adopts 32 addresses, 32 single data and some control signals) causes the poor reliability being subject to interfering data transmission, for the difficulty solving anti-interference problem PCB (PrintedCircuitBoard, printed circuit board) making sheet increases and causes cost very high.
Based on above investigation, present inventor finds: for meeting the real-time processing requirement of intelligent substation to SV and GOOSE message, needing badly and proposing a kind of message transmissions solution rapidly and efficiently.
Utility model content
In view of this, the object of the utility model embodiment is to propose a kind of intelligent converting equipment and data transmission system thereof, rapidly and efficiently can realize the transmission of SV and GOOSE message.
Further, the data transmission system of above-mentioned intelligent converting equipment is arranged on the protection measuring and controlling equipment of intelligent converting equipment, merging equipment and intelligent terminal, described protection measuring and controlling equipment is for receiving SV message and transmitting-receiving GOOSE message, described merging equipment is for sending SV message, and described intelligent terminal is for receiving and dispatching GOOSE message; Wherein, described data transmission system comprises FPGA data acquisition expansion board and core cpu card, described FPGA data acquisition expansion board is connected by PCI-E core bus with described core cpu card, for transmitting DMA data, transmitting-receiving SV and GOOSE message and encoding and decoding.
Alternatively, in above-mentioned data transmission system, described FPGA data acquisition expansion board comprises: network interface module, for receiving the data of Ethernet; SV processor, with described network interface model calling, for receiving and dispatching described SV message and to the encoding and decoding of described SV message; GOOSE processor, with described network interface model calling, for receiving GOOSE message; Dma controller, is connected with described SV processor and described GOOSE processor, for the valid data of described SV message and described GOOSE message are write PCI-E module by the mode of DMA; PCI-E module, is connected with described core cpu card by described PCI-E core bus, for receiving and dispatching PCI-E data and realizing PCI-E consultative management.
Alternatively, in above-mentioned data transmission system, described GOOSE processor also for send GOOSE message encode and for receive GOOSE message decode.
Alternatively, in above-mentioned data transmission system, described core cpu card also for send GOOSE message encode and for receive GOOSE message decode.
Alternatively, above-mentioned data transmission system also comprises: pair time and synchronizer, whether the running status for module each in monitoring system synchronous.
In addition, the utility model also proposes a kind of intelligent converting equipment, and this intelligent converting equipment is provided with aforementioned data transmission system described in any one; Described protection measuring and controlling equipment is positioned at the wall of described intelligent converting equipment; described merging equipment and intelligent terminal are positioned at the process layer of described intelligent converting equipment, and described data transmission system is arranged on described protection measuring and controlling equipment and described merging equipment and intelligent terminal.
Relative to prior art, each embodiment of the utility model has the following advantages:
After adopting the technical scheme of the utility model embodiment, FPGA data acquisition expansion board is an independently device plug-in unit, be connected with the PCI-E bus of core cpu card by backboard, PCI-E bus is adopted to compare fast and reliable more with the LocalBus usually adopted with pci bus, and have employed the transmitting-receiving process that FPGA goes to realize PCI-E bus and SV, GOOSE message, the demand completing SV and GOOSE message that product is better met is quick, stable.
More characteristics and advantages of the present utility model are explained in embodiment afterwards.
Accompanying drawing explanation
The accompanying drawing of a part for formation the utility model embodiment is used to provide the further understanding to the utility model embodiment, and schematic description and description of the present utility model, for explaining the utility model, is not formed improper restriction of the present utility model.In the accompanying drawings:
The three-decker schematic diagram of the intelligent converting equipment that Fig. 1 provides for the utility model embodiment;
The hardware that Fig. 2 provides for the utility model embodiment forms and bus connection layout schematic diagram;
The FPGA expansion board schematic diagram that Fig. 3 provides for the utility model embodiment.
Embodiment
Below in conjunction with the accompanying drawing in the utility model embodiment, be clearly and completely described the technical scheme in the utility model embodiment, obviously, described embodiment is only the utility model part embodiment, instead of whole embodiments.Based on the utility model embodiment, those of ordinary skill in the art are not making the every other embodiment obtained under creative work prerequisite, all belong to the scope of the utility model protection.
It should be noted that, when not conflicting, the feature in the utility model embodiment and embodiment can combine mutually.
Below in conjunction with accompanying drawing, each embodiment of the present utility model is described further:
With reference to Fig. 1, it is the typical three-decker schematic diagram of intelligent converting equipment.Intelligence converting equipment mainly comprises process layer, wall and station level.Wherein, the present embodiment proposes a kind of data transmission system of intelligent converting equipment; mainly can be applicable to the intelligent terminal of intelligent converting equipment; here, the intelligent terminal of intelligent converting equipment mainly refers to intelligent converting equipment protection measuring and controlling equipment, the merging of intelligent converting equipment equipment, intelligent converting equipment intelligent terminal.Intelligence converting equipment protection measuring and controlling equipment is bay device, and merging equipment and intelligent terminal belong to process layer devices.The protection measuring and controlling equipment primary recipient SV message of wall and transmitting-receiving GOOSE data, merging equipment mainly sends SV message, intelligent terminal transmitting-receiving GOOSE data.Usually, protect that measuring and controlling equipment needs to merge equipment with multiple stage, intelligent terminal is sampled, and fiber optic Ethernet is point-to-point or be connected by switch.
Data transmission system is arranged on the protection measuring and controlling equipment of intelligent converting equipment and the merging equipment of intelligent converting equipment and intelligent terminal; protection measuring and controlling equipment is for receiving SV message and transmitting-receiving GOOSE message; merging equipment is for sending SV message, and intelligent terminal is for receiving and dispatching GOOSE message.
In the present embodiment, data transmission system comprises FPGA data acquisition expansion board and core cpu card, FPGA data acquisition expansion board and core cpu card are by PCI-E (PCIExpress, Peripheral Component Interconnect expansion interface) core bus is connected, for transmitting DMA data, transmitting-receiving SV and GOOSE message and encoding and decoding.
In above-described embodiment, the feature due to SV message is that data format is fixed, and packet sending intervals is fixed, and message sends interval 250 microsecond, and it is 1 delicate to require interval error to be less than.The feature of GOOSE message is once the data item of message data collection changes, and just needs to send fast, and inverse time-lag interval sends afterwards, finally presses Fixed Time Interval (heartbeat) and sends.SV and GOOSE needs in real time process, and SV message time period is short and be likely that many group messages are received and dispatched simultaneously, so how quick, the stable transmitting-receiving completing SV and GOOSE message is the key technology of intelligent terminal.Therefore, above-described embodiment adopts PCI-E bus to compare fast and reliable more with the LocalBus usually adopted with pci bus, and have employed the transmitting-receiving process that FPGA goes to realize PCI-E bus and SV, GOOSE message, the demand completing SV and GOOSE message that product is better met is quick, stable.
In above-described embodiment, FPGA data acquisition expansion board is an independently device plug-in unit, is connected with the PCI-E bus of core cpu card by backboard.FPGA data acquisition expansion board is by the codec functions of the transmitting-receiving message of the programming realization PCI-E bus DMA data-transformation facility to FPGA, SV and GOOSE message.The transceiving data of SV and GOOSE realizes the data interaction with core cpu plate by the DMA data-transformation facility of PCI-E bus.
With reference to shown in Fig. 2-3, as the optional execution mode of one, above-mentioned FPGA data acquisition expansion board can comprise following composition structure:
1) network interface module, for receiving the data of Ethernet;
2) SV processor, with network interface model calling, for receiving and dispatching SV message and to the encoding and decoding of SV message;
3) GOOSE processor, with network interface model calling, for receiving GOOSE message.
4) dma controller, is connected with SV processor and GOOSE processor, for the valid data of SV message and GOOSE message are write PCI-E module by the mode of DMA;
5) PCI-E module, is connected with core cpu card by PCI-E core bus, for receiving and dispatching PCI-E data and realizing PCI-E consultative management.
Optionally, above-mentioned GOOSE processor also can be used for send GOOSE message encode and for receive GOOSE message decode.Take FPGA resource too many, make the scale of FPGA excessive, Costco Wholesale is too high, about realizing the expensive twice of the encoding and decoding of GOOSE message than CPU.It is not only resource that encoding and decoding take, also has the monitoring function of the GOOSE message such as GOOSE chain rupture also will to be realized by FPGA, and FPGA is bad to do this kind of work causes resource serious waste.
With FPGA data acquisition expansion board, the mode of encoding and decoding is carried out alternately to GOOSE message, core cpu card can be used for send GOOSE message encode and for receive GOOSE message decode.Here, although it is relatively slow that the GOOSE message of employing core cpu card to transmission carries out encoding and decoding speed, but the requirement of state's net relevant criterion can be met, the monitoring of encoding and decoding and GOOSE message correctness that CPU realizes GOOSE message is all realized by software, give full play to the advantage of CPU, make cost lower simultaneously.Although high to the requirement of CPU, much more cheap than FPGA of the cost of CPU.In this programme, CPU adopts the P1010 of Freescale company, and cost is $ 20 only, and speed is up to the load factor of 800M, Cpu about 30%, and this is also that we adopt the reason of A scheme.
As the optional execution mode of one, the data transmission system in above-described embodiment also can comprise: pair time and synchronizer, whether the running status for module each in monitoring system synchronous.
The scheme that the various embodiments described above utilize FPGA and PCI-E bus to realize SV and GOOSE message data DMA (DirectMemoryAccess, direct memory access) rapidly and efficiently to transmit,
It should be noted that, in the various embodiments described above, PCI-E, SV, GOOSE and pair time synchronization module be the module of core.And, add dma controller and other nucleus module running state monitoring, thus understand the running status of nucleus module, judge whether to occur to block, out-of-limit, the whether abnormality such as synchronous so that whether whether understanding program have BUG (defect, damage) or resource to distribute rationally so that optimize and improved design project.
Such as, following composition structure can be comprised in FPGA data acquisition expansion board:
Clk_0 is clock module, is the clock source of other module of system, produces unified reset signal simultaneously.
PCI-E_hard_ip_0 is that the stone of PCI-E realizes module, and it completes the transmitting-receiving of PCI-E data and PCI-E consultative management and realization.
Modular_sgdma_dispatcher_0, dma_read_master_0 and dma_write_master_0 tri-modules realize the management of DMA data read and write.
Onchip_memory2_0 module is used for storage configuration parameter.
The control and management of pio_led module LED light
Pio_pb module input and output control module
Ruiji_qsys_interface_0 module: the interface of SV and GOOSE data
PCI-E_core_clk module: export the clock that PCI-E core uses, so that peripheral components is synchronous with PCI-E core.
Other module of RuiJi_cpuIF_0 module: FPGA and CPU pass through the interface module of PCI-E interaction data.
SV module: realize SV packet sending and receiving and encoding and decoding;
GOOSE module: the reception and the encoding and decoding that realize GOOSE message;
A/D module: realize AD data acquisition and storage administration;
EtherNet module: the data transmit-receive management realizing Ethernet;
Pair time and synchronizer.
Based on foregoing embodiments, below the method for transfer of data and process is described further:
One, DRP data reception process comprises:
1, EtherNet module ethernet control module just receives network interface data, and sends message to SV module and GOOSEModule.
If 2, the data analysis that EtherNet module sent of SV module to carry out CRC check to critical field as consistent in the reception message of configuration, then decode to message, analyze valid data and give dma module and process.
If 3, GOOSE module data analysis that EtherNet module is sent to carry out the reception message of CRC check as configuration to critical field consistent, then message all received and give that dma module is transparent is sent to CPU side, carrying out decoding and extracting data in CPU side.
4, the valid data of SV and GOOSE message are write PCI-E module by the mode of DMA by dma module.
5, dma module is write the data come are sent to core cpu plate according to the message protocol of PCI-E specified memory region by PCI-E bus by PCI-E module.
6, core cpu plate processes SV and GOOSE data.
Two, GOOSE data transmission procedure comprises:
1, the transmission first of GOOSE message organized by core cpu plate, when certain data item of GOOSE message data centralization changes (such as switch input variable displacement), the application program of CPU is compiled to reorganize and is sent message, message is encoded, and message is sent FPGA data acquisition expansion card by PCI-E bus with dma mode.
2, message is delivered to EtherNet module after receiving the DMA data of PCI-E bus and is sent by it by GOOSE module at once.GOOSE module itself is also responsible for sending to heartbeat for 2,3,4,5 times of GOOSE message.
Three, the process of transmitting of SV message comprises:
The transmission core cpu plate of SV message data is not intervened in real time, only needs to send the configuration information such as message format and other transmission time interval when powering on by configuration.The transmission timed sending of SV message is completed according to configuration information oneself by SV module, and the message organized in transmission message, and is delivered to EtherNet module by the Data Update that AD sampling comes by its timing, and is sent by it.
Four, the receiving course of SV message comprises:
1, power-up initializing needs the data item of configuration:
The data item of the CRC check of SV message is formed and CRC check numerical value, and the checking data item of a general configuration comprises: the target MAC (Media Access Control) address (MacAddr) of message, SV controll block index character string (SvcbRefId), APPID.
2, after SV module receives message from network interface module, first the message that will receive is determined whether, decoding message takes out corresponding field (MacAddr, SvcbRefId, Appid) and does CRC check computing, if CRC result is worth identical with the CRC check of the reception message of configuration, then docking receiving literary composition is all resolved, and effective sample values is saved in corresponding data buffer zone, and start DMA transmission.
3, DMA sending module is according to the reception data initial address of the CPU side of configuration when powering on, and calculates offset address according to the sampling period of sampled value and be added with initial address, obtains the address of data at CPU.And by PCI-E interface, data are sent to the internal memory of CPU side.
4, the sample values buffering area of CPU side is a buffer circle, the data that FPGA sends side leave annular sample values block buffer in order in, buffer circle all clear 0 time initial, it is regular length and set form that FPGA sends sample values data block, initial two bytes are " SV " character marking, the period containing sampled value of data field simultaneously, and period is that (0 ~ 3999) increases progressively continuously.The application program of CPU side, by certain time interval, reads the sample values received within the time interval, is set to sky after reading.
It is more than the whole process that SV message receives.
Based on the above, the various embodiments described above compared with prior art, have the following advantages:
The intelligent terminal of intelligence converting equipment mainly refers to intelligent converting equipment protection measuring and controlling equipment, intelligent converting equipment merges equipment, intelligent converting equipment intelligent terminal.Intelligence converting equipment protection measuring and controlling equipment is bay device, and merging equipment and intelligent terminal belong to process layer devices.The protection measuring and controlling equipment primary recipient SV message of wall and transmitting-receiving GOOSE data, merging equipment mainly sends SV message, intelligent terminal transmitting-receiving GOOSE data.
Usual protection measuring and controlling equipment needs and multiple stage to merge equipment, intelligent terminal point-to-point or be connected by switch by fiber optic Ethernet of sampling.The feature of SV message is that data format is fixed, and packet sending intervals is fixed, and message sends interval 250 microsecond, and it is 1 delicate to require interval error to be less than.The feature of GOOSE message is once the data item of message data collection changes, and just needs to send fast, and inverse time-lag interval sends afterwards, finally presses Fixed Time Interval (heartbeat) and sends.SV and GOOSE needs in real time process, and SV message time period is short and be likely that many group messages are received and dispatched simultaneously, so how quick, the stable transmitting-receiving completing SV and GOOSE message is the key technology of intelligent terminal.
Above-described embodiment adopts PCI-E bus to compare fast and reliable more with the LocalBus usually adopted with pci bus, and have employed the transmitting-receiving process that FPGA goes to realize PCI-E bus and SV, GOOSE message, the demand completing SV and GOOSE message that product is better met is quick, stable.LocalBus and pci bus technology realize difficulty relative to lower PCI-E bus, immediately easily realize.These Bus Speeds low such as pci bus flank speed is 66M and the speed of PCI-E is up to 8G; cause data transmission efficiency low because speed is low; cause CPU can the number for the treatment of S V and GOOSE message limited, the many devices of outlet are connected for bus differential protection etc. and are just difficult to realize.Further, bus number many (PCI be 32 addresses, 32 single data ,+some control signals) causes the poor reliability being subject to interfering data transmission, for the difficulty solving anti-interference problem PCB making sheet increases and causes cost very high.
In addition, the utility model embodiment still provides a kind of intelligent converting equipment, this intelligent converting equipment is provided with any one data transmission system above-mentioned, because any one data transmission system above-mentioned has above-mentioned technique effect, therefore, the intelligent converting equipment being provided with this data transmission system also should possess corresponding technique effect, and its specific implementation process is similar to the above embodiments, does not hereby repeat.
The foregoing is only embodiment of the present utility model, not in order to limit the utility model, all within spirit of the present utility model and principle, any amendment done, equivalent replacement, improvement etc., all should be included within protection range of the present utility model.
Claims (6)
1. the data transmission system of an intelligent converting equipment, it is characterized in that, described data transmission system is arranged on the protection measuring and controlling equipment of intelligent converting equipment, merging equipment and intelligent terminal, described protection measuring and controlling equipment by described data transmission system for receive SV message and transmitting-receiving GOOSE message, described merging equipment by described data transmission system for sending SV message, described intelligent terminal by described data transmission system for receiving and dispatching GOOSE message; Wherein, described data transmission system comprises FPGA data acquisition expansion board and core cpu card, described FPGA data acquisition expansion board is connected by PCI-E core bus with described core cpu card, for transmitting DMA data, transmitting-receiving SV and GOOSE message and encoding and decoding.
2. data transmission system according to claim 1, is characterized in that, described FPGA data acquisition expansion board comprises:
Network interface module, for receiving the data of Ethernet;
SV processor, with described network interface model calling, for receiving and dispatching described SV message and to the encoding and decoding of described SV message;
GOOSE processor, with described network interface model calling, for receiving GOOSE message;
Dma controller, is connected with described SV processor and described GOOSE processor, for the valid data of described SV message and described GOOSE message are write PCI-E module by the mode of DMA;
PCI-E module, is connected with described core cpu card by described PCI-E core bus, for receiving and dispatching PCI-E data and realizing PCI-E consultative management.
3. data transmission system according to claim 2, is characterized in that, described GOOSE processor also for send GOOSE message encode and for receive GOOSE message decode.
4. data transmission system according to claim 2, is characterized in that, described core cpu card also for send GOOSE message encode and for receive GOOSE message decode.
5. the data transmission system according to any one of Claims 1-4, is characterized in that, also comprises:
Pair time and synchronizer, whether the running status for module each in monitoring system synchronous.
6. an intelligent converting equipment, is characterized in that, is provided with the data transmission system described in any one of claim 1 to 5; Described protection measuring and controlling equipment is positioned at the wall of described intelligent converting equipment; described merging equipment and intelligent terminal are positioned at the process layer of described intelligent converting equipment, and described data transmission system is arranged on described protection measuring and controlling equipment and described merging equipment and intelligent terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520759243.3U CN205004841U (en) | 2015-09-28 | 2015-09-28 | Intelligence substation equipment and data transmission system thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201520759243.3U CN205004841U (en) | 2015-09-28 | 2015-09-28 | Intelligence substation equipment and data transmission system thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN205004841U true CN205004841U (en) | 2016-01-27 |
Family
ID=55161712
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201520759243.3U Active CN205004841U (en) | 2015-09-28 | 2015-09-28 | Intelligence substation equipment and data transmission system thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN205004841U (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106209340A (en) * | 2016-03-25 | 2016-12-07 | 国网江苏省电力公司电力科学研究院 | Intelligent substation test equipment SV, GOOSE synchronism output control method |
| CN107241241A (en) * | 2017-07-17 | 2017-10-10 | 国网四川省电力公司电力科学研究院 | A kind of Network records analytical equipment performance test methods |
| CN113868165A (en) * | 2021-09-28 | 2021-12-31 | 许昌许继软件技术有限公司 | Communication device and method based on auxiliary equipment on-site module |
| CN114221439A (en) * | 2021-12-08 | 2022-03-22 | 南京丰道电力科技有限公司 | Real-time data exchange method and device for power control system |
-
2015
- 2015-09-28 CN CN201520759243.3U patent/CN205004841U/en active Active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106209340A (en) * | 2016-03-25 | 2016-12-07 | 国网江苏省电力公司电力科学研究院 | Intelligent substation test equipment SV, GOOSE synchronism output control method |
| CN106209340B (en) * | 2016-03-25 | 2019-02-19 | 国网江苏省电力公司电力科学研究院 | Intelligent substation test equipment SV, GOOSE synchronism output control method |
| CN107241241A (en) * | 2017-07-17 | 2017-10-10 | 国网四川省电力公司电力科学研究院 | A kind of Network records analytical equipment performance test methods |
| CN113868165A (en) * | 2021-09-28 | 2021-12-31 | 许昌许继软件技术有限公司 | Communication device and method based on auxiliary equipment on-site module |
| CN114221439A (en) * | 2021-12-08 | 2022-03-22 | 南京丰道电力科技有限公司 | Real-time data exchange method and device for power control system |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN205004841U (en) | Intelligence substation equipment and data transmission system thereof | |
| CN101312302B (en) | Parallel signal transmission method of uninterrupted power source | |
| CN102354175B (en) | Remote I/O (input/output) control system of Modbus fieldbus DI-16-route monitor | |
| CN104348673B (en) | A kind of method of commissioning, master control borad and business board | |
| CN105573239A (en) | High speed backboard bus communication control device and method | |
| CN206804747U (en) | A kind of DTU devices of synchronized sampling | |
| CN103676661B (en) | Multifunction emulation verifies system and its emulation verification method | |
| CN103019141A (en) | Control module, control method and electric power dynamic recording device and implementation method thereof | |
| CN103592549A (en) | Intelligent power system fault recorder | |
| CN204256732U (en) | The high-speed data transmission apparatus of Based PC I-Express interface | |
| CN203260219U (en) | Simulated merging unit simulation device | |
| CN204390023U (en) | A kind of industrial control system | |
| CN208386577U (en) | Communication system based on M-LVDS how main high-speed bus in real time | |
| CN102710025A (en) | Power system communication device and method | |
| CN202872835U (en) | Wireless sensor network and Ethernet protocol conversion device available for industrial control | |
| CN201601690U (en) | Input-output module based on EtherCAT technique | |
| CN204795120U (en) | Split type extensible network message storage device | |
| CN102880576B (en) | Method for simulating multiple groups of UART interfaces based on STM32F103VE chip | |
| CN203572895U (en) | Intelligent power system fault recorder | |
| CN201167335Y (en) | Profibus-DP bus serial port server | |
| CN103414620A (en) | Double-channel CAN simulation system based on CAN buses | |
| CN204089864U (en) | A kind of gateway for connecting MVB and CAN | |
| CN207706195U (en) | A kind of automatic off-line type half-duplex communication circuit | |
| CN207304023U (en) | A kind of photovoltaic DC-to-AC converter based on high speed Ethernet industrial bus | |
| CN201285527Y (en) | Network computer based on FPGA |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |