CN112100112A - Full duplex bus and train - Google Patents
Full duplex bus and train Download PDFInfo
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- CN112100112A CN112100112A CN202010987103.7A CN202010987103A CN112100112A CN 112100112 A CN112100112 A CN 112100112A CN 202010987103 A CN202010987103 A CN 202010987103A CN 112100112 A CN112100112 A CN 112100112A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
Abstract
The invention provides a full-duplex bus and a train, wherein a master node and a slave node of the full-duplex bus respectively comprise an M-LVDS driver and an M-LVDS receiver, data signal transmission is carried out between the M-LVDS driver of the master node and the M-LVDS receiver of the slave node through a first differential pair circuit, and data signal transmission is carried out between the M-LVDS driver of the slave node and the M-LVDS receiver of the master node through a second differential pair circuit, so that a set of full-duplex data bus system based on M-LVDS is formed. Compared with other types of buses, the main node and the slave node have fewer signals, IO consumption is reduced, and cost is further reduced. And the serial data valid signal and the serial data signal are matched for use, and the data receiving part determines whether the serial data signal is transmitted or not by using the serial data valid signal, so that the coding overhead defined by the data frame boundary is reduced, and the data recovery logic is simplified.
Description
Technical Field
The invention relates to the technical field of buses, in particular to a full-duplex bus and a train.
Background
The bus is a common communication trunk for transmitting information among various functional components of the computer, and is a transmission line bundle consisting of wires. In the current backplane bus, point-to-point high-speed serial signal forms, such as PECL, CML, LVDS, etc., are usually used for high-speed data transmission, but these point-to-point high-speed serial signal forms consume a large amount of IO, and are relatively costly.
Disclosure of Invention
In view of the above, the present invention provides a full duplex bus and a train, which aims to achieve the purpose of reducing the cost.
In order to achieve the above object, the following solutions are proposed:
in a first aspect, a full duplex bus is provided, comprising: the synchronous clock signal transmission device comprises a main node, a slave node, a first differential pair circuit, a second differential pair circuit and a third differential pair circuit, wherein the first differential pair circuit is a physical channel for transmitting a data signal from the main node to the slave node, the second differential pair circuit is a physical channel for transmitting a data signal from the slave node to the main node, and the third differential pair circuit is a physical channel for transmitting a synchronous clock signal from the main node to the slave node;
the master node comprises a first M-LVDS (multi-point low Voltage Differential Signaling) driver and a first M-LVDS receiver, wherein the first M-LVDS driver comprises a first transmitting end, a second transmitting end and a third transmitting end, the first transmitting end is used for transmitting a synchronous clock signal to the third Differential pair circuit, the second transmitting end is used for transmitting a serial data effective signal to the first Differential pair circuit, the third transmitting end is used for transmitting a serial data signal to the first Differential pair circuit, the serial data effective signal is effective when the serial data signal is transmitted, and the serial data effective signal is ineffective when the serial data signal is not transmitted;
the slave node comprises a second M-LVDS driver and a second M-LVDS receiver, the second M-LVDS receiver comprises a first receiving end, a second receiving end and a third receiving end, the first receiving end is used for receiving a synchronous clock signal sent by the master node from the third differential pair circuit, the second receiving end is used for receiving a serial data effective signal sent by the master node from the first differential pair circuit, and the third receiving end is used for receiving a serial data signal sent by the master node from the first differential pair circuit;
the second M-LVDS driver includes a fourth transmitting end and a fifth transmitting end, the fourth transmitting end is configured to transmit a serial data valid signal to the second differential pair circuit, and the fifth transmitting end is configured to transmit a serial data signal to the second differential pair circuit;
the first M-LVDS receiver includes a fourth receiving end for receiving the serial data valid signal transmitted from the slave node from the second differential pair circuit, and a fifth receiving end for receiving the serial data signal transmitted from the slave node from the second differential pair circuit.
Optionally, the second M-LVDS driver further includes: the sixth receiving end is configured to receive, from the second differential pair circuit, a serial data valid signal sent from the slave node to the master node, and the seventh receiving end is configured to receive, from the second differential pair circuit, a serial data signal sent from the slave node to the master node.
Optionally, the number of the slave nodes is: at least two;
after receiving the data request instruction sent by the master node, the slave node sends a serial data valid signal to the second differential pair circuit through the fourth sending terminal, and sends a serial data signal containing the data requested by the data request instruction to the second differential pair circuit through the fifth sending terminal.
Optionally, for the master node and the slave node that transmit the serial data signal, the transmitted serial data signal updates data output at each pulse falling edge position of the synchronous clock signal;
and judging whether the serial data valid signal is valid at each pulse rising edge position of the synchronous clock signal for the master node and the slave node which receive the serial data signal, and sampling the serial data signal if the serial data valid signal is valid.
Optionally, the first M-LVDS driver specifically is:
M-LVDS drives of model SN65MLVD206D or SN65MLVD 207.
Optionally, the second M-LVDS driver is specifically:
M-LVDS drives of model SN65MLVD206D or SN65MLVD 207.
In a second aspect, a train is provided comprising a full duplex bus;
the full-duplex bus comprises: the synchronous clock signal transmission device comprises a main node, a slave node, a first differential pair circuit, a second differential pair circuit and a third differential pair circuit, wherein the first differential pair circuit is a physical channel for transmitting a data signal from the main node to the slave node, the second differential pair circuit is a physical channel for transmitting a data signal from the slave node to the main node, and the third differential pair circuit is a physical channel for transmitting a synchronous clock signal from the main node to the slave node;
the master node comprises a first M-LVDS driver and a first M-LVDS receiver, the first M-LVDS driver comprises a first sending end, a second sending end and a third sending end, the first sending end is used for sending a synchronous clock signal to the third differential pair circuit, the second sending end is used for sending a serial data valid signal to the first differential pair circuit, the third sending end is used for sending a serial data signal to the first differential pair circuit, the serial data valid signal is valid when the serial data signal is sent, and the serial data valid signal is invalid when the serial data signal is not sent;
the slave node comprises a second M-LVDS driver and a second M-LVDS receiver, the second M-LVDS receiver comprises a first receiving end, a second receiving end and a third receiving end, the first receiving end is used for receiving a synchronous clock signal sent by the master node from the third differential pair circuit, the second receiving end is used for receiving a serial data effective signal sent by the master node from the first differential pair circuit, and the third receiving end is used for receiving a serial data signal sent by the master node from the first differential pair circuit;
the second M-LVDS driver includes a fourth transmitting end and a fifth transmitting end, the fourth transmitting end is configured to transmit a serial data valid signal to the second differential pair circuit, and the fifth transmitting end is configured to transmit a serial data signal to the second differential pair circuit;
the first M-LVDS receiver includes a fourth receiving end for receiving the serial data valid signal transmitted from the slave node from the second differential pair circuit, and a fifth receiving end for receiving the serial data signal transmitted from the slave node from the second differential pair circuit.
Optionally, the second M-LVDS driver further includes: the sixth receiving end is configured to receive, from the second differential pair circuit, a serial data valid signal sent from the slave node to the master node, and the seventh receiving end is configured to receive, from the second differential pair circuit, a serial data signal sent from the slave node to the master node.
Optionally, the number of the slave nodes is: at least two;
after receiving the data request instruction sent by the master node, the slave node sends a serial data valid signal to the second differential pair circuit through the fourth sending terminal, and sends a serial data signal containing the data requested by the data request instruction to the second differential pair circuit through the fifth sending terminal.
Optionally, for the master node and the slave node that transmit the serial data signal, the transmitted serial data signal updates data output at each pulse falling edge position of the synchronous clock signal;
and judging whether the serial data valid signal is valid at each pulse rising edge position of the synchronous clock signal for the master node and the slave node which receive the serial data signal, and sampling the serial data signal if the serial data valid signal is valid.
Optionally, the first M-LVDS driver specifically is:
M-LVDS drives of model SN65MLVD206D or SN65MLVD 207.
Optionally, the second M-LVDS driver is specifically:
M-LVDS drives of model SN65MLVD206D or SN65MLVD 207.
Compared with the prior art, the technical scheme of the invention has the following advantages:
according to the full-duplex bus and the train provided by the technical scheme, the master node and the slave node of the full-duplex bus respectively comprise the M-LVDS driver and the M-LVDS receiver, data signal transmission is carried out between the M-LVDS driver of the master node and the M-LVDS receiver of the slave node through the first differential pair circuit, data signal transmission is carried out between the M-LVDS driver of the slave node and the M-LVDS receiver of the master node through the second differential pair circuit, namely the physical channel from the master node to the slave node is realized, the physical channels from the slave node to the master node respectively adopt independent physical channels, and a set of full-duplex data bus system based on M-LVDS is formed. Compared with other types of buses, the main node and the slave node have fewer signals, IO consumption is reduced, and cost is further reduced. And the serial data valid signal and the serial data signal are matched for use, and the data receiving part determines whether the serial data signal is transmitted or not by using the serial data valid signal, so that the coding overhead defined by the data frame boundary is reduced, and the data recovery logic is simplified.
The slave node transmits a serial data signal to the master node and simultaneously listens the serial data signal transmitted by the slave node so as to judge whether information transmission failure is caused by network failure or error contact of other slave nodes. In the normal data transmission stage, the rest of the slave nodes which do not receive the data request instruction transmitted by the master node listen to the data in the second differential pair circuit, so that the data transmitted by the slave node which is transmitting the serial data signal can be acquired, and the data interaction capability between the slave nodes is provided.
And the master node and the slave node which send the serial data signals update data output at the falling edge position of the synchronous clock signal, the master node and the slave node which receive the serial data signals judge whether the serial data effective signal is effective at each pulse rising edge position of the synchronous clock signal, and sample the serial data signals when the serial data effective signal is effective, so that sufficient time margin is provided for the bus, and the requirements of reducing the wiring length of corresponding signals of the bus are facilitated.
Of course, it is not necessary for any product in which the invention is practiced to achieve all of the above-described advantages at the same time.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a schematic diagram of a full-duplex bus according to an embodiment of the present invention;
fig. 2 is a schematic diagram of a structure of a full-duplex bus transmitting a synchronous clock signal according to an embodiment of the present invention;
fig. 3 is a schematic diagram illustrating a structure of a master node transmitting a serial data valid signal to a slave node according to an embodiment of the present invention;
fig. 4 is a schematic diagram illustrating a structure of a master node transmitting a serial data signal to a slave node according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating an exemplary structure of a slave node transmitting a serial data valid signal to a master node according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a structure for transmitting a serial data signal from a slave node to a master node according to an embodiment of the present invention;
FIG. 7 is a diagram illustrating an alternative configuration for transmitting a serial data valid signal from a slave node to a master node according to an embodiment of the present invention;
fig. 8 is a schematic diagram of another structure for transmitting a serial data signal from a slave node to a master node according to an embodiment of the present invention;
fig. 9 is a schematic diagram of another structure for transmitting a serial data valid signal from a slave node to a master node according to an embodiment of the present invention;
fig. 10 is a schematic diagram of another structure for transmitting a serial data signal from a slave node to a master node according to an embodiment of the present invention;
fig. 11 is a schematic diagram illustrating a manner in which a master node transmits a serial data signal to a slave node according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
An embodiment of the present invention provides a full-duplex bus, see fig. 1, comprising a master node, a slave node, a first differential pair circuit L1, a second differential pair circuit L2, and a third differential pair circuit L3. The master node is one and the slave nodes may be one or more. The first differential pair circuit L1 is a physical channel for transmitting data signals from the master node to the slave node, the second differential pair circuit L2 is a physical channel for transmitting data signals from the slave node to the master node, and the third differential pair circuit L3 is a physical channel for transmitting synchronous clock signals from the master node to the slave node. And the master node and the slave nodes realize the sampling recovery and processing work of data based on synchronous clock signals.
The master node provides a data signal to the slave node based on the synchronous clock signal; and the slave node recovers the data sent by the master node based on the synchronous clock signal, accesses a second differential pair circuit according to the analyzed data feedback requirement, and sends a data signal based on the synchronous clock signal. Referring to fig. 2, a synchronous clock signal 21 provided by a synchronous clock source in the network is sent by a first sending end 22 of the first M-LVDS driver to a first receiving end 24 of a second M-LVDS receiver of the slave node through a third differential pair circuit 23, and a clock pulse 25 recovered by the second M-LVDS receiver is used as a reference clock signal for data transceiving between the slave node and the master node. In the present invention, the first M-LVDS driver refers to an M-LVDS driver of the master node, and the second M-LVDS receiver refers to an M-LVDS receiver of the slave node.
The master node transmits a serial data valid signal and a serial data signal to the slave node through the first differential pair circuit. The serial data valid signal is used in cooperation with the serial data signal, and the serial data valid signal is valid when the serial data signal is transmitted and invalid when the serial data signal is not transmitted. The serial data valid signal is high indicating valid, and the serial data valid signal is low indicating invalid. The serial data signal jumps as the bit value of the transmitted data changes.
Referring to fig. 3, the serial data valid signal 31 is sent to the first differential pair circuit 33 through the second sending end 32 of the first M-LVDS driver, and the second receiving end 34 of the second M-LVDS receiver obtains the serial data valid signal from the first differential pair circuit 33 and recovers a local serial data valid signal 35. Referring to fig. 4, a serial data signal 41 is transmitted to the first differential pair circuit 33 through the third transmitting end 42 of the first M-LVDS driver, and the third receiving end 44 of the second M-LVDS receiver of the node acquires the serial data signal from the first differential pair circuit 33 and recovers a local serial data signal 45.
The slave node transmits a serial data valid signal and a serial data signal to the master node through the first differential pair circuit. The serial data valid signal and the serial data signal transmitted from the slave node to the master node are also used in combination, and the serial data valid signal is valid when the serial data signal is transmitted and invalid when the serial data signal is not transmitted. The serial data valid signal is high indicating valid, and the serial data valid signal is low indicating invalid. The serial data signal jumps as the bit value of the transmitted data changes.
Referring to fig. 5, a serial data valid signal 51 is sent from a fourth transmitting end 52 of the second M-LVDS driver to the second differential pair circuit 53, and a fourth receiving end 54 of the first M-LVDS receiver acquires the serial data valid signal from the second differential pair circuit 53 and recovers a local serial data signal 55. Referring to fig. 6, a serial data signal 61 is sent from a fifth transmitting terminal 62 of the second M-LVDS driver to the second differential pair circuit 53, and a fifth receiving terminal 64 of the first M-LVDS receiver acquires the serial data valid signal from the second differential pair circuit 53 and recovers a local serial data signal 65. The first M-LVDS receiver refers to an M-LVDS receiver of the master node and the second M-LVDS driver is an M-LVDS driver of the slave node in the present invention.
According to the full-duplex bus provided by the invention, the master node and the slave node respectively comprise the M-LVDS driver and the M-LVDS receiver, data signal transmission is carried out between the M-LVDS driver of the master node and the M-LVDS receiver of the slave node through the first differential pair circuit, and data signal transmission is carried out between the M-LVDS driver of the slave node and the M-LVDS receiver of the master node through the second differential pair circuit, so that a physical channel from the master node to the slave node is realized, and the physical channels from the slave node to the master node respectively adopt independent physical channels, so that a set of full-duplex data bus system based on M-LVDS is formed. Compared with other types of buses, the main node and the slave node have fewer signals, IO consumption is reduced, and cost is further reduced. And the serial data valid signal and the serial data signal are matched for use, and the data receiving part determines whether the serial data signal is transmitted or not by using the serial data valid signal, so that the coding overhead defined by the data frame boundary is reduced, and the data recovery logic is simplified.
Referring to fig. 7 and 8, the second M-LVDS driver further includes a sixth receiving terminal 56 and a seventh receiving terminal 66, the sixth receiving terminal 56 is configured to receive the serial data valid signal 51 transmitted from the node to the master node from the second differential pair circuit 53, and the seventh receiving terminal 66 is configured to receive the serial data signal transmitted from the node to the master node from the second differential pair circuit 53. The slave node transmits a serial data signal to the master node and simultaneously listens the serial data signal transmitted by the slave node so as to judge whether information transmission failure is caused by network failure or error contact of other slave nodes.
When the number of the slave nodes is at least two, the slave nodes transmit the serial data valid signal 51 to the second differential pair circuit 53 through the fourth transmitting terminal 52 after receiving the data request command transmitted by the master node, and transmit the serial data signal 61 containing the data requested by the data request command to the second differential pair circuit 53 through the fifth transmitting terminal 62. Namely, in the normal data transmission phase, the remaining slave nodes which do not receive the data request command transmitted by the master node listen to the data in the second differential pair circuit 53, so that the data being transmitted by the slave node which is transmitting the serial data signal can be acquired, and the data interaction capability between the slave nodes is provided. Referring to fig. 9 and 10, a case where the number of slave nodes is plural is shown.
In one embodiment, for the master node and the slave node that transmit the serial data signal, the transmitted serial data signal updates the data output at the falling edge position of each pulse of the synchronizing clock signal, as shown in fig. 11; and for the master node and the slave node which receive the serial data signal, judging whether the serial data effective signal is effective at each pulse rising edge position of the synchronous clock signal, and sampling the serial data signal if the serial data effective signal is effective. And further, sufficient time margin is provided for the bus, and the requirement of the equal length of the wiring of corresponding signals of the bus is favorably reduced.
In an embodiment, the first M-LVDS driver is specifically:
M-LVDS drives of model SN65MLVD206D or SN65MLVD 207.
In an embodiment, the second M-LVDS driver is specifically:
M-LVDS drives of model SN65MLVD206D or SN65MLVD 207.
The embodiment also provides a train comprising the full-duplex bus. The full duplex bus in a train is as described above. Other parts of the train can adopt the contents disclosed in the prior art, and the invention is not described in detail.
In this document, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The embodiments in the present description are mainly described as different from other embodiments, the same and similar parts in the embodiments may be referred to each other, and the features described in the embodiments in the present description may be replaced with each other or combined with each other.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (12)
1. A full-duplex bus, comprising: the synchronous clock signal transmission device comprises a main node, a slave node, a first differential pair circuit, a second differential pair circuit and a third differential pair circuit, wherein the first differential pair circuit is a physical channel for transmitting a data signal from the main node to the slave node, the second differential pair circuit is a physical channel for transmitting a data signal from the slave node to the main node, and the third differential pair circuit is a physical channel for transmitting a synchronous clock signal from the main node to the slave node;
the master node comprises a first M-LVDS driver and a first M-LVDS receiver, the first M-LVDS driver comprises a first sending end, a second sending end and a third sending end, the first sending end is used for sending a synchronous clock signal to the third differential pair circuit, the second sending end is used for sending a serial data valid signal to the first differential pair circuit, the third sending end is used for sending a serial data signal to the first differential pair circuit, the serial data valid signal is valid when the serial data signal is sent, and the serial data valid signal is invalid when the serial data signal is not sent;
the slave node comprises a second M-LVDS driver and a second M-LVDS receiver, the second M-LVDS receiver comprises a first receiving end, a second receiving end and a third receiving end, the first receiving end is used for receiving a synchronous clock signal sent by the master node from the third differential pair circuit, the second receiving end is used for receiving a serial data effective signal sent by the master node from the first differential pair circuit, and the third receiving end is used for receiving a serial data signal sent by the master node from the first differential pair circuit;
the second M-LVDS driver includes a fourth transmitting end and a fifth transmitting end, the fourth transmitting end is configured to transmit a serial data valid signal to the second differential pair circuit, and the fifth transmitting end is configured to transmit a serial data signal to the second differential pair circuit;
the first M-LVDS receiver includes a fourth receiving end for receiving the serial data valid signal transmitted from the slave node from the second differential pair circuit, and a fifth receiving end for receiving the serial data signal transmitted from the slave node from the second differential pair circuit.
2. The full-duplex bus of claim 1, wherein the second M-LVDS driver further comprises: the sixth receiving end is configured to receive, from the second differential pair circuit, a serial data valid signal sent from the slave node to the master node, and the seventh receiving end is configured to receive, from the second differential pair circuit, a serial data signal sent from the slave node to the master node.
3. The full-duplex bus of claim 2, wherein the number of slave nodes is: at least two;
after receiving the data request instruction sent by the master node, the slave node sends a serial data valid signal to the second differential pair circuit through the fourth sending terminal, and sends a serial data signal containing the data requested by the data request instruction to the second differential pair circuit through the fifth sending terminal.
4. A full duplex bus according to any of claims 1 to 3, wherein for the master node and the slave node transmitting a serial data signal, the transmitted serial data signal updates the data output at each falling edge position of a pulse of the synchronous clock signal;
and judging whether the serial data valid signal is valid at each pulse rising edge position of the synchronous clock signal for the master node and the slave node which receive the serial data signal, and sampling the serial data signal if the serial data valid signal is valid.
5. The full-duplex bus according to claim 1, wherein the first M-LVDS driver is in particular:
M-LVDS drives of model SN65MLVD206D or SN65MLVD 207.
6. The full-duplex bus according to claim 1, wherein the second M-LVDS driver is in particular:
M-LVDS drives of model SN65MLVD206D or SN65MLVD 207.
7. A train, comprising a full duplex bus;
the full-duplex bus comprises: the synchronous clock signal transmission device comprises a main node, a slave node, a first differential pair circuit, a second differential pair circuit and a third differential pair circuit, wherein the first differential pair circuit is a physical channel for transmitting a data signal from the main node to the slave node, the second differential pair circuit is a physical channel for transmitting a data signal from the slave node to the main node, and the third differential pair circuit is a physical channel for transmitting a synchronous clock signal from the main node to the slave node;
the master node comprises a first M-LVDS driver and a first M-LVDS receiver, the first M-LVDS driver comprises a first sending end, a second sending end and a third sending end, the first sending end is used for sending a synchronous clock signal to the third differential pair circuit, the second sending end is used for sending a serial data valid signal to the first differential pair circuit, the third sending end is used for sending a serial data signal to the first differential pair circuit, the serial data valid signal is valid when the serial data signal is sent, and the serial data valid signal is invalid when the serial data signal is not sent;
the slave node comprises a second M-LVDS driver and a second M-LVDS receiver, the second M-LVDS receiver comprises a first receiving end, a second receiving end and a third receiving end, the first receiving end is used for receiving a synchronous clock signal sent by the master node from the third differential pair circuit, the second receiving end is used for receiving a serial data effective signal sent by the master node from the first differential pair circuit, and the third receiving end is used for receiving a serial data signal sent by the master node from the first differential pair circuit;
the second M-LVDS driver includes a fourth transmitting end and a fifth transmitting end, the fourth transmitting end is configured to transmit a serial data valid signal to the second differential pair circuit, and the fifth transmitting end is configured to transmit a serial data signal to the second differential pair circuit;
the first M-LVDS receiver includes a fourth receiving end for receiving the serial data valid signal transmitted from the slave node from the second differential pair circuit, and a fifth receiving end for receiving the serial data signal transmitted from the slave node from the second differential pair circuit.
8. The train of claim 7, wherein the second M-LVDS driver further comprises: the sixth receiving end is configured to receive, from the second differential pair circuit, a serial data valid signal sent from the slave node to the master node, and the seventh receiving end is configured to receive, from the second differential pair circuit, a serial data signal sent from the slave node to the master node.
9. The train of claim 8, wherein the number of slave nodes is: at least two;
after receiving the data request instruction sent by the master node, the slave node sends a serial data valid signal to the second differential pair circuit through the fourth sending terminal, and sends a serial data signal containing the data requested by the data request instruction to the second differential pair circuit through the fifth sending terminal.
10. The train according to any one of claims 7 to 9, wherein for the master node and the slave node that transmit a serial data signal, the transmitted serial data signal updates the data output at each pulse falling edge position of the synchronous clock signal;
and judging whether the serial data valid signal is valid at each pulse rising edge position of the synchronous clock signal for the master node and the slave node which receive the serial data signal, and sampling the serial data signal if the serial data valid signal is valid.
11. The train according to claim 7, wherein the first M-LVDS driver is specifically:
M-LVDS drives of model SN65MLVD206D or SN65MLVD 207.
12. The train according to claim 7, wherein the second M-LVDS driver is specifically:
M-LVDS drives of model SN65MLVD206D or SN65MLVD 207.
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