CN101459675A - Real-time multi-path multiplexing synchronous high-speed transmission serial bus protocol - Google Patents
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Abstract
The invention relates to a real time multiplexed synchronous high speed transmission serial bus protocol, wherein transmission signals of a series bus in the protocol comprise three groups of signals of control signals, clock signals and data signals, any node can be appointed in advance as an only main node on the bus, the control signals are sent by the main node to control each node to send data in turn, the sending order and the data length of each node are preset, all data on the bus can be received through the clock signals and the data signals, the control signals of the main node comprise three states: (a) idle states, a synchronous series bus under the states is controlled by the main node, (b) node switching states, the states represent that data transmission of a preceding node is finished, the transmission of a next node is about to start, the node which obtains the bus control right discards the bus control right under the states, a next bus owner obtains the bus control rights and starts outputting the bus signals, (c) data transmission states, the states represent that the node which obtains the bus control right is outputting signals to the bus.
Description
Technical field
The present invention relates between industrial control equipment and electric power system control protection device interior each node by the serial core bus carry out regularly, large-capacity data switching technology and use the equipment of this technology.
Background technology
In Industry Control and electric power system control protection field; along with controlled function becomes increasingly complex; not only need a plurality of CPU or DSP together co-ordination finish control corresponding protection task; the data volume that needs between CPU or the DSP to exchange also constantly increases; therefore; system is also increasing to the requirement of bus bandwidth, requires in the 100Mbps grade.How to solve between a plurality of CPU the problem of real time high-speed swap data in a control cycle, common way is by parallel data/address bus task as the bus of the many master controls of support such as PCI, VME is finished, but parallel bus also exists back plate design complexity, cost height, poor anti jamming capability, need CPU to intervene shortcomings such as more.
And the universal serial bus line is few, generally adopts differential signal transmission, has simplicity of design, antijamming capability is strong, error detection is convenient, CPU intervenes advantages such as few.There is multiple universal serial bus technology can be used for the application of core bus at present, such as:
1.CAN bus: (Controller Area Net control area net)
The CAN bus is a kind of asynchronous serial bus technology.The bus node signal has " dominance " and " recessiveness " two states, during two transmissions of node " dominance " another transmissions of state " recessiveness " state, the state of bus is " dominance " state, the node that at this time sends " recessiveness " state can find that the state of bus is inconsistent with the state that oneself sends, thereby initiatively stops to send.The CAN bus realizes the arbitration of transmission route between node in this way.The speed of CAN bus is the highest has only 1Mbps, and message data partly has only 8 bytes, can't realize the large-capacity data exchange.
2.ARCNET bus: (Attached Resource Computer Network attached resource computer network)
The ARCNET bus is a kind of asynchronous serial bus technology that adopts the logic token ring to realize the transmission route arbitration.Node on all buses is formed a logic box, current node with transmission token when this node is sent completely or do not have data to send, sends a token frame to next node, next node obtains transmission route, and the node on the logic box obtains transmission route in turn.A large amount of transmission times have been wasted in the transmission of ARCNET bus logic token ring and the affirmation of message etc., cause message transmission rate lower, the highlyest only can reach 10Mbps.
3.TDM bus: (Time Division Multiplex time division multiplexing)
The TDM bus is a kind of synchronous serial bus, can reach the requirement that the big capacity of two-forty transmits data, transmits but TDM can only realize point-to-point data, can't realize the exchanges data between the multinode.
4.FlexRay bus:
The FlexRay bus is a kind of high speed confirmability that is used for automobile, possesses the bus system of failure tolerant.FlexRay meets time-multiplexed principle, and each access component and information all have been assigned with the time slot of determining, in the meantime their access bus uniquely.Time slot repeated through the fixing cycle.The time of information on bus can come out in perfect forecast, thereby is deterministic to the visit of bus.
The difference of FlexRay bus and HTM bus is that the HTM bus adopts each node of hardware controls signal controlling right
The visit of bus, it is few to have frame structure simple redundancy information, the advantage that efficiency of transmission is high.
5. other high-speed serial bus
The high-speed serial bus technology of present main flow is as PCI Express, SATA etc.These buses all have very high speed, can transmit large-capacity data, these buses are also supported point-to-point connection as common of TDM bus, realize the communication of point-to-multipoint, must be by the expansion of HUB equipment, therefore the exchanges data between general application domain CPU of these two kinds of buses and peripheral hardware can't realize the real time communication of a plurality of CPU of this bus equity each other.
Rapid IO has the characteristics of high-speed high capacity universal serial bus, but adopt point-to-point mode to be connected between each communication node and the exchange chip, must could realize a plurality of CPU or a plurality of plug-in unit exchanges data each other by special Rapid IO exchange chip, so Rapid IO do not have bus-type signal connection characteristics.
To sum up, still lack at present a kind of suitable electric power system control protection application need, high-speed high capacity with support that equity is transmitted the backboard universal serial bus technology that data combine between a plurality of nodes.
Summary of the invention
The present invention seeks to: a kind of high-speed high capacity and the backboard universal serial bus technology of supporting that reciprocity transfer of data combines between a plurality of nodes are provided, it is real-time multichannel synchronous high-speed transmission serial bus protocol, also claim HTM (abbreviation of Highperformance Time determinate Multiplexed synchronous serial Bus) bus protocol, be a kind of serial core bus agreement that is applied to industrial control field, but the exchange of the real time data between a plurality of nodes in the implement device.Be used for data sync between a plurality of nodes of industrial automation control protection equipment.
A kind of real-time multi-path multiplexing synchronous high-speed transmission serial bus protocol, its transmission signals comprises control signal, clock signal and three groups of signals of data-signal, it is characterized in that: the transmission sequence that to allocate a node earlier in advance on the universal serial bus transmission path be host node and Control Node, send control signal by host node, allocate the length of each node data transmission in advance; Control each node and send data in turn, each node can be by all data on clock signal and the data-signal reception bus simultaneously; The control signal of host node comprises three kinds of states:
(a) idle condition, synchronous serial bus is controlled by host node under this state;
(b) node switching state, a node data end of transmission on this state representation, next node transmission are about to begin, and a node that obtains bus control right is abandoned bus control right under this state, next bus owner obtains bus control right, and beginning output bus signal;
(c) data transfer state, this state show that the node that obtains bus control right is to bus-out signal;
The node operating state is switched synchronously; Each node is intercepted unique host node control signal, switches this node operating state according to the variation of control signal; When host node is initiated the current data exchange cycle, each node enters the exchanges data cycle synchronously, when a certain node when sending data, other each nodes receive the data on the bus synchronously, all nodes send data and finish, and each node withdraws from the current data exchange cycle synchronously;
Host node is regularly initiated transfer of data, but the cycle dynamic-configuration of transfer of data; In the course of the work, because the operating state of other each nodes and the operating state of host node are switched synchronously, adjust the cycle of host node initiation transfer of data dynamically and can realize the synchronous cycle adjustment of all node datas in the whole device.The time interval of host node initiation transfer of data is dynamically configurable, and this change will realize in next transmission cycle.
After each node obtained bus control right, to bus clock signal and data-signal, wherein clock signal can be a signal or be embedded within the data-signal by coding independently.Any one node can have and only have a host node as host node work in the device.Each node obtains bus control right acquisition bus control right according to default rotation and sends data under the control of control signal.
Allocate the length of each node data transmission in advance; The exchanges data load of bus is constant, and its each node and total transmission required time are constant, and host node can carry out the control signal state efficiently according to default data length and the bus signals that receives and switch, and the time overhead that node switches is low.
Its data-signal is made up of one or more data wire, by increasing data signal line, can increase exponentially the transfer of data speed amount of bus.
Bus signals carries out the bus-type transfer of data by difference bussing techniques such as High-Speed RS-485, MLVDS, BLVDS.
Beneficial effect of the present invention: the multichannel synchronous high-speed transmission serial bus protocol is stipulated each node timesharing use high-speed synchronous universal serial bus in real time, sends Frame in turn.Adopt hardware to generate control signal, allocate the method for the length of node transmission order and each node data frame in advance, can be implemented between a plurality of nodes efficient, the target that large-capacity data is regularly synchronous.HTM bus protocol regulation is regularly initiated transfer of data by host node, and transmission intercal can dynamically be adjusted, and each node carries out transfer of data in turn according to the host node control signal, and the transmission sequence and the data length of each node preestablish, and it is few to need CPU to intervene; Total data on the equal shared bus of all nodes; The HTM bus protocol especially is fit to be applied to industrial control equipment and each the internodal real time high-speed large-capacity data exchange of electric power system control protection device interior.
Description of drawings
Fig. 1 is the data transmission procedure and the data frame format of an application example of the present invention;
Fig. 2 is the state transition graph of an application example of the present invention;
Fig. 3 is the pie graph of the system of an application example composition of the present invention.
(1) Fig. 3 is an example with the HTM bus configuration of 3 nodes, and the interstitial content of real system is configurable;
(2) blackfin 534 is a CPU element among Fig. 3, and EP1C5 is for realizing the FPGA hardware circuit of HTM bus functionality, connects by parallel bus between CPU and the FPGA;
(3) SN65MLVD200 is a differential driver among Fig. 3.
Embodiment
With a concrete case study on implementation the specific embodiment of the present invention is described: in this example, device is a system that comprises 3 HTM bus nodes, each node comprises the correlation function that a FPGA realizes HTM bus protocol regulation, connect by parallel bus between CPU and the FPGA, CPU can have access to all data on the HTM bus by FPGA.In this example, HTM bus protocol embodiment is as follows:
1, the HTM bus has following column signal: control signal, clock signal, the independently clock signal that adopts in the data-signal, this example;
(a) control signal: by host node control, in this example, host node is to be specified by upper layer software (applications), and arbitrary node can be as host node, but host node must be unique in the system;
(b) clock signal: in this example, adopt the 40MHz clock as clock signal;
(c) data-signal: in this example, adopt two single data holding wires, so the actual maximum data transfer bandwidth of bus is 80Mbps.
2, the HTM bus is provided with idle condition, data transmission state, three kinds of states of node switching state, as shown in Figure 1;
(f) idle condition: the definition control signal is that logic high surpasses 2us and represents idle condition, idle condition represents that last time, data sync was finished, next time, data sync did not also begin, and at this state, all nodes are not to clock signal and data-signal output signal;
(g) node switching state: the definition control signal is a logic high, but no more than 1us of retention time is the node switching state, this state representation is in data synchronization process, previous node data has transmitted, this node is no longer exported clock and data-signal, the node data transmission in back is about to begin, and prepares output clock and data-signal;
(h) data transmission state: the definition control signal is that logic low is a data transfer state, in this state, the node of obtaining bus control right begins to export clock and data-signal, and the length of Frame is preestablished by upper layer software (applications), and other nodes obtain data message from bus simultaneously.
3, the logic of HTM bus and state transition graph are as shown in Figure 2, bus is from idle condition, when the fixed time interval of transfer of data arrives, bus enters data transfer state, host node is according to the length information that comprises in data clock signal that receives and the data, whether judgment data transmission is normal, then stops the current data transmission state as Data Transfer Done or data transmission exception and enters the node switching state; Sending node switches and finishes, and enters the data transfer state of new node; The Frame of all nodes sends and finishes, and bus is got back to idle condition again.
4, the form of the Frame of each node transmission is divided into 5 parts as shown in Figure 1:
(a) node number, length are 5, and the sending order number of expression present node in this example, can be supported 32 HTM bus nodes at most, and the node number of each node must be continuous mutually different positive integer;
(b) length, length are 7, and the length of expression data field is unit with 32 dword, and the data field length maximum of individual node can be 127 dword;
(c) keep, length is 20, and this keeps the expansion that the territory can be used as node number or length field, to realize the application need of more nodes or bigger data length;
(d) data field, data content is a unit with 32 dword, the length of data content is specified by length field;
(e) check code, length are 16, adopt cyclic redundancy check, and multinomial is x
16+ x
12+ x
5+ 1, the scope that verification comprises is (a) and (b), (c), (d) part, and HTM bus data frame adopts 16 CRC check to guarantee its reliability, abandons the reception data when CRC check is made mistakes.
5, send the realization of control: each node, comprise host node itself, all receive the control signal that host node sends, control signal whenever enters a minor node switching state, the then current node ID of obtaining bus control right adds 1, when certain node finds that the current node number of obtaining bus control right is consistent with node number own, this node is the node of next transmission, when control signal enters data transmission state, this node is just to bus output clock and data-signal, and wherein the length of data-signal is by data length field decision in (4); Find that when certain node current node number and the node number own of obtaining bus control right is inconsistent, this node continues wait; When control signal enters idle condition, the process of transmitting of all nodes finishes, and each node begins to wait for the beginning of data transfer cycle next time.
6, receive the realization of control: each node, comprise host node itself, all receive the control signal that host node sends, control signal whenever enters a minor node switching state, the then current node ID of obtaining bus control right adds 1, find that when certain node current node number and the node number own of obtaining bus control right is inconsistent, in the then next data transmission state, this node receives the data message of other nodes transmissions from bus; Find that when certain node the current node number of obtaining bus control right is consistent with node number own, represent that then this section point will send data in the next data transmission state, so this node need not from bus reception data; When control signal enters idle condition, the receiving course of all nodes finishes, and each node begins to wait for the beginning of data transfer cycle next time.
7, node sends troubleshooting: it is undesired to cause certain (or several) node to send data for a certain reason; its fault can show as: the unusual or transmission data exception of tranmitting data register; in this example; host node is under data transmission state; with the clock information on the monitor bus,, then can confirm as current sending node and send fault if clock signal does not have the upset of occurrence logic level for a long time; host node stops the current data transmission state, and switching state gets the hang of.
8, node receives troubleshooting: each node utilizes 16 cyclic redundancy checks to come verification to receive the correctness of data when receiving data, and by the data of cyclic redundancy check (CRC), receiving terminal does not directly abandon; Adopt 16 cyclic redundancy checks, can detect wrong sum all error in data below 16 bits; In the practical application, the probability of occurrence that comprises above wrong of 16 bits and error situation that can be by cyclic redundancy check in the data can be ignored.
9, the time interval of transfer of data; In theory according to the difference of time of day and data bit width, host node is initiated data transmission period scope at interval should be from 0 to infinity, in this example, with 50ns is the timing interval, represent that with one 16 bit binary number host node initiates the time interval of transfer of data, therefore, the cycle configurable range of this instance data transmission is 0～3.2768 millisecond
10, the realization in the time interval of dynamic adjusting data transmission; Each node adopts one 32, and every 50ns adds 1 counter as the local zone time counter; The time point that host node is initiated transfer of data first is that software is specified when initialization, and host node is relatively initiated the transfer of data moment and local zone time, as identical, then initiates transfer of data; After transfer of data begins first, but the data transmission period of time that host node begins according to this data transfer and dynamic-configuration is at interval, calculate initiate next time transfer of data time point, by that analogy; Therefore, if dynamic-configuration data transmission period at interval, this change will come into force in next data transfer cycle.
11, bus is finished once the summation that the required time of complete data transmission procedure equals the time of required time of all node data transmission and node switching, because the data length and the transmission sequence of each node preestablish, so each node transmission data need occupy the time of bus control right and fix, and the shared time of node switching state determines that also the load of bus just is constant.
12, each node employing SN65MLVD200 is that differential driver drives bus signals.The differential driver direction of host node drive control signal is set to all the time to bus output, and the driver direction of other nodes is made as from bus to be imported; For data-signal and clock signal, under data transmission state, when this node obtained bus control right, the direction of differential driver was made as to the bus output state, and the differential driver direction of other nodes is made as from bus to be imported; Under free time and node switching state, the direction of differential driver is made as high-impedance state.
Claims (10)
1, real-time multi-path multiplexing synchronous high-speed transmission serial bus protocol, the transmission signals of universal serial bus comprises control signal, clock signal and three groups of signals of data-signal in the agreement, it is characterized in that: specifying any one node in advance is host node unique on the bus, sends control signal by host node and controls each node and send data in turn; The sending order and the data length of each node preestablish, by all data on clock signal and the data-signal reception bus; The control signal of host node comprises three kinds of states:
(d) idle condition, synchronous serial bus is controlled by host node under this state;
(e) node switching state, a node data end of transmission on this state representation, next node transmission are about to begin, and a node that obtains bus control right is abandoned bus control right under this state, next bus owner obtains bus control right, and beginning output bus signal;
(f) data transfer state, this state representation obtain the node of bus control right to bus-out signal.
2, real-time multi-path multiplexing synchronous high-speed transmission serial bus protocol according to claim 1 is characterized in that: bus is from idle condition, and when the fixed time interval of transfer of data arrived, bus entered data transfer state; Data Transfer Done enters the node switching state; Sending node switches and finishes, and enters the data transfer state of new node; The data of all nodes send and finish, and bus is got back to idle condition again.
3, real-time multi-path multiplexing synchronous high-speed transmission serial bus protocol according to claim 1, it is characterized in that: each node is according to the synchronous switch operating state of unique control signal, when host node is initiated the current data exchange cycle, each node enters the exchanges data cycle synchronously, when a certain node when sending data, other each nodes receive the data on the bus synchronously, and all nodes send data and finish, and each node withdraws from the current data exchange cycle synchronously.
4, real-time multi-path multiplexing synchronous high-speed transmission serial bus protocol according to claim 1 is characterized in that: the form of the Frame that each node sends is divided into 5 parts:
(a) node number, the sending order number of expression present node;
(b) length, the length of expression data field;
(c) keep the territory,, can be used as the expansion of node number and length field for concrete the application keeps;
(d) data field, data content is a unit with 32 dword, the length of data content is specified by length field;
(e) scope that check code, verification comprise is (a) and (b), (c), (d) part.
5, real-time multi-path multiplexing synchronous high-speed transmission serial bus protocol according to claim 1, it is characterized in that: after each node obtains bus control right, to bus clock signal and data-signal, wherein clock signal can be a signal or be embedded within the data-signal by coding independently.
6, real-time multi-path multiplexing synchronous high-speed transmission serial bus protocol according to claim 1, it is characterized in that: the length of allocating each node data transmission in advance, the exchanges data load of bus is constant, its each node and total transmission required time are constant, data length that the host node basis is default and the bus signals that receives can carry out the control signal state efficiently and switch, and the time overhead that node switches is low.
7, real-time multi-path multiplexing synchronous high-speed transmission serial bus protocol according to claim 1, it is characterized in that: host node is regularly initiated transfer of data, but the cycle dynamic-configuration of transfer of data; In the course of the work, because the operating state of other each nodes and the operating state of host node are switched synchronously, adjust the cycle of host node initiation transfer of data dynamically and can realize the synchronous cycle adjustment of all node datas in the whole device.
8, real-time multi-path multiplexing synchronous high-speed transmission serial bus protocol according to claim 1, it is characterized in that: but host node is initiated the time interval dynamic-configuration of transfer of data, as configuration change at this transmission cycle transmission intercal, change will realize in next transmission cycle.
9, real-time multi-path multiplexing synchronous high-speed transmission serial bus protocol according to claim 1, its data-signal is made up of one or more data wire, by increasing data signal line, improves the transfer of data speed amount of bus.
10, real-time multi-path multiplexing synchronous high-speed transmission serial bus protocol according to claim 1, it is characterized in that: bus signals carries out the bus-type transfer of data by High-Speed RS-485, MLVDS, BLVDS differential bus.
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