CN110309086A - A kind of multichannel low speed mouth and single channel high speed port data interactive method - Google Patents
A kind of multichannel low speed mouth and single channel high speed port data interactive method Download PDFInfo
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- CN110309086A CN110309086A CN201910416755.2A CN201910416755A CN110309086A CN 110309086 A CN110309086 A CN 110309086A CN 201910416755 A CN201910416755 A CN 201910416755A CN 110309086 A CN110309086 A CN 110309086A
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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Abstract
A kind of multichannel low speed mouth and single channel high speed port data interactive method, comprising: FPGA acquires the data of multi-channel interface, and the data of acquisition are sent to DSP by inner high speed serial ports；The DSP receives the data that the FPGA is sent and carries out analysis and operation to data, and the data after analysis and operation are back to the FPGA；The DSP data returned are sent to multi-channel interface by the FPGA.Technical solution provided by the invention can not only be communicated with the realization internal data of precise and high efficiency, also make system compatibility stronger, and FPGA is avoided to repeat to modify, and shorten exploitation debugging cycle.
Description
Technical field
The present invention relates to digital communication fields, and in particular to a kind of multichannel low speed mouth and the data interaction of single channel high speed port
Method.
Background technique
Electric control protection system is the key player in electric system, is related to the safety and monitoring of whole system,
Core technology is the acquisition and real-time information process analysis of data, with the fine control of Control protection system more sophisticated
Strategy, internal system communication data amount is more and more huger, and system real time needs are also being continuously improved, the control week of whole system
Phase is also constantly reducing, and new challenge is proposed to internal communication mechanism and scheme.
Electric system control at present is kept tie in platform, and data communication uses parallel address data bus interface between FPGA and DSP,
FPGA collects the data interaction for carrying out chip chamber after the data in multiple channels by parallel address data bus interface, and FPGA is needed
Parallel address data bus interface module is individually developed, the module logic is complicated, and transplantability is poor, and is limited to parallel number of addresses
It is lower according to bus interface clock frequency, it is difficult to meet higher and higher communication need.
Summary of the invention
It is not able to satisfy higher and higher communication need in order to solve the prior art, the present invention provides a kind of multichannel low speed mouth
With single channel high speed port data interactive method.
Present invention provide the technical scheme that
A kind of multichannel low speed mouth and single channel high speed port data interactive method, comprising:
FPGA acquires the data of multi-channel interface, and the data of acquisition are sent to DSP by inner high speed serial ports；
The DSP receives the data that the FPGA is sent and carries out analysis and operation to data, and will be after analysis and operation
Data be back to the FPGA；
The DSP data returned are sent to multi-channel interface by the FPGA.
Preferably, FPGA acquires the data of multi-channel interface, and the data of acquisition are sent to by inner high speed serial ports
DSP, comprising:
Data are acquired by the slow channels acquisition module of FPGA, and send the data of acquisition to by SRIO sending module
The DSP.
Preferably, the slow channels acquisition module by FPGA acquires data, later further include:
The data of acquisition are subjected to priority ranking by channel priorities decision-making module；
And the DSP is sent by SRIO sending module by the data after sequence.
Preferably, the data by acquisition carry out priority ranking by channel priorities decision-making module, comprising:
The parallel multi-channel data of acquisition are summarized by channel priorities decision-making module for single-channel data, progress multi-pass
Road priority judgement, and will judge information group packet SRIO frame head.
Preferably, the data of the acquisition are sent to the DSP by SRIO sending module, before further include:
By the data-pushing after sequence to SRIO transmitting terminal cache module, the SRIO sending module is actively described in reading
The data of SRIO transmitting terminal cache module.
For the data-pushing by after sequence to SRIO transmitting terminal cache module, the SRIO sending module actively reads institute
The data of SRIO transmitting terminal cache module are stated, later further include:
First judge whether SRIO receiving module read lock signal locks, then SRIO sending module will be write if it is unlocked state
Then locking signal locking sends data, data, which are sent completely SRIO sending module, will write locking signal unlock；
If it is determined that SRIO receiving module read lock signal is that lock state then waits until unlocked state.
Preferably, the data of the acquisition are sent to the DSP by SRIO sending module, comprising:
The SRIO sending module completes the frame head analysis judgment data length of SRIO data, will be acquired according to handshaking information
Data the DSP is sent to by SRIO sending module.
Preferably, the data by after analysis and operation are back to the FPGA, comprising:
Data after analysis and operation are sent to the SRIO receiving module of the FPGA, the SRIO receiving module will connect
The data of receipts send data to multichannel and send trade-off decision module after being verified.
Preferably, the SRIO receiving module sends data to multichannel and sends choosing after being verified received data
Decision-making module is selected, before further include:
The SRIO receiving module data received are verified after by data-pushing to the receiving end SRIO cache mould
In block；
The multichannel sends trade-off decision module by judging in the cache module of the receiving end SRIO buffer state to lead
The dynamic data for reading buffer area.
Preferably, by data-pushing to the receiving end SRIO after the SRIO receiving module is verified the data received
In cache module, comprising:
The SRIO receiving module completes the reception and frame head parsing of data, determines sendaisle and data type, and right
Received data are verified, while designing the receiving end SRIO cache module write-in logic, by the data-pushing after verification to institute
It states in the cache module of the receiving end SRIO.
Preferably, the multichannel sends trade-off decision module by judging buffer area shape in the cache module of the receiving end SRIO
State actively reads buffer area data, comprising:
The multichannel sends trade-off decision module and judges whether buffer state is in state to be sent；
The data in the cache module of the receiving end SRIO are then read if non-null states；
And data-pushing to corresponding each slow channels is sent mould by the channel obtained according to parsing frame head and corresponding agreement
In block.
Compared with prior art, the invention has the benefit that
A kind of multichannel low speed mouth and single channel high speed port data interactive method, comprising: FPGA acquires multi-channel interface
Data, and the data of acquisition are sent to DSP by inner high speed serial ports；The DSP receives the data of the FPGA transmission simultaneously
Analysis and operation are carried out to data, and the data after analysis and operation are back to the FPGA；The FPGA returns the DSP
The data returned are sent to multi-channel interface；The technical program sends SRIO by SRIO sending module for the data of acquisition and receives mould
Block, and the data received are subjected to checking treatment, the communication of the realization internal data of accurate high speed by SRIO receiving module.
It is simple that the present invention realizes communication modes logic, is easy to implement, avoids FPGA user oneself development logic timing
Control module.
It is stronger that the present invention realizes system compatibility, and FPGA is avoided to repeat to modify, and shortens exploitation debugging cycle.
The present invention realizes two-way handshake mechanism and guarantees that data communication is reliable.
Detailed description of the invention
Fig. 1 is multichannel low speed mouth and single channel high speed port data interactive method flow chart of the invention；
Fig. 2 is control protecting platform CPU board card block diagram of the invention；
Fig. 3 is each module frame chart inside FPGA of the invention；
Fig. 4 is that multichannel of the invention turns single-channel data flow chart；
Fig. 5 is that single channel of the invention turns multi-channel data flow chart.
Specific embodiment
For a better understanding of the present invention, the contents of the present invention are done further with example with reference to the accompanying drawings of the specification
Explanation.
The present invention provides a kind of multichannel low speed mouths and single channel high speed port data interactive method, wrap as shown in Figure 1:
It includes:
S1, FPGA acquire the data of multi-channel interface, and the data of acquisition are sent to DSP by inner high speed serial ports；
S2, the DSP receive the data that the FPGA is sent and carry out analysis and operation to data, and will analysis and operation
Data afterwards are back to the FPGA；
The DSP data returned are sent to multi-channel interface by S3, the FPGA.
The invention is interacted inside a kind of low-speed parallel multichannel based on hardware platform and high speed serialization single-channel data
Method realizes inner bottom communication frame module design based on FPGA, utilizes the driving of FPGA design total interface and internal number
According to processing transport frame, this method is a kind of general internal communication Frame Design, and interface driver type can be according to actual needs
Exploitation.HSSI High-Speed Serial Interface can take SRIO or PCIE etc. to realize that the single channel high-speed data between chip chamber or board is handed over
Mutually；Any low speed acquisition channel such as IIC interface or SPI interface or 485 serial ports can be used in multichannel；External high-speed expansion connects
Mouth uses QSFP module.
For Fig. 2, single channel serial line interface of the present invention uses SRIO, and parallel multi-channel interface uses 485 serial interfaces
Mouth and backboard I/O interface.FPGA direct-passing mode is taken in all data transmissions, and FPGA only does the verification forwarding of data, not logarithm
According to parsing and handle.FPGA calls SRIO IP kernel to realize High Speed Serial driving exploitation, and the caching of internal data uses first to enter
First dequeue (FIFO) buffer area, FPGA decide whether to send data by judging whether FIFO is sky.SRIO communication uses
NWRITE instruction and DOORBELL instruction, for NWRITE as data transmission frames, DOORBELL can be used as handshaking information or mark
The transmission of will position.
It mainly include 8 modules in FPGA design of the present invention, respectively slow channels acquisition module, channel priorities are determined
Plan module, SRIO transmitting terminal cache module, SRIO sending module, SRIO receiving module, the receiving end SRIO cache module, multichannel
Send trade-off decision module, slow channels sending module.
Fig. 3 gives each Module Links block diagram inside FPGA.Entire communication flow is sent and received all solely based on FPGA
Vertical operation, is not influenced by other chips, as long as after multichannel collecting end collects data and verification passes through, all channel datas
Priority judgement is carried out to data by channel priorities decision-making module, single channel SRIO transmitting terminal caching mould is pushed to after sequence
Block, SRIO transmitting terminal is by judging that higher level's buffer area actively reads buffer area data as long as having data to be sent and connects by SRIO
Mouth is sent to recipient.In single channel receiving end, as long as receiving SRIO data, verification is pushed to reception buffer area after passing through
In, multichannel sends trade-off decision module and receives buffer state by judgement actively to read buffer area data, parses frame head
It is pushed data into each channel sending module after judging sendaisle, sending module is according to sending protocol requirement format for data
It is sent by external interface.
The invention internal communication is based on FPGA design, communicates frame and each module interface is fixed, and internal logic and interface drive
Dynamic type is designed according to actual demand, and specific embodiment is now described for controlling protecting platform.Slow channels acquisition module:
Acquisition module need to realize data parsing verification and the level cache of acquisition according to user's actual items Demand Design, and design
Unified module interface, to be docked with channel priorities decision-making module.
Channel priorities decision-making module: it is single-channel data that the module, which is used to handle parallel multi-channel data summarization, is carried out
Multichannel priority judgement, and will judge information group packet SRIO frame head, by frame head and data push to SRIO transmitting terminal cache mould
Block.
SRIO transmitting terminal cache module: the module uses First Input First Output buffer area, receiving channel priority decisions mould
The multi-channel data that block is sent, the module only provide reading-writing port, do not do read-write logic, read and write all by higher level's module and junior's mould
Block control, port is fixed.
SRIO sending module: the module is SRIO transmitting terminal, completes SRIO transmitting terminal cache module and reads logic.It completes
The frame head analysis judgment data length of SRIO data is completed SRIO according to handshaking information and is sent, and wherein handshaking information can pass through
DOORBELL frame format carries out two-way handshake, and the handshaking information of chip chamber can also be realized by GPIO interface, and outside extension connects
Mouth handshaking information can also be realized by external fiber.
SRIO receiving module: the module completes the reception and frame head parsing of SRIO data, and the design receiving end SRIO caches mould
Logic is written in block.
The receiving end SRIO cache module: the module uses First Input First Output buffer area, receives the data in the channel SRIO, should
Module only provides reading-writing port, does not do read-write logic, and read-write is all controlled by higher level's module and Subordinate module, and port is fixed.
Multichannel sends trade-off decision module: the module determines the hair of data according to the result that SRIO receiving module parses
Channel is sent, the reading logic of the receiving end SRIO cache module is done.The data of buffer area are read according to parsing result and buffer area
State determines.
Slow channels sending module: the module does the transmission of data, receives higher level's multichannel and sends trade-off decision module
Data, which does the verification of data and group is wrapped and sent according to respective protocol.
Fig. 4 gives multichannel collecting and receives flow chart to single-channel data.
1) FPGA receives multi-channel data simultaneously by multiple low-speed interfaces, and data are entered priority decisions module, are sentenced
Open close track data priority.
2) each channel data is pushed to by SRIO transmitting terminal cache module according to priority.
3) judge that buffer state is in state to be sent, judgement and receiving end handshake.
4) handshake is in state to be sent, then FPGA will write locking handshake locking, by the to be sent of buffer area
Data are pushed to specified sending port by SRIO.
5) FPGA will write locking handshake unlock after the completion of pushing, and data receiver is completed.
Fig. 5 gives single-channel data reception and turns multi-channel data transmitting flow chart.
1) serial data that FPGA is sent by SRIO interface DSP or expansion interface is right after receiving data
Frame head, which parses, determines sendaisle and data type.
2) by received data-pushing to the receiving end SRIO buffer area.
3) it sends front end and judges buffer state, the channel that buffer area data are obtained according to parsing is then read if it is non-empty
It is sent with corresponding agreement starting.
This method using NWRITE and DOORBELL data packet in SRIO agreement, SRIO this be that a kind of high speed serial communication connects
Mouthful, NWRITE and DOORBELL data packet is the data-transmission mode of SRIO communication, and NWRITE is transmitted as data, DOORBELL
Interaction as handshaking information, interface modes have a 1x, 2x, 4x, communication speed can be set as 1.25Gbps, 2.5Gbps,
3.125Gbps, 5Gbps, setting interface modes and communication speed when calling the IP kernel of FPGA SRIO.
It should be understood by those skilled in the art that, embodiments herein can provide as method, system or computer program
Product.Therefore, complete hardware embodiment, complete software embodiment or reality combining software and hardware aspects can be used in the application
Apply the form of example.Moreover, it wherein includes the computer of computer usable program code that the application, which can be used in one or more,
The computer program implemented in usable storage medium (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.) produces
The form of product.
The application is referring to method, the process of equipment (system) and computer program product according to the embodiment of the present application
Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions
The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs
Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute for real
The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.
The above is only the embodiment of the present invention, are not intended to restrict the invention, all in the spirit and principles in the present invention
Within, any modification, equivalent substitution, improvement and etc. done, be all contained in apply pending scope of the presently claimed invention it
It is interior.
Claims (11)
1. a kind of multichannel low speed mouth and single channel high speed port data interactive method characterized by comprising
FPGA acquires the data of multi-channel interface, and the data of acquisition are sent to DSP by inner high speed serial ports；
The DSP receives the data that the FPGA is sent and carries out analysis and operation to data, and will analyze and the number after operation
According to being back to the FPGA；
The DSP data returned are sent to multi-channel interface by the FPGA.
2. the method as described in claim 1, which is characterized in that FPGA acquires the data of multi-channel interface, and by the number of acquisition
DSP is sent to according to by inner high speed serial ports, comprising:
Data are acquired by the slow channels acquisition module of FPGA, and are sent by SRIO sending module the data of acquisition to described
DSP。
3. method according to claim 2, which is characterized in that the slow channels acquisition module by FPGA acquires number
According to later further include:
The data of acquisition are subjected to priority ranking by channel priorities decision-making module；
And the DSP is sent by SRIO sending module by the data after sequence.
4. method as claimed in claim 3, which is characterized in that the data by acquisition pass through channel priorities decision-making module
Carry out priority ranking, comprising:
The parallel multi-channel data of acquisition are summarized by channel priorities decision-making module for single-channel data, it is excellent to carry out multichannel
The judgement of first grade, and will judge information group packet SRIO frame head.
5. method as claimed in claim 4, which is characterized in that the data of the acquisition are sent to described by SRIO sending module
DSP, before further include:
By the data-pushing after sequence to SRIO transmitting terminal cache module, the SRIO sending module actively reads the SRIO hair
The data of sending end cache module.
6. method as claimed in claim 5, which is characterized in that the data-pushing by after sequence to SRIO transmitting terminal caches
Module, the SRIO sending module actively read the data of the SRIO transmitting terminal cache module, later further include:
First judge whether SRIO receiving module read lock signal locks, then SRIO sending module will write locking if it is unlocked state
Then semaphore lock sends data, data, which are sent completely SRIO sending module, will write locking signal unlock；
If it is determined that SRIO receiving module read lock signal is that lock state then waits until unlocked state.
7. method as claimed in claim 6, which is characterized in that the data of the acquisition are sent to described by SRIO sending module
DSP, comprising:
The SRIO sending module completes the frame head analysis judgment data length of SRIO data, according to handshaking information by the number of acquisition
The DSP is sent to according to by SRIO sending module.
8. the method as described in claim 1, which is characterized in that the data by after analysis and operation are back to described
FPGA, comprising:
Data after analysis and operation are sent to the SRIO receiving module of the FPGA, the SRIO receiving module will be received
Data send data to multichannel and send trade-off decision module after being verified.
9. method according to claim 8, which is characterized in that after the SRIO receiving module is verified received data
It sends data to multichannel and sends trade-off decision module, before further include:
The SRIO receiving module data received are verified after by data-pushing into the receiving end SRIO cache module；
The multichannel sends trade-off decision module by judging in the cache module of the receiving end SRIO buffer state actively to read
Take the data of buffer area.
10. method as claimed in claim 9, which is characterized in that the data received are carried out school by the SRIO receiving module
After testing by data-pushing into the receiving end SRIO cache module, comprising:
The SRIO receiving module completes the reception and frame head parsing of data, determines sendaisle and data type, and to reception
Data verified, while the receiving end SRIO cache module write-in logic is designed, by the data-pushing after verification to described
In the cache module of the receiving end SRIO.
11. method as claimed in claim 10, which is characterized in that the multichannel sends trade-off decision module and passes through judgement
Buffer state actively reads buffer area data in the cache module of the receiving end SRIO, comprising:
The multichannel sends trade-off decision module and judges whether buffer state is in state to be sent；
If the data then read to non-null states in the cache module of the receiving end SRIO；
And according to the obtained channel of parsing frame head and corresponding agreement by data-pushing into corresponding each slow channels sending module.
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