CN109902053A - A kind of SPI communication method, terminal device and storage medium based on dual controller - Google Patents
A kind of SPI communication method, terminal device and storage medium based on dual controller Download PDFInfo
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Abstract
The present invention relates to a kind of SPI communication method, terminal device and storage medium based on dual controller, in the method, host mode is set by main equipment, slave mode will be set as from equipment, main equipment and it is connected from four line SPI signals are passed through between equipment, wherein CS signal, which is used to control main equipment, still receives data for sending data；And CS pin be low level when, a data frame is sent to from equipment by main equipment, after the data frame is sent completely stop send data；Start to receive data from from equipment, the level height of CS pin, when receiving data since equipment, sets low level for CS pin by being arranged from equipment, when from equipment the data received are handled and send main equipment complete when, set high level for CS pin.The present invention realizes the data communication between primary processor and encryption chip using the four-wire system and programed logic of spi bus itself in the case where additionally not increasing external signal line.
Description
Technical field
The present invention relates to industrial control field, in particular to a kind of SPI communication method based on dual controller, terminal device
And storage medium.
Background technique
In security information product, either data communication or authentication procedures require to use Encryption Algorithm, very
Crypto engine is not attached on the primary processor of multi-product, so an encryption chip, main process task must be increased outside primary processor
Device chip can carry out the functions such as data encrypting and deciphering by this encryption chip.Serial peripheral equipment interface SPI (Serial
Peripheral Interface) be a kind of common primary processor and encryption chip communication mode.
Spi bus system is a kind of synchronous serial peripheral interface bus.It is using principal and subordinate's working method, in this mould
Usually there is a main equipment (Master) under formula and one or more from equipment (Slave).Host controls data transmission, and slave is matched
It closes host and completes transformation task.On hardware resource, what it was generallyd use is that four-wire system carries out two-way communication, and three-wire system is realized unidirectional
Transmission, in communication process, host passes through chip selection signal line CS (Chip select) first and chooses slave, and then host will
The data in 8 bit shift registers are fitted under the driving of 8 clock signal SCLK (Serial Clock), pass through spi bus
Host output/slave input signal cable MOSI (Master Output Slave Input, serial data output) pin be sent to from
In the shift register of machine, simultaneously, data are also by spi bus host input/slave output signal line MISO in slave
(Master Input, Slave Output) pin is transplanted in host.Signal wire can only be set by master in entire communication process
Standby control, slave do not have control action to communication process.
It for encryption chip, needs to control the transmission process of data, i.e., encryption chip sends out primary processor
The data brought are being sent to primary processor after carrying out encryption and decryption processing, so needing a control signal to primary processor
When carry out data receiver to be controlled, developer's current technology scheme of this engineering field is substantially external using increasing
Signal wire is to synchronize the data communication between slave, for example " one kind is based on SPI application No. is 201110387599.5 invention
The double processor communication method of bus " it is exactly one control signal wire of increase on the basis of SPI four-wire system, form five-wire system
Spi bus carries out the synchronization mechanism of two-way communication.Based on inertial thinking, industry application developer would generally be outer to increase
The mode of portion's communication line controls the synchronization mechanism of SPI.
Summary of the invention
To solve the above-mentioned problems, the present invention is intended to provide a kind of SPI communication method based on dual controller, terminal device
And storage medium is patrolled in the case where additionally not increasing external signal line using the four-wire system and process control of spi bus itself
It collects to realize the data communication between primary processor and encryption chip.
Concrete scheme is as follows:
A kind of SPI communication method based on dual controller, comprising the following steps:
S10: setting host mode for main equipment, will be set as slave mode from equipment, main equipment and between equipment
It is connected by MISO, MOSI, SCLK with tetra- line SPI signal of CS, wherein the setting of MISO, MOSI and SCLK signal and general SPI
Signal setting is identical, and CS signal is used to control main equipment and still receives data for sending data；
S20: when main equipment, which receives, to be sent data to from the task of equipment, after data composition data frame to be sent
The data being stored in main equipment send chained list；
S30: the data in real-time judge main equipment send in chained list whether have data, if so, and CS pin is low electricity
Usually, from chained list one data frame of acquisition is sent, which is sent to from equipment, is stopped after the data frame is sent completely
Send data；
S40: it is received in buffer area from the data deposit that equipment sends over main equipment；
S50: receiving buffer area from equipment timing scan, forms a complete data frame when receiving the data in buffer area
When, to handling in the data frame, generate one group of new data after processing, it will treated after data reformulate data frame
Then write-in sets high level for CS pin from the transmission buffer area of equipment, main equipment is waited to read the data from from equipment；
S60: main equipment receives CS pin when being high signal, reads data from from equipment, every to read the inspection of byte
The level height situation of a CS pin is surveyed, if CS pin is high level, continues to read data, if CS pin is low electricity
It is flat, stop reading data, starts the preparation for carrying out the transmission of next data frame；
S70: when having read a byte by main equipment every time from equipment, turn the data in buffer area are sent from equipment
The reading next time that main equipment is waited from the shift register of equipment is moved on to, if do not counted out of equipment transmission buffer area
According to when, be set as low level from equipment by CS pin.
Further, the data frame includes ID number, check code, data length, data field and the request class of data task
Type.
Further, the processing in step S50 includes verification data frame, parsing data frame and processing data.
Further, the processing data include one such or a variety of: encryption data, ciphertext data, generate abstract,
Generate random number.
A kind of SPI communication terminal device based on dual controller, including memory, equipment and it is stored in the memory
In and the computer program that can run on said device, the equipment realized when executing the computer program the present invention is based on
The step of SPI communication method of dual controller.
A kind of computer readable storage medium, the computer-readable recording medium storage have computer program, the meter
The step of realizing that the present invention is based on the SPI communication methods of dual controller when calculation machine program is executed by processor.
The present invention uses technical solution as above, provides a kind of SPI communication method based on dual controller, is not increasing additionally
In the case where adding outside lead, the data communication of primary processor and encryption chip is carried out using the four-wire system of spi bus itself,
By CS pin being arranged to common input and output pin, and by procedure logical control system, the function of flexible Application CS can be with
It is effective to coordinate main equipment and the communication issue from equipment, save the external pin resource of processor.
Detailed description of the invention
Fig. 1 show the step schematic diagram of the embodiment of the present invention one.
Specific embodiment
To further illustrate that each embodiment, the present invention are provided with attached drawing.These attached drawings are that the invention discloses one of content
Point, mainly to illustrate embodiment, and the associated description of specification can be cooperated to explain the operation principles of embodiment.Cooperation ginseng
These contents are examined, those of ordinary skill in the art will be understood that other possible embodiments and advantages of the present invention.In figure
Component be not necessarily to scale, and similar component symbol is conventionally used to indicate similar component.
Now in conjunction with the drawings and specific embodiments, the present invention is further described.
Embodiment one:
The embodiment of the present invention one provides a kind of SPI communication method based on dual controller, as shown in Figure 1, it is this hair
The flow diagram of SPI communication method described in bright embodiment one based on dual controller, the method can comprise the following steps that
S10: setting host mode for main equipment, will be set as slave mode from equipment, main equipment and between equipment
It is connected by four line SPI signals.
The four lines SPI signal is respectively as follows: MISO, MOSI, SCLK and CS, and wherein MISO, MOSI and SCLK signal are set
Set identical as general SPI signal setting, the setting of CS signal selects setting different with general piece.
MISO is the input of main device data, is exported from device data；
MOSI is the output of main device data, is inputted from device data；
SCLK is clock signal, is controlled and is exported by main equipment；
CS is that direction selection controls signal, and it is output from equipment that main equipment, which is input, this signal is used to control main equipment use
Still receive data in sending data.
In the embodiment, the main equipment is host processor chip, the model grace intelligence Pu processor MC9S12 of use, institute
Stating from equipment is encryption chip, the encryption chip IS8U256 of model its people's technology.Encryption chip sends host processor chip
By treated, data are sent to host processor chip again after the data to come over are handled, and host processor chip receives first
Second group of data is retransmitted again after group treated data to be handled to encryption chip.Due to the hair of the host processor chip
The requirement for having timing with receive process is sent, so different realized by general SPI function, passing through in the embodiment will be general
CS signal in SPI signal is set as transmitting and receiving selection signal, for controlling the transmitting and receiving timing of host processor chip, with
Reach the set goal.
S20: when main equipment, which receives, to be sent data to from the task of equipment, after data composition data frame to be sent
The data being stored in main equipment send chained list.
The data frame includes ID number, check code, data length, data field and the request type of data task.
S30: the data in real-time judge main equipment send in chained list whether have data, if so, and CS pin is low electricity
Usually, from chained list one data frame of acquisition is sent, which is sent to from equipment, is stopped after the data frame is sent completely
Send data.
It is general SPI data transmission procedure that the data, which are sent to from the process of equipment, i.e., the described number is first by data
Frame is stored in the transmission buffer area of main equipment, then the data for sending buffer area is transferred to main equipment as unit of a byte
It is the data of a byte to out of, equipment shift register by 8 in main equipment shift register in shift register
Transfer.
S40: it is received in buffer area from the data deposit that equipment sends over main equipment.
The data that the main equipment sends over first are stored in out of, equipment shift register, are shifted from shift register
To out of, equipment reception buffer area, since shift register is usually 8, so data deposit receives buffering in the embodiment
Area is as unit of a byte i.e. 8.
S50: receiving buffer area from equipment timing scan, forms a complete data frame when receiving the data in buffer area
When, to handling in the data frame, generate one group of new data after processing, it will treated after data reformulate data frame
Then write-in sets high level for CS pin from the transmission buffer area of equipment, main equipment is waited to read the data from from equipment.
Processing described in the embodiment includes verification data frame, parsing data frame and processing data.
Processing data described in the embodiment includes one such or a variety of: encryption data, ciphertext data, generation are plucked
, to generate random number.
S60: main equipment receives CS pin when being high signal, reads data from from equipment, every to read the inspection of byte
The level height situation of a CS pin is surveyed, if CS pin is high level, represent data, also no reading is not finished, and continues to read
Data represent data and have read and finish if CS pin is low level, stop reading data, start to carry out next data
The preparation of the transmission of frame.
S70: when having read a byte by main equipment every time from equipment, turn the data in buffer area are sent from equipment
The reading next time that main equipment is waited from the shift register of equipment is moved on to, if do not counted out of equipment transmission buffer area
According to when, be set as low level from equipment by CS pin, notice main equipment data are all sent completely, and can be received next
A request.
The embodiment of the present invention one provides a kind of SPI communication method based on dual controller, draws outside not increasing additionally
In the case where line, the data communication of primary processor and encryption chip is carried out using the four-wire system of spi bus itself, by CS
Pin is arranged to common input and output pin, and by procedure logical control system, the function of flexible Application CS can be assisted effectively
Main equipment and the communication issue from equipment are adjusted, the external pin resource of processor is saved.
Embodiment two:
The present invention also provides a kind of SPI communication terminal device based on dual controller, including memory, equipment and storage
In the memory and the computer program that can run on said device, the equipment execute real when the computer program
Step in the above method embodiment of the existing embodiment of the present invention one.
Further, as an executable scheme, the SPI communication terminal device based on dual controller can be table
Laptop computer, notebook, palm PC and cloud server etc. calculate equipment.The SPI communication based on dual controller is whole
End equipment may include, but be not limited only to, equipment, memory.It will be understood by those skilled in the art that above-mentioned based on dual controller
The composed structure of SPI communication terminal device is only based on the example of the SPI communication terminal device of dual controller, composition pair
The restriction of SPI communication terminal device based on dual controller may include or combining certain than above-mentioned more or fewer components
A little components or different components, such as the SPI communication terminal device based on dual controller can also include input and output
Equipment, network access equipment, bus etc., it is not limited in the embodiment of the present invention.
Further, as an executable scheme, alleged processor can be central processing unit (Central
Processing Unit, CPU), it can also be other general processors, digital signal processor (Digital Signal
Processor, DSP), it is specific integrated circuit (Application Specific Integrated Circuit, ASIC), existing
At programmable gate array (Field-Programmable Gate Array, FPGA) or other programmable logic device, discrete
Door or transistor logic, discrete hardware components etc..General processor can be microprocessor or the processor can also
To be any conventional processor etc., the processor is in the control of the SPI communication terminal device based on dual controller
The heart utilizes the various pieces of the entire SPI communication terminal device based on dual controller of various interfaces and connection.
The memory can be used for storing the computer program and/or module, and the processor is by operation or executes
Computer program in the memory and/or module are stored, and calls the data being stored in memory, described in realization
The various functions of SPI communication terminal device based on dual controller.The memory can mainly include storing program area and storage
Data field, wherein storing program area can application program needed for storage program area, at least one function (for example sound plays
Function, image player function etc.) etc.；Storage data area, which can be stored, uses created data (such as audio number according to mobile phone
According to, phone directory etc.) etc..In addition, memory may include high-speed random access memory, it can also include non-volatile memories
Device, such as hard disk, memory, plug-in type hard disk, intelligent memory card (Smart Media Card, SMC), secure digital (Secure
Digital, SD) card, flash card (Flash Card), at least one disk memory, flush memory device or other volatibility are solid
State memory device.
Further, described computer-readable to deposit the embodiment of the invention also provides a kind of computer readable storage medium
Storage media is stored with computer program, and the above method of the embodiment of the present invention is realized when the computer program is executed by processor
Step.
If the integrated module/unit of the SPI communication terminal device based on dual controller is with SFU software functional unit
Form realize and when sold or used as an independent product, can store in a computer readable storage medium.Base
In such understanding, the present invention realizes all or part of the process in above-described embodiment method, can also pass through computer program
It is completed to instruct relevant hardware, the computer program can be stored in a computer readable storage medium, the calculating
Machine program is when being executed by processor, it can be achieved that the step of above-mentioned each embodiment of the method.Wherein, the computer program includes
Computer program code, the computer program code can for source code form, object identification code form, executable file or certain
A little intermediate forms etc..The computer-readable medium may include: any entity that can carry the computer program code
Or device, recording medium, USB flash disk, mobile hard disk, magnetic disk, CD, computer storage, read-only memory (ROM, Read-Only
Memory), random access memory (RAM, Random Access Memory), electric carrier signal, telecommunication signal and software
Distribution medium etc..It should be noted that the content that the computer-readable medium includes can be according to making laws in jurisdiction
Requirement with patent practice carries out increase and decrease appropriate, such as in certain jurisdictions, according to legislation and patent practice, computer
Readable medium does not include electric carrier signal and telecommunication signal.
Although specifically showing and describing the present invention in conjunction with preferred embodiment, those skilled in the art should be bright
It is white, it is not departing from the spirit and scope of the present invention defined by the appended claims, it in the form and details can be right
The present invention makes a variety of changes, and is protection scope of the present invention.
Claims (6)
1. a kind of SPI communication method based on dual controller, it is characterised in that: the following steps are included:
S10: setting host mode for main equipment, will be set as slave mode from equipment, main equipment and passes through between equipment
MISO, MOSI, SCLK are connected with tetra- line SPI signal of CS, wherein the setting of MISO, MOSI and SCLK signal and general SPI signal
It is arranged identical, CS signal, which is used to control main equipment, still receives data for sending data；
S20: it when main equipment, which receives, to be sent data to from the task of equipment, is stored in after data composition data frame to be sent
Data in main equipment send chained list；
S30: data in real-time judge main equipment send in chained list whether have data, if so, and CS pin when being low level,
A data frame is obtained from chained list is sent, which is sent to from equipment, stops sending after the data frame is sent completely
Data；
S40: it is received in buffer area from the data deposit that equipment sends over main equipment；
S50: receiving buffer area from equipment timing scan, when receiving data one complete data frame of composition in buffer area,
To handling in the data frame, one group of new data is generated after processing, it will treated writes after data reformulate data frame
Enter from the transmission buffer area of equipment, then set high level for CS pin, main equipment is waited to read the data from from equipment；
S60: main equipment receives CS pin when being high signal, reads data from from equipment, every to read byte detection one
The level height situation of secondary CS pin continues reading data and stops if CS pin is low level if CS pin is high level
Data are only read, the preparation for carrying out the transmission of next data frame is started；
S70: it when having read a byte by main equipment every time from equipment, is transferred to the data in buffer area are sent from equipment
The reading next time that main equipment is waited from the shift register of equipment, if without data out of equipment transmission buffer area
When, low level is set as from equipment by CS pin.
2. the SPI communication method according to claim 1 based on dual controller, it is characterised in that: the data frame includes
ID number, check code, data length, data field and the request type of data task.
3. the SPI communication method according to claim 1 based on dual controller, it is characterised in that: described in step S50
Processing includes verification data frame, parsing data frame and processing data.
4. the SPI communication method according to claim 3 based on dual controller, it is characterised in that: the processing data packet
Include one such or a variety of: encryption data, ciphertext data generate abstract, generate random number.
5. a kind of SPI communication terminal device based on dual controller, including memory, processor and it is stored in the memory
In and the computer program that can run on the processor, which is characterized in that the processor executes the computer program
The step of Shi Shixian such as Claims 1 to 4 the method.
6. a kind of computer readable storage medium, the computer-readable recording medium storage has computer program, and feature exists
In realization is such as the step of Claims 1 to 4 the method when the computer program is executed by processor.
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| CN113886297A (en) * | 2021-09-27 | 2022-01-04 | 北京中电华大电子设计有限责任公司 | SPI concurrent communication SE device and method based on DMA |
| CN113886297B (en) * | 2021-09-27 | 2023-12-01 | 北京中电华大电子设计有限责任公司 | SPI concurrent communication SE device and method based on DMA |
| CN114124613A (en) * | 2021-11-22 | 2022-03-01 | 江苏科技大学 | Anti-competition industrial 485 networking system and control method thereof |
| CN114124613B (en) * | 2021-11-22 | 2023-11-21 | 江苏科技大学 | Industrial 485 networking system capable of preventing competition and control method thereof |
| CN114546925A (en) * | 2022-03-08 | 2022-05-27 | 合肥富煌君达高科信息技术有限公司 | Multi-device communication device and method suitable for high-speed camera |
| CN114546925B (en) * | 2022-03-08 | 2022-09-02 | 合肥富煌君达高科信息技术有限公司 | Multi-device communication device and method suitable for high-speed camera |
| CN115941102A (en) * | 2022-10-31 | 2023-04-07 | 三峡智控科技有限公司 | Method for synchronous communication between controllers by connecting MCU and FPGA through SPI |
| CN115941102B (en) * | 2022-10-31 | 2023-09-15 | 三峡智控科技有限公司 | Method for synchronous communication between controllers connected with MCU and FPGA by SPI |
| CN115580507A (en) * | 2022-12-09 | 2023-01-06 | 北京紫光青藤微系统有限公司 | Communication bus structure and communication method |
| CN115834739A (en) * | 2023-02-16 | 2023-03-21 | 石家庄科林电气股份有限公司 | Receiving method of indefinite-length data frame in platform area intelligent convergence terminal SPI communication |
| CN116069698A (en) * | 2023-03-10 | 2023-05-05 | 苏州萨沙迈半导体有限公司 | SPI data transmission method and device |
| CN116069698B (en) * | 2023-03-10 | 2023-10-31 | 苏州萨沙迈半导体有限公司 | SPI data transmission method and device |
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