CN115941102A - Method for synchronous communication between controllers by connecting MCU and FPGA through SPI - Google Patents
Method for synchronous communication between controllers by connecting MCU and FPGA through SPI Download PDFInfo
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Abstract
The invention discloses a method for synchronous communication between controllers by connecting an MCU (micro control unit) and an FPGA (field programmable gate array) through an SPI (serial peripheral interface). And the FPGA simultaneously undertakes the optical fiber communication task and the extended switching value refreshing task. The MCU in the main controller is started by the synchronous signal to send optical fiber communication data and an opening signal to the FPGA through the SPI, and the optical fiber communication data which is sent to the MCU by the FPGA not only is received to the bottom but also comprises an opening signal. The other responses after receiving the optical fiber communication data are called slave controllers, and the invention reduces the communication times while using long data frame communication for the master controller and considering the expansion switching value and the optical fiber communication. The slave controller uses a method of mixed use of long and short data frames, refreshes switching values and inquires optical fiber communication states through the short data frames, and uses the long data frames to exchange optical fiber communication data, so that the problem of inquiring the optical fiber communication states when the MCU is used as SPI communication master equipment is solved, and finally synchronous communication can be realized by connecting the MCU with the controller of the FPGA by using the SPI.
Description
Technical Field
The invention belongs to the technical field of synchronous communication and optical fiber communication, and particularly relates to a method for synchronous communication between controllers by connecting an MCU (micro control unit) and an FPGA (field programmable gate array) through an SPI (serial peripheral interface) in a scene requiring the coordination of a plurality of controllers by synchronous signals.
Background
An MCU (Micro Controller Unit, micro control Unit) is a core of the embedded control system, performs functions such as measurement, control calculation, and process processing, and includes various types such as a C51 Controller, an X86 Controller, and an ARM Controller.
The FPGA (Field-Programmable Gate Array) has the characteristics of high main frequency and multipath parallel processing, and can be matched with the MCU to perform the functions of switching value expansion, data communication, data processing and the like, so that the task burden of the MCU can be effectively reduced, and the application range of the controller is expanded.
The switching value is a value having only two states of 0 and 1, for example, the switching contact on/off state is an on amount, and the command for controlling the switch off is an on amount. Most pins of the MCU are multiplexed, and can be used as a switching value or assigned to an internal integrated peripheral. After the FPGA is used, the switching values are directly connected to the FPGA, and the MCU indirectly controls the switching values through communication, so that pin resources of the MCU can be greatly saved.
The SPI (Serial Peripheral Interface) bus system is a synchronous Serial Peripheral Interface that allows the MCU to communicate with various peripherals in a Serial manner to exchange information, and generally uses 4 lines: serial Clock Line (SCLK), master input/slave output data line MISO, master output/slave input data line MOSI, and active low slave select line NSS. Fig. 1 is a typical connection: one master device is connected to one slave device. In SPI communication, when NSS signal is low level, communication is effective, at this time, the master device outputs data through MOSI, meanwhile, clock signals are provided for the slave device through SCLK pin, and the slave device sends data to the master device through MISO pin. This communication method requires the master device and the slave device to transmit data with the same length for normal communication. In addition, because the SPI communication is started and stopped by the master device, the slave device must prepare data to be transmitted before the master device starts communication, and timing of the master device and the slave device needs to be coordinated to ensure normal communication.
The MCU and the FPGA are connected through parallel ports, so that the parallel processing capability of the FPGA can be fully exerted, the MCU and the FPGA have no communication delay, and the MCU can sequentially inquire the state of a communication channel or read and write communication data without delay. However, the parallel port occupies more MCU pin resources, including 16 data lines, 20 address lines, and control lines such as chip select, and may use up to 41 MCU pins.
When the MCU is connected with the FPGA by adopting the SPI, the MCU occupies less MCU pin resources, but the communication delay between the SPI between the MCU and the FPGA causes that the MCU can not inquire external data or state in real time. In addition, if the MCU and the FPGA need to execute the variable-length SPI data communication, the coordination of the correct response of the FPGA serving as the slave equipment is also complicated.
The MCU can start communication interruption to ensure the reliability of communication when performing flow control with low real-time requirement, but generally performs communication in an inquiry manner when performing real-time control. The DMA (Direct Memory Access) function is an important means for the MCU to carry out data communication, the MCU only needs to set the transmission length when transmitting data, starts transmission after preparing the data, receives the data only needs to inquire whether the data with the preset length is received, does not need to inquire transceiving byte by byte, and effectively reduces the occupancy rate of the MCU.
Some embedded control systems require multiple controller modules to cooperatively control, and optical fiber communication between the controllers is coordinated by a synchronization signal. Taking the scheme of the intelligent rectifier bridge as an example, the control channel and the intelligent rectifier bridge are both provided with controllers. The two control channels are used for on-line control and standby control; a plurality of intelligent rectifier bridges are used for connecting output current in parallel. And the control result calculated by the control channel is transmitted to the intelligent rectifier bridge through the optical fiber network to be synchronously executed. The intelligent rectifier bridges must output current according to the same control angle to ensure that the output currents of the rectifier bridges are close. For this purpose, a synchronous communication method for the excitation system is proposed (CN 201610224359.6 a synchronous communication method between a parallel intelligent rectifier bridge and a regulator): the intelligent rectifier bridge in the optical fiber communication is a main controller, a communication period is started by driving of a synchronous signal, the state of the intelligent rectifier bridge is sent to a control channel, the control channel is a slave controller, a control result is responded immediately after data of any main controller are received, and the next period of each rectifier bridge is executed according to the result. The optical fiber network connection is as shown in fig. 2, and optical fiber connection is arranged between any two controllers.
The FPGA processes data receiving and sending of the optical fiber channel and also gives consideration to the control switching value of the controller, reads the input and output state from the outside and transmits the input and output state to the MCU, and obtains the output level of the corresponding pin of the output data operation from the MCU. The requirement on the refresh frequency of the switching value is not high, and the frequency of the switching value is not lower than the frequency of the synchronous signal.
Disclosure of Invention
The invention provides a method for synchronous communication between controllers connected with an MCU and an FPGA by using an SPI, aiming at solving the problems that the state of receiving external data cannot be inquired when the controllers connected with the MCU and the FPGA by using the SPI are used for communication, and the problem that the variable-length SPI data communication is difficult to execute between the MCU and the FPGA.
The technical scheme of the invention is as follows: a method for realizing synchronous communication between controllers connected with an MCU and an FPGA by using an SPI is applied between controllers which are interconnected point to point through optical fibers, wherein a controller for driving data communication by a synchronous signal is a master controller, a slave controller responds after receiving information of the master controller, the controllers participating in the optical fiber communication are both the MCU and the FPGA connected by using the SPI, the MCU in the SPI communication of the MCU and the FPGA in the two controllers is both used as a master, and the FPGA simultaneously undertakes an optical fiber communication task and a controller expansion switching value refreshing task;
in the main controller, a synchronous signal starts the MCU to send optical fiber communication data and an opening signal to the FPGA through the SPI, the FPGA realizes expansion and sending the optical fiber communication data to other controllers, and meanwhile, the FPGA transmits the optical fiber communication data and the opening signal received through the optical fiber port to the MCU;
in the slave controller, the MCU and the FPGA carry out short data frame communication according to at least 5 times of synchronous frequency through the SPI, the switching value is refreshed regularly, the state that the optical fiber port receives optical fiber communication is inquired from the short data frame received from the FPGA, when the MCU detects that the optical fiber port receives any main controller optical fiber communication data, the first refreshing period informs the FPGA to start optical fiber communication data interaction through control words arranged in the short data frame, data needing to be sent through an optical fiber network is processed into optical fiber communication data, the MCU starts long data frame communication and sends the optical fiber communication data to the FPGA, the FPGA sends all the optical fiber communication data received from other controllers to the MCU, and the optical fiber communication data sent by the MCU are immediately sent to all the other controllers through the optical fiber ports after the optical fiber communication data are received.
Furthermore, a receiving optical fiber and a transmitting optical fiber are arranged between the master controller and the slave controller, a receiving optical fiber and a transmitting optical fiber are arranged between each pair of the master controller and the slave controller, each optical fiber is provided with an independent optical fiber port, and the controllers are connected with different controllers in a multi-path and parallel mode through different optical fiber ports.
The optical fiber port of the controller for sending data is uniquely corresponding to the optical fiber port of the controller for receiving data.
Furthermore, in the master controller, the data of the SPI communication between the MCU and the FPGA are equal in length and comprise a plurality of port transceiving data and switching value data which are equal in length, the switching value data of the data sent to the FPGA by the MCU are switching-out data, the switching value data of the data sent to the MCU by the FPGA are switching-in data, the port transceiving data comprise target equipment ID and self equipment ID data which are equal in length, the plurality of port transceiving data are arranged and spliced into optical fiber communication data according to optical fiber port serial numbers, and the switching value data are arranged and spliced at the tail part of the optical fiber communication data.
Further, in the master controller, the communication process after the synchronization signal starts the MCU includes:
the synchronous signal triggers MCU interruption, MCU collects data to be sent and expands the data to splice and then transmits the data to FPGA through SPI, FPGA realizes expansion and sends communication data to other controllers, FPGA receives MCU data through SPI and at the same time splices the expanded input data and the received data of other controllers into a long data frame to be sent to MCU according to the serial numbers of the optical fiber ports connected with each controller, and then FPGA transmits the data sent by MCU to all other controllers through optical fiber network.
Preferably, in the slave controller, the data of the SPI communication performed by the MCU and the FPGA are equal in length, and when short data frame communication is performed, the short data frame sent by the FPGA to the MCU contains the state of whether each optical fiber port receives optical fiber communication data in addition to the open input amount, and the short data frame output by the MCU to the FPGA also includes a control word in addition to the open data;
the data which needs to be sent through each optical fiber port is equal in length, and when long data frame communication is carried out, the data of the MCU and the FPGA for SPI communication comprises optical fiber communication data consisting of a plurality of ports with equal length for receiving and sending data.
The optical fiber communication data which is formed by a plurality of ports with equal length and is transmitted and received by the MCU and the FPGA when the long data frame is communicated is also called a long data frame.
Preferably, the lengths of the optical fiber communication data sent by the controller through the optical fiber are consistent, after the MCU receives the optical fiber communication data, the MCU decomposes the optical fiber communication data into data received by each port according to the data lengths, and detects whether the port is matched with the equipment ID in the data, whether the target ID is matched with the ID of the MCU, and if the port is not matched with the equipment ID, an optical fiber connection error is alarmed.
When the MCU in the controller is connected with the FPGA by the SPI, the pin resource of the MCU is saved, and meanwhile, the problem of internal communication delay is also brought. The invention uses long data frame communication in the main controller, and reduces the communication times while giving consideration to the expansion of switching value and optical fiber communication. The slave controller uses a method of mixed use of long and short data frames, refreshes switching values and inquires optical fiber communication states through the short data frames, and uses the long data frames to exchange optical fiber communication data, so that the problem of inquiring the optical fiber communication states when the MCU is used as SPI communication master equipment is solved, and finally synchronous communication can be realized by connecting the MCU with the controller of the FPGA by using the SPI.
Drawings
FIG. 1 is a schematic diagram of the SPI communication connection between the MCU and the FPGA;
FIG. 2 is a schematic diagram of an optical fiber network of an excitation system configured with 4 intelligent rectifier bridges;
FIG. 3 is a schematic diagram of a communication data format of the host controller;
FIG. 4 is a communication protocol schematic for on-off refresh from a controller;
FIG. 5 is a schematic diagram of a communication protocol for communicating data with the FPGA through the SPI interactive optical fiber from the controller MCU;
fig. 6 is a schematic diagram of internal and external communication timing sequences of each controller of the optical fiber communication network driven by a synchronization signal.
Detailed Description
The following detailed description of specific embodiments of the invention is provided in conjunction with the accompanying drawings.
The method is applied to scenes needing synchronous signal coordination and combined control of a plurality of controllers, the controllers are internally connected with the MCU and the FPGA by the SPI, and the FPGA simultaneously undertakes optical fiber communication tasks and expansion switching value refreshing tasks. The controller which drives data communication by the synchronous signal is a master controller, the controller which responds after receiving the information of the master controller is a slave controller, and the MCU in the two controllers and the MCU in the SPI communication of the FPGA are both used as masters.
Taking the excitation system shown in fig. 2 as an example, the intelligent rectifier bridge is used as a main controller of a communication network, in the communication process shown in fig. 6, a synchronization signal triggers the input of a timer of the main controller MCU to capture interrupt, the main controller MCU starts the DMA transmission of the SPI after splicing the optical fiber communication data composed of the data to be transmitted at each optical fiber port and the outgoing signal into a long data frame in a timer interrupt service program, and the main controller FPGA splices the optical fiber communication data composed of the data received at each previous optical fiber port and the incoming signal into a long data frame with the length equal to the long data frame transmitted by the main controller MCU and transmits the long data frame to the main controller MCU. The data length sent by each master controller in the optical fiber communication is consistent, the optical fiber communication data is arranged according to the port serial number corresponding to receiving and sending in the SPI communication in the master controller, and the switching value signal is added at the tail part.
For example, a controller has 8 optical fiber ports, each port transmits and receives data with a length of 128 bytes, the first byte is the ID of the optical fiber communication destination device, and the second byte is the device ID providing the data. If a master controller device ID of 3 needs to be sent to a controller with device ID of 7, the first byte of the data frame output by the controller through the fiber port is 7, and the second byte is 3. The signals 32 (4 bytes) are expanded and opened (one signal occupies 1 bit, 8 bits are 1 byte, and 4 bytes are total), the SPI communication data format is shown in fig. 3, and the transceiving lengths are 1028 (128 × 8+ 4) bytes. The main controller FPGA intercepts data according to a preset length after receiving a long data frame of the main controller MCU, immediately sends the data to other equipment through a corresponding optical fiber port, the other equipment comprises a slave controller and other main controllers, and the FPGA of each controller receives the data through the optical fiber port.
The control channel in the excitation system shown in fig. 2 is a slave controller of a communication network, and data such as a control amount and the like can be transmitted to other controllers through an optical fiber network after receiving data of any master controller (an intelligent rectifier bridge in the excitation system) (the other controllers refer to controllers which are connected with the slave controller through optical fibers and include the intelligent rectifier bridge and another control channel).
The extended switching value refresh and data communication of the MCU of the slave controller are divided into two communication protocols, in the short frame communication protocol of the switching value refresh, the MCU of the slave controller is a master party of SPI communication, and the switching value is refreshed at a frequency which is at least 5 times that of a synchronous signal. As shown in fig. 4, the short data frame sent by the MCU of the slave controller includes an open signal and a command byte for starting the fiber communication data interaction, and when the command byte is 1, prompts the FPGA of the slave controller to perform the fiber communication data interaction next time; the short data frame sent from the FPGA of the controller comprises an input quantity signal and a state of whether each optical fiber port receives information, the lowest bit of a status byte of the optical fiber port is the status of the No. 1 optical fiber port, the highest bit is the status of the No. 8 optical fiber port, and the status bit is 1 to indicate that the port receives the data. Where fiber ports 1-7 are connected to a master controller and port 8 is connected to another slave controller.
The MCU of the slave controller executes short data frame communication for refreshing the switching value under a normal state, once the optical fiber port state sent by the FPGA of the slave controller detects that data from the master controller is received, the MCU of the slave controller immediately sets an optical fiber communication data interaction command when the switching value is refreshed next time, and the MCU of the slave controller informs the FPGA of the slave controller to execute long data frame communication for optical fiber communication data interaction at the SPI. Namely, long data frame communication is executed in the next query period after the optical fiber communication data interaction command is sent: the MCU of the slave controller arranges a plurality of equal-length port transceiving data which need to be sent through the optical fiber in sequence according to the port serial numbers to form a long data frame, namely optical fiber communication data. The long data frame communication data format is as shown in fig. 5, the slave controller has 8 total optical fiber ports, the length of the data received and transmitted by each port is 128 bytes, the data is arranged according to the port serial number, after receiving the long data frame communication command, the FPGA of the slave controller immediately splices all the received port received and transmitted data in the optical fiber communication into a long data frame according to the optical fiber port serial number, and the long data frame of the MCU of the slave controller is received and simultaneously transmitted to the MCU of the slave controller in the next polling period. Except that the tail part of the long data frame has no switching value data, the long data frame communication from the SPI inside the controller is consistent with the data format of the SPI communication inside the master controller. And the FPGA of the slave controller receives the long data frame sent by the MCU of the slave controller through the SPI and then is connected with the long data frame to forward other controllers through optical fibers. Under the drive of a synchronous signal, with the combination of the communication time sequence of each slave controller of the optical fiber communication network of a specific example as shown in fig. 6, after receiving the optical fiber communication data of the master controller at the optical fiber port 1, the slave controller FPGA sets the position corresponding to the optical fiber port status byte to 1 in the SPI short data frame interacted with the MCU; the MCU of the slave controller detects that any one of the low 7 bits of the optical fiber port status byte is 1 in the subsequent switching value refreshing period, confirms that the optical fiber communication data of the master controller are received, sets an optical fiber communication data interaction command to be 1 in the next switching value refreshing period, and informs the FPGA of the slave controller to prepare to execute long data frame communication; the MCU of the slave controller arranges the port transceiving data needing to be sent through the optical fiber in sequence according to the port serial number to form a long data frame. And sending the long data frame communication to the slave controller FPGA, splicing all received data in the optical fiber communication into a long data frame according to the serial number of the optical fiber port immediately after the slave controller FPGA receives a long data frame communication command, and transmitting the data received through the optical fiber network to the MCU while receiving the optical fiber communication data of the MCU. And after receiving the optical fiber communication data sent by the MCU, decomposing the optical fiber communication data according to the length and then transmitting the optical fiber communication data to other controllers through the optical fiber ports.
The controller for sending the optical fiber communication data is communicated with different controllers through different optical fiber ports, the optical fiber port sending end of the controller for sending the optical fiber communication data is in point-to-point connection with the optical fiber port receiving end of the controller for receiving the optical fiber communication data, so that a one-to-one mapping relation is provided, the received optical fiber communication data is provided with a target equipment ID and an equipment ID for providing data, and the MCU can also determine which optical fiber port of the controller for sending the data comes from and whether the target ID is consistent with the ID of the MCU through the arrangement position of the port transceiving data. The optical fiber network connection has a determined sequence, if the MCU detects that the equipment ID carried by the data is not matched with the optical fiber port or the target ID is not consistent with the ID of the MCU, an alarm of 'optical fiber connection error' is given immediately, and a debugging person is prompted to check the optical fiber connection.
When the MCU in the controller is connected with the FPGA by adopting the SPI, the problem of internal communication delay is also brought while pin resources of the MCU are saved. The invention uses long data frame communication in the main controller, and reduces the communication times while giving consideration to the expansion of switching value and optical fiber communication. The slave controller uses a method of mixed use of long and short data frames, refreshes switching values and inquires optical fiber communication states through the short data frames, and uses the long data frames to exchange optical fiber communication data, so that the problem of inquiring the optical fiber communication states when the MCU is used as SPI communication master equipment is solved, and finally synchronous communication can be realized by connecting the MCU with the controller of the FPGA by using the SPI.
The internal SPI communication of controller means that the MCU from the controller communicates effectively with FPGA when the NSS signal is the low level in the SPI communication with FPGA, and MCU passes through MOSI to FPGA output data this moment, provides clock signal for FPGA through the SCLK pin simultaneously, and FPGA passes through the MISO pin and sends data to MCU.
Claims (6)
1. A method for realizing synchronous communication between controllers connected with an MCU and an FPGA by using an SPI is applied between controllers which are interconnected point to point through optical fibers, wherein a controller for driving data communication by a synchronous signal is a master controller, and a slave controller responds after receiving information of the master controller;
in the main controller, a synchronous signal starts an MCU to send optical fiber communication data and an opening signal to an FPGA through an SPI, the FPGA expands and releases the optical fiber communication data and sends the optical fiber communication data to other controllers, and meanwhile, the FPGA transmits the optical fiber communication data and the opening signal received through an optical fiber port to the MCU;
in the slave controller, the MCU and the FPGA carry out short data frame communication according to at least 5 times of synchronous frequency through the SPI, the switching value is refreshed regularly, the state that the optical fiber port receives optical fiber communication is inquired from the short data frame received from the FPGA, when the MCU detects that the optical fiber port receives any main controller optical fiber communication data, the FPGA is informed to start optical fiber communication data interaction through control words arranged in the short data frame in a first refreshing period, data needing to be sent through an optical fiber network is processed into optical fiber communication data, the MCU starts long data frame communication in a second refreshing period and sends the optical fiber communication data to the FPGA, and the FPGA sends all the optical fiber communication data received from other controllers to the MCU in the refreshing period and immediately sends the optical fiber communication data to other controllers through the optical fiber network after the optical fiber communication data sent by the MCU are received.
2. The method of claim 1, wherein two optical fibers are arranged between each pair of master controller and slave controller, each optical fiber is provided with a respective independent optical fiber port, and the controllers are connected with different controllers in multi-way and in parallel through different optical fiber ports.
3. The method according to claim 2, wherein in the master controller, the data of the MCU and the FPGA in SPI communication are equal in length and include a plurality of port transceiving data and switching value data of equal length, the switching value data of the data sent by the MCU to the FPGA is open data, the switching value data of the data sent by the FPGA to the MCU is open data, the port transceiving data includes target device ID and self device ID data of equal byte length, the plurality of port transceiving data are arranged and spliced according to the fiber port serial numbers to form fiber communication data, and the switching value data are arranged and spliced at the tail of the fiber communication data.
4. The method of claim 2, wherein the step of enabling the communication process after the MCU by the synchronization signal in the master controller comprises:
the synchronous signal triggers MCU interruption, MCU collects data to be sent and expands the data to splice and then transmits the data to FPGA through SPI, FPGA realizes expansion and sends communication data to other controllers, FPGA receives MCU data through SPI and at the same time splices the expanded input data and the received data of other controllers into a long data frame to be sent to MCU according to the serial numbers of the optical fiber ports connected with each controller, and then FPGA transmits the data sent by MCU to all other controllers through optical fiber network.
5. The method according to any one of claims 3 to 4, wherein the data of SPI communication between the MCU and the FPGA in the slave controller is equal in length, when short data frame communication is performed, the short data frame sent to the MCU by the FPGA contains the state that whether each optical fiber port receives optical fiber communication data besides the input amount, and the short data frame output to the FPGA by the MCU also comprises a control word besides the input data;
the data which needs to be sent through each optical fiber port is equal in length, and when long data frame communication is carried out, the data of the MCU and the FPGA for SPI communication comprises optical fiber communication data consisting of a plurality of ports with equal length for receiving and sending data.
6. The method of claim 5, wherein the lengths of the optical fiber communication data sent by the controller through the optical fiber are consistent, after the MCU receives the optical fiber communication data, the MCU decomposes the optical fiber communication data into the data received by each port according to the data lengths, and detects whether the port is matched with the equipment ID in the data, whether the target ID is matched with the ID of the MCU, and if not, the MCU alarms that the optical fiber connection is wrong.
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| CN117312221A (en) * | 2023-11-28 | 2023-12-29 | 西安现代控制技术研究所 | Triggering type SPI data communication method |
| CN117312221B (en) * | 2023-11-28 | 2024-03-15 | 西安现代控制技术研究所 | Triggering type SPI data communication method |
| CN117687347A (en) * | 2024-02-02 | 2024-03-12 | 三峡智控科技有限公司 | Synchronous wave recording method and device based on FPGA and communication network |
| CN117687347B (en) * | 2024-02-02 | 2024-04-09 | 三峡智控科技有限公司 | Synchronous wave recording method and device based on FPGA and communication network |
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