CN111966623A - Method for real-time full-duplex reliable communication between MCU and multiple FPGAs by using SPI - Google Patents

Abstract

The invention discloses a method for real-time full-duplex reliable communication between an MCU and a plurality of FPGAs by using SPI, which aims to solve the problems that the prior art does not fully utilize the characteristics of the SPI full duplex and a bus, can not reliably transmit indefinite-length data in real time, and the communication speed of the MCU and the FPGAs is not effectively improved. The MCU terminal of the invention is used as a host to continuously and circularly send subdata to the plurality of FPGA terminals through the SPI, and the plurality of FPGA terminals are used as slaves to continuously and circularly send the subdata to the MCU terminal after receiving the enabling signal of the host. And after receiving the subdata, the two parties judge the data property according to the 1 st byte, if the subdata is invalid, the data property is directly discarded, if the subdata is retransmitted, if the subdata is valid, whether the check bit is correct is judged, if the check bit is incorrect, retransmission is applied, if the check bit is correct, the length of the frame data is calculated according to the 2 nd to 3 rd bytes, and the complete frame data is formed.

Description

Method for real-time full-duplex reliable communication between MCU and multiple FPGAs by using SPI

Technical Field

The invention relates to a method for real-time full-duplex reliable communication between an MCU and a plurality of FPGAs by using SPI.

Background

In the field of communication, it is a common scenario to use an FPGA to process data in combination with chips of other architectures, and SPI is an abbreviation of a Serial Peripheral Interface (Serial Peripheral Interface), and is a high-speed, full-duplex, synchronous communication bus, which occupies a small number of pins, has a high data transmission rate, and has a simpler logic compared to an ultra-high speed Interface, and thus, can be used for full-duplex communication between an MCU and an FPGA.

At present, the use of the SPI between the MCU and the FPGAs mainly performs the reading and writing of the registers and the continuous reading of the data, but does not fully utilize the characteristics of the full duplex and the bus thereof, so that the indefinite-length data cannot be reliably transmitted in real time, and the communication speed between the MCU and the FPGAs is not effectively increased, which is specifically explained from the following three aspects:

(1) real-time full duplex

The SPI communication is limited to a master-slave relationship, and when the master transmits data, the master reads the data at the same time, and when the master does not transmit data, the slave cannot transmit data, and when the master is connected to a plurality of slaves, effective real-time duplex communication cannot be performed.

(2) Reliable transmission of indefinite length data

The host computer reads the data sent by the slave computer while sending the data, all the data cannot be accurately received under the condition that the length of the data sent by the slave computer is unknown, and the SPI has no error detection mechanism and cannot be reliably transmitted.

(3) Communication speed of MCU and FPGA

MCU passes through SPI to FPGA send data, and according to the mode and the difference of agreement of SPI, the speed that FPGA received data is different, only suitable mode and agreement can effectively improve communication speed.

Disclosure of Invention

The invention aims to solve the problems that in the prior art, reading and writing of a register and continuous reading of data are mainly carried out by using SPI between an MCU and a plurality of FPGAs, full duplex and bus characteristics are not fully utilized, indefinite-length data cannot be reliably transmitted in real time, and the communication speed of the MCU and the FPGA is not effectively improved, and provides a method for carrying out real-time full duplex reliable communication between the MCU and the plurality of FPGAs by using SPI.

In order to achieve the purpose, the technical scheme adopted by the invention is as follows:

a method for real-time full-duplex reliable communication between an MCU and a plurality of FPGAs by using SPI is characterized in that: simultaneously performing the steps 1 and 2 by the MCU terminal and the plurality of FPGA terminals through the SPI;

step 1, an MCU terminal sends data to a plurality of FPGA terminals;

step 1.1, the MCU end judges whether frame data needs to be sent or not; if so, the MCU end constructs a plurality of subdata from the frame data according to the data format of the transmission protocol; if not, the MCU terminal constructs a plurality of subdata from any data according to the data format of the transmission protocol; the length of the subdata is M; the data format of the transmission protocol is as follows: the 1 st byte is data property, the 2 nd to 3 rd bytes are frame data length, the 4 th to (M-1) th bytes are transmitted data, and the Mth byte is check bit; the data properties comprise valid data, invalid data and a retransmission application; wherein M is more than or equal to 5;

step 1.2, the MCU terminal is used as a host to continuously and circularly send subdata to the plurality of FPGA terminals through the SPI;

step 1.3, each FPGA end receives the subdata and judges the data property according to the 1 st byte; if the data property is valid, executing step 1.4; if the data property is invalid, ending; if the data property is a retransmission application, retransmitting the subdata;

step 1.4, judging whether the Mth byte is correct or not by the FPGA terminal; if yes, executing step 1.5; if not, sending an instruction to the MCU terminal to apply for retransmission;

step 1.5, the FPGA end calculates the length of frame data according to bytes 2-3;

step 1.6, the FPGA end sequentially composes the 4 th to (M-1) th bytes in the plurality of subdata into complete frame data according to the frame data length, and the process is finished;

step 2, a plurality of FPGA terminals send data to the MCU terminal;

step 2.1, judging whether frame data needs to be sent by the FPGA end; if so, the FPGA end constructs a plurality of subdata from the frame data according to the data format of the transmission protocol; if not, the FPGA end constructs a plurality of subdata from any data according to the data format of the transmission protocol; the length of the subdata is M; the data format of the transmission protocol is as follows: the 1 st byte is data property, the 2 nd to 3 rd bytes are frame data length, the 4 th to (M-1) th bytes are transmitted data, and the Mth byte is check bit; the data properties comprise valid data, invalid data and a retransmission application; wherein M is more than or equal to 5;

step 2.2, the plurality of FPGA terminals are used as slave computers to continuously and circularly send the subdata to the MCU terminal through the SPI;

step 2.3, the MCU end receives the subdata and judges the data property according to the 1 st byte; if the data property is valid, executing step 2.4; if the data property is invalid, ending; if the data property is a retransmission application, retransmitting the subdata;

step 2.4, the MCU end judges whether the Mth byte is correct or not; if yes, executing step 2.5; if not, sending an instruction to the FPGA end for applying for retransmission;

step 2.5, the MCU end calculates the length of frame data according to the 2 nd to 3 rd bytes;

and 2.6, the MCU terminal sequentially combines the 4 th to (M-1) th bytes in the plurality of subdata into complete frame data according to the frame data length, and the process is finished.

Further, in step 1.1, when the MCU has frame data to be transmitted, the 1 st byte data of the sub-data is valid data; when the MCU end has no frame data to be sent, the property of the 1 st byte data of the subdata is invalid data;

in the step 2.1, when the FPGA end has frame data to be sent, the 1 st byte data of the subdata is valid data; when the FPGA end has no frame data to be sent, the property of the 1 st byte data of the subdata is invalid data.

Further, in step 1.1, the valid data is 0xAA, the invalid data is 0xAB, and the retransmission application is 0 xAC;

in step 2.1, the valid data is 0xAD, the invalid data is 0xAE, and the retransmission request is 0 xAF.

Further, in step 1.1, M is 140;

in step 2.1, M is 140.

Further, in step 1.2, the MCU side sends the subdata cyclically using DMA.

Further, the FPGA end enables to receive the subdata according to the chip selection level of the MCU end, and the specific steps are as follows:

when the chip selection of the MCU terminal is low level, the FPGA terminal receives subdata at the first rising edge of the clock, and stores the subdata into the shift register at the first falling edge of the clock.

Further, the SPI master frequency is 84 MHz.

Compared with the prior art, the invention has the beneficial effects that:

(1) according to the method for real-time full-duplex reliable communication between the MCU and the plurality of FPGAs by using the SPI, the MCU terminal continuously and circularly sends the subdata to the plurality of FPGA terminals, so that the FPGA terminals can also send the subdata in real time, and the purpose of real-time full-duplex communication between the MCU and the plurality of FPGAs through the SPI is achieved; the subdata is constructed according to a certain data format, so that the data property, the data correctness and the frame data length of the subdata can be determined, and the reliability of transmitting the data with indefinite length is improved;

(2) the MCU terminal circularly transmits the subdata by using the DMA, so that a large amount of resources are not occupied, and the transmission real-time property can be improved;

(3) the MCU end enables the SPI mode to be low level when a clock is idle, sampling is started at the first edge, and the mode can effectively improve the speed of receiving data by the FPGA.

Drawings

FIG. 1 is a schematic diagram showing the connection between an MCU and multiple FPGAs in the method for real-time full-duplex reliable communication between the MCU and the multiple FPGAs by using SPI;

FIG. 2 is a flow chart of the MCU terminal transmitting data to a plurality of FPGA terminals in the method of the present invention;

FIG. 3 is a flow chart of the FPGA terminal transmitting data to the MCU terminal in the method of the present invention;

FIG. 4 is a timing diagram of the FPGA terminal receiving sub-data in the method of the present invention.

Detailed Description

The present invention will be described in detail below with reference to the accompanying drawings and specific embodiments.

According to the method for the MCU and the FPGAs to carry out real-time full-duplex reliable communication by using the SPI, the MCU is connected with the FPGAs, as shown in figure 1, the MCU is a host computer, the FPGA is a slave computer, and the MCU is communicated with the FPGAs by using the SPI.

The Clock Phase (CPHA) and the Clock Polarity (CPOL) of the SPI may be 0 or 1, respectively, and the corresponding 4 combinations constitute 4 modes (modes) of the SPI, which are:

Mode 0：CPOL＝0,CPHA＝0；

Mode 1：CPOL＝0,CPHA＝1；

Mode 2：CPOL＝1,CPHA＝0；

Mode 3：CPOL＝1,CPHA＝1。

the level of the clock signal SCLK (1: idle high level; 0: idle low level) when the clock polarity CPOL, that is, SPI, is idle;

the clock phase CPHA, or SPI, starts sampling at the SCLK second edge (0: the start of the first edge; 1: the start of the second edge).

In this embodiment, the MCU terminal enables the SPI Mode to select Mode 0, i.e., the clock is at idle low level, and sends and reads the sub-data at the first rising edge of the clock, so that the FPGA terminal sends and reads the sub-data.

And (3) simultaneously carrying out the steps 1 and 2 by the MCU terminal and the plurality of FPGA terminals through the SPI.

Step 1, the MCU terminal sends data to the plurality of FPGA terminals, and the flow is shown in FIG. 2.

Step 1.1, the MCU end judges whether frame data needs to be sent or not; if so, the MCU end constructs a plurality of subdata from the frame data according to the data format of the transmission protocol; if not, the MCU terminal constructs a plurality of subdata from any data according to the data format of the transmission protocol; the length of the subdata is M; the data format of the transmission protocol is as follows: the 1 st byte is data property, the 2 nd to 3 rd bytes are frame data length, the 4 th to (M-1) th bytes are transmitted data, and the Mth byte is check bit; the data properties comprise valid data, invalid data and a retransmission application; wherein M is more than or equal to 5.

In this embodiment, the length M of the sub data sent by the MCU is 140, and the data format is shown in the following table:

when the MCU end has frame data to be sent, the 1 st byte data of the subdata is effective data, specifically 0 xAA; when the MCU end has no frame data to be sent, the property of the 1 st byte data of the subdata is invalid data, specifically 0 xAB; when the MCU terminal needs to retransmit by the FPGA terminal, the property of the 1 st byte data of the subdata is a retransmission application, specifically 0 xAC.

And step 1.2, the MCU terminal is used as a host to continuously and circularly send subdata to the plurality of FPGA terminals through the SPI.

The MCU terminal circularly transmits the sub data by using DMA (Direct Memory Access) for providing high-speed data transmission between the peripheral and the Memory or between the Memory and the Memory, which can improve the real-time performance of the transmission. The MCU end sets the SPI master frequency to 84MHz, and transmits 140 bytes each time, and each transmission time is 140 × 8 × 1000/84000000 ═ 0.013 ms. Thus, when one FPGA end has subdata to be sent, the delay is 0.013ms, when 10 FPGA ends have subdata to be sent, the maximum delay is 0.013ms x 10 to 0.13ms, and the real-time performance can be achieved.

Step 1.3, each FPGA end receives sub data, and the time sequence of receiving the sub data is shown in fig. 4. The FPGA end serves as a slave and can run according to the chip selection high-low enable of the host, when the chip selection of the MCU end is low level, the FPGA end receives the subdata on the first rising edge of the clock, and the subdata is stored in the shift register on the first falling edge of the clock. After the master sends the sub data, the slave can process the sub data only by the delay of half period, and the time of half period is 1/84MHz/2 which is 6 ns.

The FPGA end judges the data property according to the 1 st byte; if the data property is valid, executing step 1.4; if the data property is invalid, directly discarding, and ending; and if the data property is the retransmission application, retransmitting the sub-data.

Step 1.4, judging whether the Mth byte is correct or not by the FPGA terminal; if yes, executing step 1.5; if not, sending an instruction to the MCU terminal to apply for retransmission.

And step 1.5, the FPGA end calculates the length of the frame data according to the 2 nd to 3 rd bytes.

And step 1.6, the FPGA end sequentially forms the 4 th to 139 th bytes in the plurality of subdata into complete frame data according to the frame data length, and the process is finished.

And 2, sending data to the MCU by the plurality of FPGA terminals, wherein the flow is shown in FIG. 3.

Step 2.1, judging whether frame data needs to be sent by the FPGA end; if so, the FPGA end constructs a plurality of subdata from the frame data according to the data format of the transmission protocol; if not, the FPGA end constructs a plurality of subdata from any data according to the data format of the transmission protocol; the length of the subdata is M; the data format of the transmission protocol is as follows: the 1 st byte is data property, the 2 nd to 3 rd bytes are frame data length, the 4 th to (M-1) th bytes are transmitted data, and the Mth byte is check bit; the data properties comprise valid data, invalid data and a retransmission application; wherein M is more than or equal to 5.

In this embodiment, the length M of the sub data sent by the FPGA terminal is 140, and the data format is shown in the following table:

when frame data is sent at the FPGA end, the 1 st byte data of the subdata is effective data, specifically 0 xAD; when no frame data is sent at the FPGA end, the property of the 1 st byte data of the subdata is invalid data, specifically 0 xAE; when the FPGA end needs to retransmit the MCU end, the property of the 1 st byte data of the subdata is retransmission application, specifically 0 xAF.

And 2.2, continuously and circularly sending the subdata to the MCU terminal by using the plurality of FPGA terminals as slave machines through the SPI.

Step 2.3, the MCU end receives the subdata and judges the data property according to the 1 st byte; if the data property is valid, executing step 2.4; if the data property is invalid, directly discarding, and ending; and if the data property is the retransmission application, retransmitting the sub-data.

Step 2.4, the MCU end judges whether the Mth byte is correct or not; if yes, executing step 2.5; if not, sending an instruction to the FPGA end for applying for retransmission.

And 2.5, calculating the length of the frame data by the MCU according to the 2 nd to 3 rd bytes.

And 2.6, the MCU terminal sequentially combines the 4 th to (M-1) th bytes in the plurality of subdata into complete frame data according to the frame data length, and the process is finished.

Claims (7)

1. A method for real-time full-duplex reliable communication between an MCU and a plurality of FPGAs by using SPI is characterized in that: simultaneously performing the steps 1 and 2 by the MCU terminal and the plurality of FPGA terminals through the SPI;

step 1, an MCU terminal sends data to a plurality of FPGA terminals;

step 1.1, the MCU end judges whether frame data needs to be sent or not; if so, the MCU end constructs a plurality of subdata from the frame data according to the data format of the transmission protocol; if not, the MCU terminal constructs a plurality of subdata from any data according to the data format of the transmission protocol; the length of the subdata is M; the data format of the transmission protocol is as follows: the 1 st byte is data property, the 2 nd to 3 rd bytes are frame data length, the 4 th to (M-1) th bytes are transmitted data, and the Mth byte is check bit; the data properties comprise valid data, invalid data and a retransmission application; wherein M is more than or equal to 5;

step 1.2, the MCU terminal is used as a host to continuously and circularly send subdata to the plurality of FPGA terminals through the SPI;

step 1.3, each FPGA end receives the subdata and judges the data property according to the 1 st byte; if the data property is valid, executing step 1.4; if the data property is invalid, ending; if the data property is a retransmission application, retransmitting the subdata;

step 1.4, judging whether the Mth byte is correct or not by the FPGA terminal; if yes, executing step 1.5; if not, sending an instruction to the MCU terminal to apply for retransmission;

step 1.5, the FPGA end calculates the length of frame data according to bytes 2-3;

step 1.6, the FPGA end sequentially composes the 4 th to (M-1) th bytes in the plurality of subdata into complete frame data according to the frame data length, and the process is finished;

step 2, a plurality of FPGA terminals send data to the MCU terminal;

step 2.1, judging whether frame data needs to be sent by the FPGA end; if so, the FPGA end constructs a plurality of subdata from the frame data according to the data format of the transmission protocol; if not, the FPGA end constructs a plurality of subdata from any data according to the data format of the transmission protocol; the length of the subdata is M; the data format of the transmission protocol is as follows: the 1 st byte is data property, the 2 nd to 3 rd bytes are frame data length, the 4 th to (M-1) th bytes are transmitted data, and the Mth byte is check bit; the data properties comprise valid data, invalid data and a retransmission application; wherein M is more than or equal to 5;

step 2.2, the plurality of FPGA terminals are used as slave computers to continuously and circularly send the subdata to the MCU terminal through the SPI;

step 2.3, the MCU end receives the subdata and judges the data property according to the 1 st byte; if the data property is valid, executing step 2.4; if the data property is invalid, ending; if the data property is a retransmission application, retransmitting the subdata;

step 2.4, the MCU end judges whether the Mth byte is correct or not; if yes, executing step 2.5; if not, sending an instruction to the FPGA end for applying for retransmission;

step 2.5, the MCU end calculates the length of frame data according to the 2 nd to 3 rd bytes;

and 2.6, the MCU terminal sequentially combines the 4 th to (M-1) th bytes in the plurality of subdata into complete frame data according to the frame data length, and the process is finished.

2. The method of claim 1 for real-time full-duplex reliable communication between an MCU and multiple FPGAs using SPIs, wherein:

in the step 1.1, when the MCU end has frame data to send, the 1 st byte data of the sub data is valid data; when the MCU end has no frame data to be sent, the property of the 1 st byte data of the subdata is invalid data;

in the step 2.1, when the FPGA end has frame data to be sent, the 1 st byte data of the subdata is valid data; when the FPGA end has no frame data to be sent, the property of the 1 st byte data of the subdata is invalid data.

3. The method of claim 2 for real-time full-duplex reliable communication between an MCU and multiple FPGAs using SPIs, wherein:

in step 1.1, the valid data is 0xAA, the invalid data is 0xAB, and the retransmission application is 0 xAC;

in step 2.1, the valid data is 0xAD, the invalid data is 0xAE, and the retransmission request is 0 xAF.

4. The method of claim 3 for real-time full-duplex reliable communication between an MCU and multiple FPGAs using SPIs, wherein:

in the step 1.1, M is 140;

in step 2.1, M is 140.

5. The method of claim 4 for real-time full-duplex reliable communication between an MCU and multiple FPGAs using SPIs, wherein:

in the step 1.2, the MCU side circularly transmits the subdata using DMA.

6. The method for real-time full-duplex reliable communication between an MCU and multiple FPGAs using SPI according to any of claims 1 to 5, characterized by:

the FPGA end enables to receive subdata according to chip selection high and low of the MCU end, and the specific steps are as follows:

when the chip selection of the MCU terminal is low level, the FPGA terminal receives subdata at the first rising edge of the clock, and stores the subdata into the shift register at the first falling edge of the clock.

7. The method of claim 6 for real-time full-duplex reliable communication between an MCU and multiple FPGAs using SPIs, wherein:

the SPI dominant frequency is 84 MHz.

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