CN103714029B - Novel two-line synchronous communication protocol and application - Google Patents

Abstract

The invention provides a novel two-line synchronous communication protocol and application thereof. Bidirectional data transmission between a host and a slave is performed on the basis of two signal lines; the two signal lines which are connected between the host and the slave in a defined manner comprise a clock line Y2CK and a data line Y2D; when in an idle state, the clock line Y2CK stays at high level; the host sends out a periodic clock signal through the clock line Y2CK; data are inputted or outputted at a first change edge of the clock signal through the data line Y2D; and data are inputted or outputted by the salve at a second change edge of the clock signal through the data line Y2D. A novel two-line synchronous communication interface based on the protocol, electrical equipment using the interface, an interface circuit completing the protocol and a circuit chip using the interface circuit have the advantages of simplicity, feasibility and convenience in use.

Description

Novel two wires synchronous communications protocol and application

Technical field the present invention relates to electric digital data communications technology, the application such as the bus protocol that particularly between device or equipment, data transmit and interface thereof.

Background technology modern electronic equipment has departed from not open integrated circuit (chip).Between equipment and equipment, even between device and device, between circuit and circuit, all there is a large amount of data communication.The serial communication using serial line interface to carry out data widely and there is a large amount of standards.These standards can successfully communicate between the distinct device of many different manufacturers to make, and to some basic regulationses sent and reception both sides make in data mode, the method for synchronization, coded system, data check mode and data transfer rate etc., that is communication protocol.These agreements are formulated, as TCP/IP by professional standard association usually; Also some communication protocols are had to be defined, as I2C and SPI by equipment manufacturer oneself.

The serial line interface (Serial Interface) provided for following these agreements then ensures that realizing one one order of data on communication line from circuit aspect transmits, as long as communication line simply arrives a pair transmission line just can realize two-way communication, and transmission and reception both sides realize information exchange by this two-way communication.Existing serial communication even can utilize telephone wire, and communication distance, from several meters to a few km, greatly reduces cost.Short-range communication, such as, communication between computer and mouse/keyboard is especially applicable to adopting serial line interface.

Universal asynchronous receiver/transmitter (UART), also claims UART, is the most widely used a kind of serial line interface in single-chip microcomputer, is almost the standard configuration of all 8 single-chip microcomputers at present.The domestic single-chip microcomputer of major part is downloaded and is all undertaken by UART.Its weak point is, because UART is asynchronous communications protocol, require comparatively strict to the baud rate of communicating pair for realizing data syn-chronization, thus speed can not be too high, is generally no more than 256kbps.This speed limit is enough to download program, to being that in-circuit emulator interface then seems awkward with UART, can not meet the high real-time requirement of current software development to in-circuit emulation.In addition, because UART only supports the setting of several baud rate, as common 9600,14400,19200,38400,56000bps etc., admissible error range is little, generally between ± 4%; And require that communicating pair arranges identical baud rate, use more loaded down with trivial details.

The deficiencies in the prior art part is also, along with function becomes increasingly complex, for solving test problem, existing chip generally has the functional mode such as test pattern or scanning, and most of chip is assigned with test pin or makes chip enter AD HOC by the combination of specific pin for this reason.But the employing of these methods, or add chip area, or reduce chip antijamming capability and make that chip is as easy as rolling off a log under severe applied environment enters error pattern.

Summary of the invention the technical problem to be solved in the present invention is for above-mentioned the deficiencies in the prior art part, and proposes a kind of two wires synchronous communications protocol and interface, to reach efficient data communication, and then with the emulation of facilitating chip and test.

For solving the problems of the technologies described above, basic conception of the present invention is: be many host buses as the I2C bus be widely used in two line locking communications, being connected to, this bus has unique address designation from machine, data transmission between slave only supports a single byte transmission means, and data can the artificial debugging that carries out between slave of fast transport but be unprofitable to; For ease of in-circuit emulation and the debugging of chip, the present invention attempts setting up a kind of novel two wires synchronous communications protocol and carrys out supplementary existing chip interface, in this agreement, the starting and ending condition of the Address Confirmation between simplification slave and transmission data will be conducive to the high efficiency of transmission of valid data, enrich command context more helpful to in-circuit emulation debugging if attempt further in data transmission.

As realize the present invention design technical scheme be a kind of novel two wires synchronous communications protocol is provided, carries out the bidirectional data transfers between slave based on two holding wires; Especially, method is comprised:

Described two holding wires one that definition is connected between slave are clock line Y2CK, and one is data wire Y2D;

During idle condition, clock line Y2CK rests on high level;

Main frame sends periodic clock signal by clock line Y2CK, inputs or outputs along carrying out data by data wire Y2D in the first change of this clock signal; Carry out data on the second change edge of this clock signal by this data wire Y2D from machine to input or output.

Further, in such scheme, the bidirectional data transfers between slave is the combination that some elements carry out with the data transmission procedure of several basic commands; The data transmission procedure defining each basic command all starts from start bit, ends at position of rest; This start bit sends one first change when bus free along for mark with described clock line Y2CK, and position of rest sends one second change along for mark with this clock line Y2CK after the data of current basic command transfer.

In such scheme, described basic command comprises to be read address, write address, read data and writes data command, and each command format is as table:

Wherein, the length of command word is 2, and different segment values correspond to different orders; The length of transmission length is 2, and different segment values correspond to the different transmission byte number that described data export or data input; Wait for that position is the second electrical level that the first level of a lasting X clock signal period adds a lasting clock signal period, this X is 0 or natural number.The transmission little-endian of further appointment data transmits by turn; Described data export or the figure place of data input is less than or equal to 32; Described first change is along being trailing edge, and described second change edge is rising edge; Described first level is low level, and described second electrical level is high level.

In such scheme, when in definition data transmission procedure, the information bit CFG0.HEN of configuration register is effective, once detect that the time that clock line Y2CK rests on high level exceedes data end time T _conthen be judged as that present data transmission is made mistakes, slave is abandoned the data of current transmission and is returned idle condition; Or in definition data transmission procedure, once detect that clock line Y2CK rests on the low level time and exceedes data end time T _conthen be judged as that present data transmission is made mistakes, slave is abandoned the data of current transmission and is returned idle condition.Further, the low level defining clock line Y2CK exceedes T resetting time _rstfor main frame requires to reset from machine; Once detect, carry out reset operation from machine, main frame returns idle condition.Further, when main frame is in idle condition, the train of pulse detected by clock line Y2CK represents, from machine, current state is informed main frame by predetermined way.

As realizing the technical scheme of the present invention's design still, a kind of novel two wires synchronous communication interface being provided, comprising two holding wires, be i.e. clock line Y2CK and data wire Y2D; Especially, these two holding wires follow the novel two wires synchronous communications protocol described in above either a program.

As realizing the technical scheme of the present invention's design still, a kind of electrical equipment being provided, comprising the interface being connected other electrical equipment by cable, socket or plug; Especially, this interface is the novel two wires synchronous communication interface described in above scheme.

As realizing the technical scheme of the present invention's design still, a kind of novel two wires synchronous communication interface circuit is provided, be connected between a communication interface and second circuit, especially, comprise: two connect described communication interface to carry out the holding wire of bidirectional data transfers, i.e. clock line Y2CK and data wire Y2D, described clock line Y2CK provides internal clock signal line CLK for this communication interface circuit, connect the shift register of described data wire Y2D and internal clock signal line CLK respectively, descending serial data from data wire Y2D is converted to the descending parallel data transmitted through downlink data bus Y2_WDATA, or latch the up parallel data from address register or register file, displacement exports triple gate, and described in input termination, the minimum bit line of downlink data bus Y2_WDATA, exports data wire Y2D described in termination, transport to described data wire Y2D with the data serial that shift register is latched, connect the host state machine of described internal clock signal line CLK and described downlink data bus Y2_WDATA, complete the decoding of protocol command entrained by described descending parallel data to export corresponding control signal on output control line, described output control line comprises: the read pulse holding wire Y2_RD connecting described second circuit, connect the writing pulse signal line Y2_WR of described register file and second circuit, write control signal line AR_ WR and the data direction control line DIR being connected the described control end exporting triple gate that is shifted of link address register, connect the latch control line SR_CON of described shift register, described address register also connects described internal clock signal line CLK and downlink data bus Y2_WDATA respectively, and content that is controlled or that transmit this address register is described up parallel data, or described descending parallel data is write this address register, described register file also connects described internal clock signal line CLK, downlink data bus Y2_WDATA and the address data bus AddrR from described address register respectively, controlled to each internal register or carry out addressing read operation to provide described up parallel data, or carry out addressing writing operation by internal register corresponding for described descending parallel data writing address.Further, the input line of this host state machine also comprises the acknowledge lines ACK connecting described second circuit.

In such scheme, described register file also comprises debug registers DBI-r and memory access interface register MAI, this debug registers DBI-r also provides debug command data bus DBI to connect described second circuit, and memory access interface register MAI also connects the visit data bus MAI_RDATA from described second circuit.Further, described downlink data bus Y2_WDATA and described address data bus AddrR also connects toward described second circuit.

Particularly, in such scheme, also comprise the burr filter circuit connecting described clock line Y2CK, the output line of this burr filter circuit is described internal clock signal line CLK; Also comprise burst pulse to occur and control circuit, this burst pulse occurs and the data output end of control circuit connects described clock line Y2CK through a Three-State door, control output end connects the control end of described Three-State door, and this burst pulse occurs and the input of control circuit connects from one group of status signal lines CPU-STAT of described second circuit, the configuration control line CFG0.NOTIF from the configuration register CFG0 of register file or the idle condition line Y2_IDLE from described host state machine.Further, also comprise the test state machine connecting described internal clock signal line CLK, described register file also comprises the scratchpad register TST of output data toward this test state machine; This test state machine also connects described writing pulse signal line Y2_WR, and the output line of this test state machine comprises two enable control signal wire CP-EN and SCAN-EN connecting described second circuit.

In such scheme, the output line of described burr filter circuit also comprises the reseting signal line EXT_ RSTB connecting described second circuit, host state machine and described test state machine; Or also comprise the error of transmission report line Y2_FAULTB that the described host state machine of connection carries out error reporting, now, the second configuration control line CFG0.HEN from the configuration register CFG0 of register file is access in this burr filter circuit to carry out enable control to this error of transmission report line Y2_FAULTB.

As realizing the technical scheme of the present invention's design still, a kind of IC chip being provided, especially, comprising the novel two wires synchronous communication interface circuit described in above each scheme.

The novel two wires high efficiency synchronous communication mode that these measures adopt, main frame with do not need to arrange certain operating frequency in advance from machine communication process, very easy to use; The communications frequency range that can support is large, from tens KHz to tens MHz; Speed is fast.And general single-chip microcomputer on-line debugging application is operated in 1MHz or higher, chip testing then available 10MHz is even higher, and thus these agreements substantially increase chip testing efficiency and save the expense of chip on automated test device.Interface circuit saves input/output port resource and chip area greatly, has and realizes advantage easily, is especially applicable to the application scenario of short-distance transmission.

Accompanying drawing explanation

Fig. 1 is the structured flowchart of Y2 interface circuit of the present invention;

Fig. 2 is the functional status transition diagram of host state machine in Fig. 1;

Fig. 3 is the functional status transition diagram of test state machine in Fig. 1;

Fig. 4 is the holding wire time diagram in " reading address " order data transmitting procedure;

Fig. 5 is the holding wire time diagram in " write address " order data transmitting procedure;

Fig. 6 is the holding wire time diagram in " read data " order data transmitting procedure, exports for 1 byte data;

Fig. 7 is the holding wire time diagram in " writing data " order data transmitting procedure, is input as example with 1 byte data;

Fig. 8 is that the low level of Y2CK holding wire is greater than ED time T _conand coherent signal waveform schematic diagram when being less than resetting time;

Fig. 9 is that communication process Y2CK holding wire high level exceedes data end time T _conand coherent signal waveform schematic diagram during CFG0.HEN=0;

Figure 10 is that communication process Y2CK holding wire high level exceedes data end time T _conand coherent signal waveform schematic diagram during CFG0.HEN=1;

Figure 11 is that Y2CK holding wire low level exceedes T resetting time _rsttime coherent signal waveform schematic diagram;

Figure 12 is the logic circuit diagram of host state machine in Fig. 1.

Detailed description of the invention

Below, shownschematically most preferred embodiment sets forth the present invention further by reference to the accompanying drawings.

The present invention proposes a kind of brand-new two wires synchronous communications protocol and method (for the sake of simplicity, hereafter claiming Y2 agreement), carries out the bidirectional data transfers between slave based on two holding wires.The basic methods that Y2 agreement carries out data transmission is: these two holding wires one that definition is connected between slave are clock line Y2CK, and one is data wire Y2D; During idle condition (namely without any command transfer), clock line Y2CK rests on high level, and now the state of data wire arbitrarily (that is, this data wire no matter be in high level or low level is all meaningless to data communication); Main frame sends periodic clock signal by clock line Y2CK, inputs or outputs along carrying out data by data wire Y2D in the first change of this clock signal; Carry out data on the second change edge of this clock signal by this data wire Y2D from machine to input or output.Here, " first change edge " and " the second change edge " can turn to " trailing edge " and " rising edge " by tool respectively, or as required respectively tool turn to " rising edge " and " trailing edge ".For discussing conveniently, follow-up acquiescence " the first change edge " is " trailing edge " herein, and " the second change edge " is " rising edge ".

On this basis, Y2 agreement carries out specification to the communication form of data further, concrete grammar comprises: make the bidirectional data transfers between slave be the combination that some elements carry out with the data transmission procedure of several basic commands, the two wires data communication between slave must be combined as unit with these basic commands arbitrary or its and carry out; The data transmission procedure defining each basic command all starts from start bit, ends at position of rest; This start bit sends one first change when bus free (namely not having any data to transmit between slave) along for mark with described clock line Y2CK, and position of rest sends one second change along for mark with this clock line Y2CK after the data of current basic command transfer.The benefit of this method for normalizing is, the start-stop of data transmission can be retrained by clock line Y2CK, the monitoring complexity that simple order starts and termination condition makes Y2 interface circuit factor data transmit reduces and is more easily implemented, and all synchro digital sequential especially can be adopted to carry out completing circuit design.

Under this specification, in order to improve interface data treatment effeciency so that in-circuit emulation or debugging, agreement of the present invention breaks through the restriction that existing I2C agreement only has reading and writing data two kinds to order, expand described basic command and comprise " reading address " (AR), " write address " (AW), " read data " (DR) and " writing data " (DW) four kinds order, these command format most preferred embodiments are as table:

Can see, read/write address and the order that reads and writes data have bigger difference: read/write address only comprises address date section; Read and write data " transmission length ", " data input, output " and " wait position " section.With specific embodiment, each field is elaborated below.The length of command word can be set as 2, and different segment values correspond to different orders, for but be not limited to following table:

Order	Command word segment value (binary value)
		Read address	10
Write address	11
		Read data	00
Write data	01

Transmission length length can be set as 2, different segment values correspond to described data export or data input different transmission byte numbers, for but be not limited to following table:

Transmission length segment value (binary system)	Transmission byte number
		00	8 bit data, 1 byte
01	16 bit data, 2 bytes (half-word)
		10	24 bit data, 3 bytes
11	32 bit data, 4 bytes (word)

Like this, Y2 agreement can support multibyte transmission means, and be no matter the slave communication for 8,16 or 32, Y2 interface can be handled a situation with ease and can not bring the loss in performance or deficiency because only supporting a kind of data length to transmit.Wait for that position only occurs when performing " read data " or " writing data " and ordering, asynchronous and establish for solving clock zone between slave.Wait for that position can be set as that first level (such as low level) of a lasting x clock signal period adds the second electrical level (such as high level) of a lasting clock signal period, wherein x is 0 or natural number, depends on the clock synchronous situation between slave.Utilize this wait position main frame can greatly relax the clock frequency requirement from machine, can to wait for thus can because signal is slowly to infinitely great close to direct current from the cpu clock frequency of machine close to unlimited in theory.

In addition, Y2 agreement of the present invention can also be limited in communication process further, and serial data is all that little-endian transmits by turn.

The novel two wires synchronous communication interface extended out according to agreement of the present invention, can only include two holding wires, follow clock line Y2CK and the data wire Y2D of Y2 agreement of the present invention.Described interface can be applied on arbitrary electrical equipment, is used for connecting other electrical equipment with same interface by cable, socket or plug.

In order to realize Y2 agreement of the present invention, the present invention proposes a kind of novel two wires synchronous communication interface circuit, structure as shown in Figure 1.This interface circuit is connected between a communication interface and second circuit, and the mode that described communication interface simplifies most adopts Y2 interface of the present invention, is also likely the arbitrary connectivity port being compounded with other signal of communication certainly.Interface circuit side of the present invention comprises two and connects described communication interface to carry out the holding wire of bidirectional data transfers, i.e. clock line Y2CK and data wire Y2D; Opposite side comprises various parsing and performs Y2 protocol command and carry out the various signal input/output lines of data interaction with described second circuit.

Specifically, as shown in Figure 1, clock line Y2CK described in interface circuit of the present invention provides internal clock signal line CLK for this interface circuit.In order to prevent data transmission distortion under long-distance transmissions, the burr filter circuit that one connects described clock line Y2CK can be set up in interface circuit, this burr filter circuit utilizes digital filter, such as but not limited to RC low pass filter, filter deburring operation is carried out to the clock signal from described clock line Y2CK and produces internal clock signal and export toward described internal clock signal line CLK.

Interface circuit of the present invention also comprises the shift register connecting described data wire Y2D and described internal clock signal line CLK respectively, descending serial data from this data wire Y2D is converted to the descending parallel data transmitted through downlink data bus Y2_WDATA, or latch the up parallel data from address register or register file.Design a displacement and export triple gate, it is made to input the minimum bit line of downlink data bus Y2_WDATA described in termination, export data wire Y2D described in termination, then have an opportunity shift register latch data by turn " serial " transport to described data wire Y2D, whether export and can be controlled by host state machine.The described host state machine connecting internal clock signal line CLK is the core of interface circuit of the present invention, host state machine is by connecting downlink data bus Y2_WDATA and receive descending parallel data and completing the decoding of protocol command entrained by it to export corresponding control signal on each output control line, these output control lines comprise: the read pulse holding wire Y2_RD connecting described second circuit, connect the writing pulse signal line Y2_WR of described register file and second circuit, write control signal line AR_ WR and the data direction control line DIR being connected the described control end exporting triple gate that is shifted of link address register, connect the latch control line SR_CON of described shift register.In order to keep the slave in data communication process synchronously to adapt to the situation that slave is in different clock-domains, the input line of this host state machine also comprises the acknowledge lines ACK connecting described second circuit.Interface circuit of the present invention will save a lot of exterior I O resource by this built-in state machine.

The described address register also connecting described internal clock signal line CLK and downlink data bus Y2_WDATA respectively is also the indispensable part of this interface circuit, under the signal transmitted through described write control signal line AR_ WR controls, complete the data input and output of each basic command of agreement of the present invention: or the content transmitting this address register is described up parallel data; Or described descending parallel data is write this address register.The described register file connecting host state machine also connects described internal clock signal line CLK, downlink data bus Y2_WDATA and the address data bus AddrR from described address register respectively, controlled to each internal register or carry out addressing read operation to provide described up parallel data, or carry out addressing writing operation by internal register corresponding for described descending parallel data writing address.If the data of described address register are preferably 8, then can pass through it in 0 ~ 255 addressing range to each internal register direct addressin in register file.Described internal register comprises version register REVID, device register DEVID and configuration register CFG0 etc., can expand according to the needs of project.

In the present invention, for the main frame of communication, it exports (AW/DW order) at the trailing edge of Y2CK or receives (AR/DR order) data; On the contrary, for communication from machine, it the rising edge of Y2CK receives (AW/DW order) or output (AR/DR order) data.Below in conjunction with the state transition graph of Fig. 2, be changed to example to perform in 4 basic command processes from the state of the host state machine of machine interface circuit, the timing variations of the Y2 interface signal line of Fig. 4 ~ illustrated in Figure 7 be described in detail in detail:

Order is the content that requirement reads address register from machine Y2 interface circuit " to read address (AR) "; Main frame can be understood from the internal register specified by machine Current Address Register by it.Fig. 4 illustrates the Y2 interface sequence in this order data transmitting procedure.When main frame is not given an order, clock line Y2CK is first in high level, from machine first as Fig. 2 is in idle condition M_IDLE; Main frame first sends a trailing edge (i.e. start bit) on clock line Y2CK, overturns as " order accepting state " M_INS, data direction control line DIR are low level from state such as Fig. 2 of owner's state machine; And then first send as Fig. 4 main frame sends command field 2 ' b10(due to LSB by turn at each clock line Y2CK trailing edge on data wire Y2D, therefore Y2D is it is seen that 2 ' b01), overturn as " address output state " M_AR from state such as Fig. 2 of owner's state machine, latch control line SR_CON simultaneously by connecting shift register sends and reads control impuls AR_RD, after the content of address register is latched to shift register by AddrR data wire, data direction control line DIR becomes high level, and data wire Y2D becomes output line; As Fig. 4 main frame discharges the driving to data wire Y2D thereupon, from the rising edge OPADD stream A0 ~ A7 by turn of machine clock line Y2CK in 8 then; On clock line Y2CK, send a rising edge (position of rest) with aft engine and terminate this order, turn back to idle condition M_IDLE from state such as Fig. 2 of owner's state machine, data direction control line DIR reduces to low level, and data wire Y2D reverts to input line.Visible, one time AR data transmission procedure will spend 11.5 clock signal periods.Wholely read address process read pulse holding wire Y2_RD, writing pulse signal line Y2_WR all keeps low level.

" write address (AW) " order is that requirement writes an address in the address register of Y2 interface circuit; Main frame is write in address register target register address the direct addressin realized from machine internal register by it and is accessed.Fig. 5 illustrates the Y2 interface sequence in this order data transmitting procedure.When main frame is not given an order, clock line Y2CK is first in high level, from machine first as Fig. 2 is in idle condition M_IDLE; Main frame first sends a trailing edge (i.e. start bit) on clock line Y2CK, is " order accepting state " M_INS from state such as Fig. 2 upset of owner's state machine; And then as Fig. 5 main frame sends command field 2 ' b11 by turn at each clock line Y2CK trailing edge on data wire Y2D, be " address input state " M_AW from state such as Fig. 2 upset of owner's state machine; As Fig. 5 in 8 backward a clock line Y2CK trailing edge, main frame is sent address stream A0 ~ A7 by turn from low level to a high position, while reception A7, host state machine sends write control signal by write control signal line AR_WR, shift register descending parallel data writing address register out, these data will to remain in address register always until the address date of being ordered by next " write address " cover; Complete aft engine sends a rising edge (position of rest) and terminates this order on clock line Y2CK, turns back to idle condition M_IDLE from state such as Fig. 2 of owner's state machine.Equally, once this AW data transmission procedure will spend 11.5 clock signal periods.Whole write address process data direction controlling line DIR, read pulse holding wire Y2_RD, writing pulse signal line Y2_WR all keep low level.

" read data (DR) " order is the content that requirement reads register specified by slave addresses register; The data of this appointment register can be 8,16,24 or 32.Fig. 6 illustrates the Y2 interface sequence in this order data transmitting procedure.From machine first as Fig. 2 is in idle condition M_IDLE; Main frame sends a trailing edge (i.e. start bit) on clock line Y2CK, is " order accepting state " M_INS from state such as Fig. 2 upset of owner's state machine; And then as Fig. 6 main frame sends command field 2 ' b00 by turn at each clock line Y2CK trailing edge on data wire Y2D, be " read data length condition " M_DR_LEN from state such as Fig. 2 upset of owner's state machine; Main frame such as Fig. 6 sends out data length field value 2 ' b00(again to read the data instance of 1 byte), " read data wait state " M_DR_WAIT is become from state such as Fig. 2 of owner's state machine, at this moment data direction control line DIR becomes high level, and host state machine sends the read pulse signal of a clock cycle on read pulse holding wire Y2_RD; The driving of main frame release simultaneously to data wire Y2D, tranmitting data register signal on clock line Y2CK always, exports x " 0 " from machine at data wire Y2D; If what " read data " order was read is the register of Y2 clock zone, such as REVID, DEVID, shift register is because this read pulse signal effectively and the latches data from register file after detecting useful signal on latch control line SR_CON; Otherwise, such as read the register of described second circuit, wait for the response impulse of the acknowledge lines ACK from second circuit, after this response impulse arrives, latch above control line SR_CON and produce useful signal, from the high level that machine exports 1 clock signal period at data wire Y2D, the data from register file are made to be latched to shift register." read data carries out state " M_DR_GO is become subsequently from state such as Fig. 2 of owner's state machine; If Fig. 6 is at the rising edge output stream D0 ~ D7 by turn of ensuing 8 clock line Y2CK; Finally, main frame sends position of rest, and return M_IDLE from state such as Fig. 2 of owner's state machine, data direction control line DIR becomes low level, and data wire Y2D reverts to input line.Whole reading data course writing pulse signal line Y2_WR maintains low level.The process of ordering and being somebody's turn to do " read data " to order from described " reading address ", the Design of Signal latched on control line SR_CON becomes to depend on reads the whether effective of control impuls AR_RD, or depends on that whether effective the signal on read pulse holding wire Y2_RD and acknowledge lines ACK is simultaneously.

Order is that requirement writes data in the register specified by address register " to write data (DW) "; Data in this designated register can be 8,16,24 or 32.Fig. 7 illustrates the Y2 interface sequence in this order data transmitting procedure, to read the data instance of 1 byte.From machine first as Fig. 2 is in idle condition M_IDLE, main frame sends a trailing edge (i.e. start bit) on clock line Y2CK, is " order accepting state " M_INS from state such as Fig. 2 upset of owner's state machine, and then first send as Fig. 7 main frame sends command field 2 ' b01(due to LSB by turn at each clock line Y2CK trailing edge on data wire Y2D, therefore it is seen that 2 ' b10 on data wire Y2D), be " writing data length state " M_DW_LEN from state such as Fig. 2 upset of owner's state machine, main frame such as Fig. 7 sends out data length field value 2 ' b00 again, becomes " write data and carry out state " M_DW_GO from state such as Fig. 2 of owner's state machine, at the trailing edge of ensuing 8 clock line Y2CK, main frame is as Fig. 7 output stream D0 ~ D7 by turn on the data line, and after receiving D7, target data just appears at downlink data bus Y2_WDATA, " writing data latency state " M_DW_WAIT is become from state such as Fig. 2 of owner's state machine, data direction control line DIR becomes high level, putting data wire Y2D is delivery outlet, on writing pulse signal line Y2_WR, send the writing pulse signal of a clock cycle simultaneously, as Fig. 7 main frame releases the driving to data wire Y2D, tranmitting data register signal on clock line Y2CK always, export x " 0 " from machine at data wire Y2D, until after response signal line ACK receives the response impulse of second circuit, synchronously shake hands complete, export the high level of 1 clock signal period at data wire Y2D from machine, and finally on clock line Y2CK after Host Detection to this high level send out a rising edge (position of rest) and carry out the finish command frame, M_IDLE is returned from state such as Fig. 2 of owner's state machine, data direction control line DIR becomes low level, data wire Y2D reverts to input port.The whole data procedures read pulse holding wire Y2_RD that writes maintains low level.

The data transmission procedure of above-mentioned 4 orders constitutes the data communications method basis of agreement of the present invention and interface circuit.Thus, in slave data communication process, as long as the data format that main frame sends meets agreement of the present invention, will respond from machine, improve the answer speed of data communication by this.

Interface circuit of the present invention can adopt all synchro digital sequential to design.Burr filter circuit can adopt wave digital lowpass filter.Host state machine is the core of this interface circuit, state machine conversion is in conjunction with the operating procedure of described 4 basic commands as shown in Figure 2, original state before this host state machine visible receives each order is idle condition M_IDLE, " start bit " detected and enter " order accepting state " M_INS, and then turn to different states according to different command words, and export the various control signals relevant to this state; Also different succeeding states is had respectively in " read data " command procedure of " writing data "; Each order all returns idle condition M_IDLE after " position of rest " occurs; State evolution in each command procedure is relevant to clock count.Therefore classical two-part or syllogic finite state machine can be adopted to design this host state machine, logic circuit structure is such as but not limited to shown in Figure 12, and host state machine comprises next state formation logic, existing state register, counter, some digital comparators and some with door.Wherein, counter determines counting initial value according to the existing state from existing state register, counts and export count value toward described next state formation logic to the clock from clock line Y2CK; This next state formation logic is according to described count value, from the command field (SHIFT [7:6]) of shift register, from the second circuit response signal of acknowledge lines ACK and jointly determine from the existing state CUR_S of existing state register and export NextState NXT_S toward described existing state register; Existing state register latches this NextState NXT_S and exports under from the clock effect of clock line Y2CK; The each digital comparator then condition of carrying out compares, each comparative result combines the output determining this host state machine by logical operation, such as but not limited to as shown in Figure 12: the output line that NextState NXT_S and " read data wait state M_DR_WAIT ", existing state CUR_S carry out AND operation through first and door and1 after comparing with comparator cmp1 and cmp2 respectively with " read data length condition M_DR_LEN " is again described read pulse holding wire Y2_RD; The output line that NextState NXT_S and " writing data latency state M_DW_WAIT ", existing state CUR_S carry out AND operation through second and door and2 after comparing with comparator cmp3 and cmp4 respectively with " write data and carry out state M_DW_GO " is again described writing pulse signal line Y2_WR; Existing state CUR_S is transport to be shifted to export the described data direction control line DIR of triple gate with " address output state M_AR ", " read data carries out state M_DR_GO ", " read data wait state M_DR_WAIT " or " writing data latency state M_DW_WAIT " through the output line that compares of comparator cmp9; Comparator cmp5 judges whether existing state CUR_S equals idle condition M_IDLE, and its output line is idle condition line Y2_IDLE; Comparator cmp6 judges that output line that whether described count value equals 10 is the write control signal line AR_WR of link address register; Comparator cmp7 judges whether command field equals 2, comparator cmp8 judges whether described count value equals 2, and the output line that the output of this two comparator cmp7, cmp8 carries out AND operation through the 3rd with door and3 is and is sent to described in shift register reads control impuls AR_RD via latching control line SR_CON.

In order to tackle contingent data transmission fault in communication process, Y2 agreement of the present invention additionally uses some methods to improve mechanism for correcting errors, such as: in definition data transmission procedure, once detect that the time that clock line Y2CK rests on low level or high level exceedes data end time T _conthen be judged as that present data transmission is made mistakes, slave is abandoned the data of current transmission and is returned idle condition; And for example: the low level of definition clock line Y2CK exceedes T resetting time _rstfor main frame requires to reset from machine; Once detect, carry out reset operation from machine, main frame returns idle condition in order to subsequent data communications; For another example: when main frame is in idle condition, the train of pulse detected by clock line Y2CK represents, from machine, current state is informed main frame by predetermined way.Nature, above-mentioned Y2 protocol embodiment basis can also be amplified and expand more contents, state no longer one by one.Above-mentioned several method and the expansion on interface circuit of the present invention thereof is introduced below in conjunction with Fig. 8 ~ 11.

Fig. 8 signal be the situation of multiplexing of transmission error report information on clock line Y2CK, correspondingly can utilize such as but not limited to RC low pass filter to monitor described clock line Y2CK in the described burr filter circuit of Fig. 1, its output line also comprises and connects the error of transmission report line Y2_FAULTB(that described host state machine carries out error reporting and do not mark in figure).In communication process, once burr filter circuit monitors low duration on clock line Y2CK and exceedes data end time T as described in Figure 8 _con(such as but not limited to 10us), then this burr filter circuit produces a width on error of transmission report line Y2_FAULTB is T _fanarrow pulse signal (assuming that this error of transmission report line is Low level effective), notify that host state machine communication makes mistakes, then as shown in Figure 2, host state machine can turn back to idle condition M_IDLE by any state of present frame order, present frame is discarded in communication process, and described burr filter circuit exceedes described ED time T once monitor high level lasting time on clock line Y2CK _con, also can produce described width is T _fanarrow pulse signal.This characteristic can be closed by the configuration register CFG0 of register file.As shown in Figure 9, during the information bit CFG0.HEN=0 of this internal register CFG0, the output of error of transmission report line Y2_FAULTB signal is consistent with Fig. 8.As shown in Figure 10, as CFG0.HEN=1., give tacit consent to and allow clock line Y2CK to rest on high level arbitrarily for a long time, the conductively-closed of described error of transmission function of reporting in communication process.Correspondingly, as shown in Figure 1, increase by can be designed and toward described burr filter circuit, enable control is carried out to described error of transmission report line Y2_FAULTB from second configuration control line (transmitting CFG0.HEN) of configuration register CFG0.

The output line that can also arrange described burr filter circuit in interface circuit of the present invention also comprises the reseting signal line EXT_ RSTB connecting second circuit.As shown in figure 11, at any time, described burr filter circuit is once the low level monitoring clock line Y2CK exceedes T resetting time _rst(such as but not limited to 20us), then export reset signal (assuming that Low level effective) on described reseting signal line EXT_RSTB, effective to second circuit; Also must produce width on described error of transmission report line Y2_FAULTB is T simultaneously _fanarrow pulse signal make host state machine turn back to idle condition M_IDLE.

The situation of another multiplexing clock line Y2CK is as shown in Figure 1, in interface circuit, also comprise burst pulse occur and control circuit, this burst pulse occurs and the data output end of control circuit connects described clock line Y2CK through a Three-State door, control output end connects the control end of described Three-State door, the input of the generation of this burst pulse and control circuit connects one group of status signal lines CPU-STAT from described second circuit, configuration control line CFG0.NOTIF from configuration register CFG0 or the described idle condition line Y2_IDLE(from host state machine produces useful signal when host state machine is in idle condition on this line, for the purpose of Fig. 1 understands, do not illustrate that this line is in figure).Like this, when being in idle condition from owner's state machine and being allowed to, the train of pulse representing its second circuit status information can mail to main frame by described Three-State door by clock line Y2CK.For example, as CFG0.NOTIF=1, allow, when Y2 interface is idle and second circuit CPU is in halted state, to send one or more burst pulses by clock line Y2CK to main frame, be about decided to be and represent described CPU this information that " is in halted state "; As CFG0.NOTIF=0, this function is prohibited or shields.

The advantage of Y2 agreement of the present invention is that the powerful order of in-circuit emulation and debugging is supported.For this reason, as shown in Figure 1, described register file can be set and also comprise debug registers DBI-r and memory access interface register MAI.Wherein, debug registers DBI-r also provides debug command data bus DBI to connect described second circuit, and memory access interface register MAI also connects the visit data bus MAI_RDATA from described second circuit.Based on these interfaces, a lot of application can be expanded on second circuit, such as, by realizing in-circuit emulation to the access of debug registers DBI-r; Internal storage access register MAI realizes the dereference to chip data RAM, program ROM, general register etc. in conjunction with debug registers DBI-r, thus breach Y2 agreement can only the restriction of direct addressin 0 ~ 255; These application, because of non-invention emphasis, no longer repeat at this.In addition, when the internal register lazy weight 255 of register file, can also design and described downlink data bus Y2_WDATA and described address data bus AddrR is also connected toward described second circuit, thus realize accessing the direct addressin of the register in second circuit.

The present invention also arranges the test state machine of a connection described internal clock signal line CLK in interface circuit in addition, and described register file also comprises the scratchpad register TST of output data toward this test state machine; This test state machine also connects described writing pulse signal line Y2_WR, and the output line of this test state machine comprises two enable control signal wire: the test enable CP-EN and scan enable SCAN-EN connecting described second circuit.Like this, in conjunction with 4 basic commands of Y2 agreement, the various testing and control to second circuit (such as but not limited to chip) can be realized.

In order to improve mechanism for correcting errors, the described reseting signal line EXT_RSTB in Fig. 1 can also be connected to described host state machine or described test state machine controls to carry out reset.

As indicated at 3, the method for designing that can adopt does not repeat at this because of similar host state machine the state transition graph of test state machine.The predetermined command value of following table to command word is specifically demonstrated (reality can be defined as different values as required in hardware implementing):

Test command	Value
		CMD_FREE	0xFF
CMD_STD	0xF1
		CMD_SCAN	0xF3
CMD_CP	0xF5

For, illustrate state respective change in interface operation under some test patterns and Fig. 3 as follows:

Enter the step of scan pattern:

1. main frame first performs " write address " order and address register is write in the address of scratchpad register TST;

2. main frame performs " writing data " order CMD_FREE is write in (indicated by address register) scratchpad register TST; Test state machine enters the idle condition TST_IDLE shown in Fig. 3 because " 0xFF " command word being detected;

3. main frame performs " writing data " order in CMD_STD write scratchpad register TST; Test state machine proceeds to armed state TST_STD because " 0xF1 " command word being detected;

4. main frame performs " writing data " order in CMD_SCAN write write scratchpad register TST; Test state machine proceeds to scanning mode TST_SCAN because " 0xF3 " command word being detected, and the signal put on scan enable control signal wire SCAN_EN is effective.

Enter the step of test pattern:

1. main frame first performs " write address " order and address register is write in the address of scratchpad register TST;

2. main frame performs " writing data " order in CMD_FREE write scratchpad register TST; Test state machine enters the idle condition TST_IDLE shown in Fig. 3 because " 0xFF " command word being detected;

3. main frame performs " writing data " order in CMD_STD write scratchpad register TST; Test state machine proceeds to armed state TST_STD because " 0xF1 " command word being detected;

4. main frame performs " writing data " order in CMD_CP write scratchpad register TST; Test state machine proceeds to test mode TST_CP because " 0xF5 " command word being detected, and the signal put on test enable control signal wire CP_EN is effective.

Through FPGA verification experimental verification, fast because having interface rate, support that frequency range is wide, require the advantages such as lower to from machine cpu clock frequency, agreement of the present invention and application thereof will become the first-selection realizing on-line debugging interface circuit.The main flow becoming future chips is expected on an integrated circuit die by integrated for interface circuit of the present invention.

In sum, architectural feature of the present invention and each embodiment all disclose in detail, and fully can demonstrate the progressive that the present invention all has enforcement in object and effect.

Although made detailed description to the present invention above and quoted embodiment as proof, can not be interpreted as expressing the scope limiting the present invention and implement.Those skilled in the art are to be understood that: namely the equivalence of all technical schemes described in right of the present invention changes and modifies, and all should belong to the scope that patent of the present invention contains.

Claims (7)

1. a novel two wires synchronous communication interface circuit, is connected between a communication interface and second circuit, it is characterized in that, comprising:

Two connect described communication interface to carry out the holding wire of bidirectional data transfers, i.e. clock line Y2CK and data wire Y2D;

Described clock line Y2CK provides internal clock signal line CLK for this communication interface circuit;

Connect the shift register of described data wire Y2D and internal clock signal line CLK respectively, descending serial data from data wire Y2D is converted to the descending parallel data transmitted through downlink data bus Y2_WDATA, or latch the up parallel data from address register or register file;

Displacement exports triple gate, and described in input termination, the minimum bit line of downlink data bus Y2_WDATA, exports data wire Y2D described in termination, transport to described data wire Y2D with the data serial that shift register is latched;

Connect the host state machine of described internal clock signal line CLK and described downlink data bus Y2_WDATA, complete the decoding of protocol command entrained by described descending parallel data to export corresponding control signal on output control line, described output control line comprises: the read pulse holding wire Y2_RD connecting second circuit, connect the writing pulse signal line Y2_WR of described register file and second circuit, write control signal line AR_WR and the data direction control line DIR being connected the described control end exporting triple gate that is shifted of link address register, connect the latch control line SR_CON of described shift register,

Described address register also connects described internal clock signal line CLK and downlink data bus Y2_WDATA respectively, and content that is controlled or that transmit this address register is described up parallel data; Or described descending parallel data is write this address register;

Described register file also connects described internal clock signal line CLK, downlink data bus Y2_WDATA and the address data bus AddrR from described address register respectively, controlled to each internal register or carry out addressing read operation to provide described up parallel data, or carry out addressing writing operation by internal register corresponding for described descending parallel data writing address.

2. novel two wires according to claim 1 synchronous communication interface circuit, is characterized in that:

Also comprise the burr filter circuit connecting described clock line Y2CK, the output line of this burr filter circuit is described internal clock signal line CLK;

Also comprise burst pulse to occur and control circuit, this burst pulse occurs and the data output end of control circuit connects described clock line Y2CK through a Three-State door, control output end connects the control end of described Three-State door, and this burst pulse occurs and the input of control circuit connects from one group of status signal lines CPU-STAT of described second circuit, the configuration control line CFG0.NOTIF from the configuration register CFG0 of register file or the idle condition line Y2_IDLE from described host state machine;

The input line of described host state machine also comprises the acknowledge lines ACK connecting described second circuit.

3. novel two wires according to claim 6 synchronous communication interface circuit, is characterized in that:

The output line of described burr filter circuit also comprises the reseting signal line EXT_RSTB connecting described second circuit, host state machine and described test state machine;

Or also comprise the error of transmission report line Y2_FAULTB that the described host state machine of connection carries out error reporting, now, the second configuration control line CFG0.HEN from the configuration register CFG0 of register file is access in this burr filter circuit to carry out enable control to this error of transmission report line Y2_FAULTB.

4. novel two wires according to claim 1 and 2 synchronous communication interface circuit, is characterized in that: described register file also comprises debug registers DBI-r or memory access interface register MAI; This debug registers DBI-r also provides debug command data bus DBI to connect described second circuit, and memory access interface register MAI also connects the visit data bus MAI_RDATA from described second circuit.

5. novel two wires according to claim 1 and 2 synchronous communication interface circuit, is characterized in that: described downlink data bus Y2_WDATA and described address data bus AddrR also connects toward described second circuit.

6. novel two wires according to claim 1 and 2 synchronous communication interface circuit, it is characterized in that: also comprise the test state machine connecting described internal clock signal line CLK, described register file also comprises the scratchpad register TST of output data toward this test state machine; This test state machine also connects described writing pulse signal line Y2_WR, and the output line of this test state machine comprises two enable control signal wire CP-EN and SCAN-EN connecting described second circuit.

7. an IC chip, is characterized in that: comprise the novel two wires synchronous communication interface circuit as described in any one of claim 1 ~ 6.