CN107562672A - A kind of system and method for improving vector network analyzer message transmission rate - Google Patents
A kind of system and method for improving vector network analyzer message transmission rate Download PDFInfo
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- CN107562672A CN107562672A CN201710742036.0A CN201710742036A CN107562672A CN 107562672 A CN107562672 A CN 107562672A CN 201710742036 A CN201710742036 A CN 201710742036A CN 107562672 A CN107562672 A CN 107562672A
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Abstract
The invention discloses a kind of system and method for improving vector network analyzer message transmission rate, including：CPU module, DSP module and FPGA module；The DSP module is connected with FPGA module, and the CPU module realizes the high-speed data communication of full duplex by PCIE bus links with DSP module and FPGA module respectively；For CPU module according to the thread scheduling in user's request and CPU, the PCIE device for judging to need to access is DSP module or FPGA module, and the PCIE device then accessed by PCIE buses needs is quickly accessed.Beneficial effect of the present invention：The time-sharing multiplex of vector network analyzer internal bus, shared bandwidth structure are changed to point-to-point topological, the main frame of instrument is respectively provided with single communication link with each PCIE device, each PCIE device can unshared bandwidth, the bus bandwidth of vector network analyzer is effectively increased, while reduces the complexity of the arbitrated logic of instrument internal controller.
Description
Technical field
The present invention relates to a kind of system and method for improving vector network analyzer message transmission rate.
Background technology
Pci bus is a kind of 33MHz@32bit or 66MHz@64bit parallel bus, and bus bandwidth scope is
133MB/S to 533MB/S.All devices on host pci and pci bus share one group of general address, data and control line,
All devices share bus bandwidth, which dictates that synchronization can only have a hold facility bus and and main-machine communication, its
His equipment can only wait the release of bus during this period.
With the increasingly complication of vector network analyzer application solution, increasing application requirements vector network
Analyzer can carry out the measurement of high-speed, big bandwidth to measured piece.And existing vector network analyzer internal data transfer
Using pci bus, the parallel architecture of its low speed leads to not the fast reading and writing requirement for meeting that internal system carries out mass data,
Pci bus is also therefore as the bottleneck of system data transmission speed lifting.
Existing vector network analyzer is primarily present following shortcoming both at home and abroad at present：
1) pci bus that current desk-top vector network analyzer uses when connecting multiple equipment, it is necessary to using address
Line and the time-multiplexed design method of data wire, each equipment need to initiate to take the request of bus bandwidth and led to main frame
Bus could be taken after machine response, causes the effective bandwidth of bus to be greatly reduced, transmission rate is slack-off；And pci bus when
Clock is limited in the most slow peripheral hardware in multiple peripheral hardwares, and this seriously constrains the performance of the high-speed peripheral performance in bus, bus
Autgmentability is poor；
2) pci bus can only carry out unidirectional data transfer at each moment, and sending and receiving for data needs timesharing
Carry out, add the stand-by period, cause message transmission rate slow；
3) pci bus that vector network analyzer uses is parallel architecture, its parallel data wire and number of address lines compared with
More, so that the pin number of instrument internal communication interface is more, system hardware connection is more complicated, thus hardware manufacturing cost compared with
It is high.
The content of the invention
The purpose of the present invention is exactly to solve the above problems, it is proposed that one kind improves vector network analyzer data transfer
The system and method for speed, based on the point-to-point topological of PCI Express (hereinafter referred to as PCIE) bussing technique, make vector
Network Analyzer possesses higher message transmission rate and bigger bus bandwidth, will to what is quickly measured to adapt to user
Ask.
To achieve these goals, the present invention adopts the following technical scheme that：
The invention discloses a kind of system for improving vector network analyzer message transmission rate, including：CPU module, DSP
Module and FPGA module；The DSP module is connected with FPGA module, the CPU module by PCIE bus links respectively with DSP
Module and FPGA module realize the high-speed data communication of full duplex；
The FPGA module receives digital medium-frequency signal and carries out Digital Signal Processing, and result is sent into DSP
Module, the DSP module carry out floating-point operation to digital signal processing results；
According to the thread scheduling in user's request and CPU, the PCIE device for judging to need to access is the CPU module
DSP module or FPGA module, the PCIE device then accessed by PCIE buses needs are quickly accessed.
Further, the DSP module and FPGA module include：Outside memory cell, specially ram in slice and piece
DDR3 memory bars；The DDR3 memory bars be respectively intended to access DSP module and the respective data processed result of FPGA module and
Intermediate variable.
Further, Rapid IO buses and the GPIO of general programmable are passed through between the DSP module and FPGA module
Interface connects.
Further, when the CPU module accesses DSP module, the cpu command received is parsed by DSP module
Decode and perform corresponding operation, including：Read DSP module DDR3 internal memories data or send scan control to FPGA module
Instruction and/or task scheduling instruction.
Further, when the CPU module accesses FPGA module, the cpu command received is solved by FPGA module
Analysis decodes and performs corresponding operation, including：Read FPGA module DDR3 internal memories data or to other circuit function modules
Implement control.
It is including following the invention discloses a kind of method of work for improving vector network analyzer message transmission rate system
Step：
A1) system initialization；
A2) FPGA module receiving intermediate frequency signal and Digital Signal Processing is carried out, result and intermediate variable is deposited
Storage, and result is sent to DSP module；
A3) DSP module receives FPGA module result and carries out floating-point operation, and operation result and intermediate variable are carried out
Storage；
A4) CPU module learns user's request according to User Interface, is judged to need what is accessed according to thread scheduling
PCIE device, and it is conducted interviews by PCIE buses；
A5) instruction of the accessed PCIE device to CPU module carries out parsing decoding, and performs corresponding operation；
A6) PCIE device sends CPU module to by result is accessed by PCIE buses, and depth calculation is carried out by CPU module
And show experiment curv.
Further, the step A1 is specially：
A101) powered up to CPU module and FPGA module；
A102 after the completion of) FPGA module is powered up and initialized, the power-up and reset of DSP module are controlled by FPGA module.
Further, the step A2 is specially：
A201) FPGA module receives the digital medium-frequency signal from analog-digital converter；
A202 down coversion, the processing of FIR filtered digital signals) are carried out to digital medium-frequency signal；
A203) by the DDR3 memory bars inside Digital Signal Processing result and intermediate variable deposit FPGA module, and pass through
Rapid IO Bus repeaters are to DSP module.
Further, the step A4 is specially：
A401) CPU module learns user's request by the User Interface based on windows operating systems；
A402) PCIE device for judging to need to access according to CPU thread scheduling is DSP module or FPGA module；
A403) DSP module or FPGA module are conducted interviews by PCIE buses.
Further, the step A5 is specially：
A501) if CPU module accesses DSP module, parsing decoding is carried out to the cpu command received by DSP module
And corresponding operation is performed, including read DDR3 internal memories data or send scan control and task scheduling control to FPGA module
System order；
A502) if CPU module accesses FPGA module, parsing is carried out to the cpu command received by FPGA module and translated
Code simultaneously performs corresponding operation, including reads DDR3 internal memories data or other circuit function modules are implemented to control.
The invention discloses a kind of vector network analyzer, includes and improves vector network analyzer message transmission rate
System.
Beneficial effect of the present invention：
(1) time-sharing multiplex of vector network analyzer internal bus, shared bandwidth structure are changed to pointtopoint topology knot
Structure, the main frame of instrument and each PCIE device are respectively provided with single communication link, each PCIE device can unshared bandwidth,
The bus bandwidth of vector network analyzer is effectively increased, while reduces the complexity of the arbitrated logic of instrument internal controller
Degree.
(2) vector network analyzer main frame and the communication link of each PCIE device are full-duplex mode, data
Sending and receiving synchronously to be carried out, and greatly reduce stand-by period during mass data transfers, improve message transmission rate and
Efficiency.
(3) original low speed, parallel, time division multiplex bus are substituted using high speed, universal serial bus, reduces vector network point
The pin number of analyzer internal communications interface, the complexity of system hardware connection is simplified, manufacturing cost is reduced, greatly carries
The high robustness and cost performance of system.
Brief description of the drawings
Fig. 1 is the system structure diagram that the present invention improves vector network analyzer message transmission rate.
Embodiment
The present invention is further illustrated with embodiment below in conjunction with the accompanying drawings.
The invention discloses a kind of system for improving vector network analyzer message transmission rate, as shown in figure 1, including：
CPU module, DSP module and FPGA module.The CPU module of vector network analyzer is total by two independent PCIE
Wired link is connected with DSP module and FPGA module respectively.
PCIE buses of the present invention employ at present popular point-to-point topology in the industry, compared with pci bus and more early stage
The shared parallel architecture of computer bus, each equipment in PCIE buses are connected to root system system by single serial link
(main frame), it is not necessary to whole bus request bandwidth, data transmission rate can be brought up to a very high frequency, reach PCI
The high bandwidth that can not be provided.
Connected between DSP module and FPGA module by the GPIO interface of Rapid IO buses and general programmable.FPGA
It is connected by spi bus with other circuit modules.DSP module and FPGA module are provided with DDR3 memory bars.
CPU module is the main controller of vector network analyzer, and its function is to realize that thread scheduling, data operation, figure show
The function such as show；
The function of DSP module is that auxiliary vector Network Analyzer CPU module is scanned control and task scheduling, and right
FPGA filtering data carries out certain floating-point operation；
The function of FPGA module is to receive digital medium-frequency signal and carry out Digital Signal Processing to it, can also control vector
Other circuit function modules of Network Analyzer.
Realize that high-speed serial data interacts by Rapid IO buses between DSP module and FPGA module.DSP module passes through
Control FPGA module realizes scan control and task scheduling.The DDR3 memory bars of DSP module and FPGA module are used for accessing number
According to result and intermediate variable.CPU module is realized complete double with DSP module and FPGA module respectively by PCIE bus links
The high-speed data communication of work, and the data storage of DSP module and FPGA module can be accessed, including its ram in slice and piece
Outer DDR3 memory bars.
The operation principle of present system is as follows：
Digital medium-frequency signal is received by FPGA module first and carries out Digital Signal Processing, including Digital Down Convert, FIR filters
Ripple etc.；Filter result is sent to DSP module by FPGA by Rapid IO buses, and floating-point is carried out to filter result by DSP module
Computing.FPGA and DSP is respectively by the storage of respective operation result into corresponding DDR3 memory bars, so that CPU module accesses.
CPU module learns user's request by User Interface, is then judged to need the PCIE accessed according to the thread scheduling in CPU
Equipment is DSP module or FPGA module, then quickly accesses PCIE device by PCIE buses.When CPU module accesses DSP moulds
During block, the cpu command received is carried out parsing decoding by DSP module and performs corresponding operation, including reads DDR3 internal memories
Data sends the control command such as scan control and task scheduling to FPGA；When CPU module accesses FPGA module, by
FPGA module carries out parsing decoding and performs corresponding operation to the cpu command received, including reads DDR3 internal memory datas
Or other circuit function modules are implemented to control.
Technical scheme realizes the vector network analyzer of high-throughput by following steps：
A1) each nucleus module is powered up and initialized.
A101) powered up first to CPU module and FPGA module；
A102 after the completion of) FPGA module is powered up and initialized, the power-up and reset of DSP module are controlled by FPGA module.
A2) FPGA module receiving intermediate frequency signal and Digital Signal Processing is carried out, result and intermediate variable deposit DDR3
Result is simultaneously given to DSP module by memory bar by Rapid IO buses.
A201) FPGA module receives the digital medium-frequency signal from analog-digital converter；
A202 the Digital Signal Processing such as down coversion, FIR filtering) are carried out to digital medium-frequency signal；
A203 Digital Signal Processing result and intermediate variable) are stored in DDR3 memory bars, and turned by Rapid IO buses
Issue DSP module.
A3) DSP module receives FPGA module result and carries out floating-point operation, and operation result and intermediate variable are deposited
Enter its DDR3 internal memory.
A4) CPU module learns user's request according to User Interface, is judged to need what is accessed according to thread scheduling
PCIE device is simultaneously conducted interviews by PCIE buses to it.
A401) CPU module learns user's request by the User Interface based on windows operating systems；
A402) PCIE device for judging to need to access according to CPU thread scheduling is DSP module or FPGA module；
A403) DSP module or FPGA module are conducted interviews by PCIE buses.
A5) instruction of the accessed PCIE device to CPU module carries out parsing decoding, and performs corresponding operation.
A501) if CPU module accesses DSP module, parsing decoding is carried out to the cpu command received by DSP module
And corresponding operation is performed, including read DDR3 internal memories data or send scan control and task scheduling etc. to FPGA module
Control command；
A502) if CPU module accesses FPGA module, parsing is carried out to the cpu command received by FPGA module and translated
Code simultaneously performs corresponding operation, including reads DDR3 internal memories data or other circuit function modules are implemented to control.
A6) PCIE device sends CPU module to by result is accessed by PCIE buses, and depth calculation is carried out by CPU module
And show experiment curv.
The invention also discloses a kind of vector network analyzer, the vector network analyzer includes the raising arrow of the present invention
The system for measuring Network Analyzer message transmission rate, employ the method for work of the present invention.The pointtopoint topology that the present invention uses
Structure not only makes vector network analyzer have higher data throughout and bandwidth, simultaneously because interface pin quantity falls sharply
So as to reduce the connection complexity of instrument internal, the hardware cost of instrument is significantly reduced while improving systematic function.
Although above-mentioned the embodiment of the present invention is described with reference to accompanying drawing, model not is protected to the present invention
The limitation enclosed, one of ordinary skill in the art should be understood that on the basis of technical scheme those skilled in the art are not
Need to pay various modifications or deformation that creative work can make still within protection scope of the present invention.
Claims (10)
- A kind of 1. system for improving vector network analyzer message transmission rate, it is characterised in that including：CPU module, DSP moulds Block and FPGA module；The DSP module is connected with FPGA module, the CPU module by PCIE bus links respectively with DSP moulds Block and FPGA module realize the high-speed data communication of full duplex；The FPGA module receives digital medium-frequency signal and carries out Digital Signal Processing, and result is sent into DSP module, The DSP module carries out floating-point operation to digital signal processing results；For the CPU module according to the thread scheduling in user's request and CPU, the PCIE device for judging to need to access is DSP moulds Block or FPGA module, the PCIE device then accessed by PCIE buses needs are quickly accessed.
- A kind of 2. system for improving vector network analyzer message transmission rate as claimed in claim 1, it is characterised in that institute Stating DSP module and FPGA module includes：DDR3 memory bars outside memory cell, specially ram in slice and piece；The DDR3 Memory bar is respectively intended to access DSP module and the respective data processed result of FPGA module and intermediate variable.
- A kind of 3. system for improving vector network analyzer message transmission rate as claimed in claim 1, it is characterised in that institute State and connected between DSP module and FPGA module by the GPIO interface of RapidIO buses and general programmable.
- A kind of 4. system for improving vector network analyzer message transmission rate as claimed in claim 1, it is characterised in that institute When stating CPU module access DSP module, the cpu command received is carried out parsing decoding by DSP module and performs corresponding behaviour Make, including：Read DSP module DDR3 internal memories data or send scan control instruction and/or task scheduling to FPGA module Instruction.
- A kind of 5. system for improving vector network analyzer message transmission rate as claimed in claim 1, it is characterised in that institute When stating CPU module access FPGA module, the cpu command received is carried out parsing decoding by FPGA module and performs corresponding behaviour Make, including：Read FPGA module DDR3 internal memories data or other circuit function modules are implemented to control.
- 6. a kind of method of work as claimed in claim 1 for improving vector network analyzer message transmission rate system, it is special Sign is, comprises the following steps：A1) system initialization；A2) FPGA module receiving intermediate frequency signal and Digital Signal Processing is carried out, result and intermediate variable is stored, and Result is sent to DSP module；A3) DSP module receives FPGA module result and carries out floating-point operation, and operation result and intermediate variable are deposited Storage；A4) CPU module learns user's request according to User Interface, is judged to need the PCIE accessed to set according to thread scheduling It is standby, and it is conducted interviews by PCIE buses；A5) instruction of the accessed PCIE device to CPU module carries out parsing decoding, and performs corresponding operation；A6) PCIE device sends CPU module to by result is accessed by PCIE buses, is carried out depth calculation by CPU module and is shown Show experiment curv.
- 7. a kind of method of work for improving vector network analyzer message transmission rate system as claimed in claim 6, it is special Sign is that the step A2 is specially：A201) FPGA module receives the digital medium-frequency signal from analog-digital converter；A202 down coversion, the processing of FIR filtered digital signals) are carried out to digital medium-frequency signal；A203) by the DDR3 memory bars inside Digital Signal Processing result and intermediate variable deposit FPGA module, and pass through RapidIO Bus repeaters are to DSP module.
- 8. a kind of method of work for improving vector network analyzer message transmission rate system as claimed in claim 6, it is special Sign is that the step A4 is specially：A401) CPU module learns user's request by the User Interface based on windows operating systems；A402) PCIE device for judging to need to access according to CPU thread scheduling is DSP module or FPGA module；A403) DSP module or FPGA module are conducted interviews by PCIE buses.
- 9. a kind of method of work for improving vector network analyzer message transmission rate system as claimed in claim 6, it is special Sign is that the step A5 is specially：A501) if CPU module accesses DSP module, the cpu command received is carried out parsing decoding and held by DSP module The corresponding operation of row, including read DDR3 internal memories data or send scan control and task scheduling control life to FPGA module Order；A502) if CPU module accesses FPGA module, parsing decoding is carried out to the cpu command received simultaneously by FPGA module Corresponding operation is performed, including reads DDR3 internal memories data or other circuit function modules is implemented to control.
- A kind of 10. vector network analyzer, it is characterised in that including：Using any raising vector described in claim 1-5 The system of Network Analyzer message transmission rate.
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| CN110971486A (en) * | 2019-11-21 | 2020-04-07 | 中电科仪器仪表有限公司 | Switch matrix control device and method for integrated multiport network instrument |
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| CN109710565A (en) * | 2018-12-03 | 2019-05-03 | 天津津航计算技术研究所 | The logic united when VPX cabinet B code realizes system and method |
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| CN110971486B (en) * | 2019-11-21 | 2021-08-17 | 中电科仪器仪表有限公司 | Switch matrix control device and method for integrated multiport network instrument |
| CN111766425A (en) * | 2020-06-18 | 2020-10-13 | 深圳市极致汇仪科技有限公司 | Vector network analyzer supporting multi-port parallel test |
| CN114489506A (en) * | 2022-01-21 | 2022-05-13 | 杭州海康存储科技有限公司 | Storage access control device and method and storage equipment |
| CN114489506B (en) * | 2022-01-21 | 2024-02-27 | 杭州海康存储科技有限公司 | Storage access control device, method and storage device |
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