CN108650136A

CN108650136A - A kind of design method of master/slave station card that realizing the communication of Powerlink industry real-time ethernets

Info

Publication number: CN108650136A
Application number: CN201810473167.8A
Authority: CN
Inventors: 文长明; 文可; 项曦文; 储成君; 尹若嵬
Original assignee: Middle Industry Science Peace Science And Technology Ltd
Current assignee: Middle Industry Science Peace Science And Technology Ltd
Priority date: 2018-05-17
Filing date: 2018-05-17
Publication date: 2018-10-12
Anticipated expiration: 2038-05-17
Also published as: CN108650136B

Abstract

The invention discloses a kind of design methods of master/slave station card that realizing the communication of Powerlink industry real-time ethernets.The principal and subordinate/card of standing can be configured to Powerlink industry real-time ethernets communication main website card or slave station card.When master/slave station is stuck in design, CPU, Powerlink industry real-time ethernet communicate IP kernel, CPU in piece and IP kernel are reached to the software interface of communication in FPGA internal build pieces.CPU includes Powerlink stack user layers in piece, and IP kernel includes the inner nuclear layer and MAC layer of Powerlink protocol stacks.For master/slave station card in use, golden finger is inserted into upper mainboard CAL female seats, host computer runs Powerlink protocol stack application programs, and FPGA runs client layer, inner nuclear layer and MAC layer.Using the present invention, the minimal circulation period reaches 1ms, sync response time 480us under this kind of non-real time operating systems of Windows；In the case of no operating system, the minimal circulation period is up to 200us, shake 1us or so.

Description

A kind of design of master/slave station card that realizing the communication of Powerlink industry real-time ethernets Method

Technical field

The present invention relates to a kind of design method of industrial real-time ethernet communication apparatus of industrial field bus technical field, Specially a kind of master/slave station card design method for realizing the communication of Powerlink industry real-time ethernets.

Background technology

It is often used CPU+FPGA combinations in open Powerlink resource packets and realizes Powerlink main websites or slave station.open It is disclosed in Powerlink resource packets and a kind of utilizing open MAC (Hub) and open Powerlink Application The method that Powerlink main websites or slave station are realized in stack designs.

Fig. 1 is existing open Powerlink illustratons of model, open Powerlink protocol stacks=client layer+session level of abstraction + inner nuclear layer+MAC layer.Other than MAC layer programs realization by hardware description language and runs on FPGA, remaining each layer is equal It (can be here, different as the CPU of host computer to program realization by computer advanced language and run on host computer CPU Chip, can also be the different core cpus in same chips).

Client layer is responsible for control, and inner nuclear layer is responsible for communication, and the interface between two layers is referred to as session level of abstraction CAL (communication Abstraction Layer).The CAL of Fig. 1 is parallel communication.

Client layer include event processing module, object dictionary, network state machine, time synchronization module, error handling module, Process data object PDO and Service Data Object SDO.

Inner nuclear layer includes event processing module, network state machine, time synchronization module, error handling module, process data Object PDO, data link DLL (Data Link Layer) state machine, Periodic signal drive, high precision clock hardware and Ethernet drive Dynamic, wherein PDO is responsible for synchronous event processing, and SDO is responsible for asynchronous event processing.

It is indexed in the object dictionary of client layer foundation CANopen agreements in this layer, and client layer end PDO is mapped one by one To inner nuclear layer end PDO, as communication requirements, the event processing module between two layers, time synchronization module, error handle mould Block etc. is all corresponded by CAL layers.DLL state machines positioned at inner nuclear layer are responsible for as communication core according to current network state Determine oneself state to handle the transmitting-receiving of Powerlink data frames and the encoding and decoding of data frame content, wherein Powerlink data Frame is forwarded to open MAC parsings by Powerlink network interfaces through open Hub, just inputs inner nuclear layer network-driven to trigger DLL shapes State machine redirects.Periodic signal drive defines system absolute time for DLL state machines and time synchronization mould according to high precision clock hardware Block refers to.Time synchronization module generates interruption, for determining Powerlink communication cycles, wherein dividing synchronous phase, asynchronous stages And idle phase.Protocol stack ensures that Powerlink total communication cycle times are fixed by adjusting above three phases-time, with Achieve the purpose that real-time control.

Open Powerlink resource packets are a kind of associations for realizing the communication of Powerlink industry real-time ethernets of entry level Stack is discussed, the communication of Powerlink industry real-time ethernets is realized if designed using open Powerlink resource packets and is produced Product design, and are that cannot achieve to refer to technology as defined in " Ethernet Powerlink communication professional etiquettes specification " (GB/T27960-2016) Target.It has the disadvantage that：Signal transmission shake is big, and transmission rate is slow, and cycle period is long, while needing to use multiple cores Piece, design is complicated, thus causes Powerlink industry real-time ethernets communication low-response, transmits unstable, communication cost The problems such as high.

Invention content

In view of the deficiencies of the prior art, realizing what Powerlink industry real-time ethernets communicated the present invention provides a kind of The design method of master/slave station card, the card can configure or be manufactured directly to as main website, can also configure or be manufactured directly to for from It stands, directly manufactures manufacture and the configuration status when meaning manufacture.

The card has PCIe communication interfaces interface (PCIe golden fingers), when card PCIe golden fingers are inserted into host computer (PC machine Or other industrial control equipments) behind PCIe communication interfaces interface on mainboard (PCIe female seats), when being configured to main website, the card+upper The combination of machine just constitutes the Powerlink industry real-time ethernet main station controllers of a double network interfaces, can be opened up by network It flutters, accesses others Powerlink industry real-time ethernet slave station equipments；When being configured to slave station, the combination of the card+host computer The Powerlink industry real-time ethernet slave station equipments for just constituting a double network interfaces, can be by network topology, with others Powerlink industry real-time ethernet slave station equipments access Powerlink communication networks jointly.

The present invention is realized using following technical scheme：It is a kind of to realize the master/slave of Powerlink industry real-time ethernets communication It stands the design method of card, the master/slave station card includes that CPU in piece, software interface, Powerlink industry real-time ethernets communicate IP kernel；Described interior CPU design Powerlink stack user layer, the client layer include controller one, object dictionary, in Disconnected generator one, process data object module, Service Data Object module；The IP kernel includes inner nuclear layer and MAC layer, it is described in Stratum nucleare includes interrupting generator two, synchrodata cache module, asynchronous data cache module, controller two；

Wherein, when the master/slave station card is designed as main website card, meet following characteristics：

The generator one that interrupts generates interruption according to the triggering for interrupting generator two, and interruption sequential is consequently formed, The time of two neighboring interruption is a Powerlink period in the interruption sequential, and the Powerlink periods include synchronizing Processing time, asynchronous process time and free time；

The controller one receives the control information collection in a Powerlink period, the control information collection control and institute The connected at least one slave station of main website is stated, the control information collection includes corresponding at least one at least one slave station Control information；The controller one after receiving the interrupt, is believed the control first within the synchronization process time The data of synchronization process are needed to be sent to the process data object module in breath, it will be described within the asynchronous process time The data of asynchronous process are needed to be sent to the Service Data Object module in control information, and interior do not do is located during idle time Reason；

The object dictionary assists the process data object module to establish and the synchrodata according to CANopen agreements Synchrodata channel between cache module assists the Service Data Object module to establish and the asynchronous data cache module Between asynchronoud data channel；

The process data object module will need synchronization process by software interface according to the synchrodata channel Data are sent to the synchrodata cache module, and the Service Data Object module is by the software interface according to described different Step data channel will need the data of asynchronous process to be sent to the asynchronous data cache module；

The controller two completes following data framing according to Powerlink agreements：Elder generation is within the synchronization time need It wants the data of synchronization process to form Powerlink data frames one, and the Powerlink data frames one is sent to the MAC Layer, after in the asynchronous time needing the data of asynchronous process to form Powerlink data frames two, and will be described Powerlink data frames two are sent to the MAC layer；

The interruption generator two is after the controller two completes the data framing, and at current Powerlink weeks The interruption generator one is triggered at the end of phase.

The present invention also provides the design sides of another master/slave station card for realizing the communication of Powerlink industry real-time ethernets Method, difference lies in when the master/slave station card is designed as slave station card, meet following characteristics：

After the MAC layer first receives the Powerlink synchrodata trigger frames Soc from main website, the middle stopping pregnancy is triggered Raw device two generates down trigger information；The generator one that interrupts is generated according to the interrupt trigger signal for interrupting generator two It interrupts, the interruption represents a Powerlink period and starts；The controller one is logical according to the down trigger synchrodata Road, the synchrodata channel are：Auxiliary of the process data object module in the object dictionary according to CANopen agreements Under, the channel between the synchrodata cache module of foundation；

The MAC layer receives the Powerlink synchrodatas from main website again, and the controller two is to the synchrodata It is decoded the Powerlink data frames that extraction needs synchronous transfer according to Powerlink agreements；The synchrodata caches mould Block is sent to by the Powerlink data frames for needing synchronous transfer, by software interface according to the synchrodata channel The process data object module, is transferred for the controller one；

The Powerlink asynchronous data trigger frame Soa from main website, the controller two are received after the MAC layer Asynchronoud data channel is triggered according to the Powerlink asynchronous datas trigger frame Soa, the asynchronoud data channel is：The service For data object module under auxiliary of the object dictionary according to CANopen agreements, foundation caches mould with the asynchronous data Channel between block；

The MAC layer receives the Powerlink asynchronous datas from main website again, and the controller two is to the asynchronous data It is decoded the Powerlink data frames that extraction needs asynchronous transmission according to Powerlink agreements；The asynchronous data caches mould Block sends out the Powerlink data frames for needing asynchronous transmission by the software interface according to the asynchronoud data channel It send to the Service Data Object module, is transferred for the controller one.

Compared with prior art, master/slave station card design method of the invention, has following advantageous effect.

1. the master/slave station card design method of the present invention, the FPGA in main website card is responsible for running entire Powerlink protocol stacks Main website, i.e. Powerlink client layers and inner nuclear layer, in FPGA Embeddeds CPU, (CPU can be stone, can also be at this time The soft core such as Microblaze), piece is also required to configure storage resource (DDR3) for CPU outside.Inner nuclear layer logical code is logical with client layer The connection of AXI_EPC interfaces is crossed, MAC layer and Powerlink network interfaces are then connected, completes building for Powerlink protocol stacks.PCIe Slot is for connecting PC machine, and in motion control application, user issues motion control commands by PCIe interface by PC machine and arrives AXI_PCIe, information is decoded and is sent to bus here eventually arrives at client layer caching.Controlling information can be by entire The main website put up is transmitted to other Powerlink slave station equipments.

2. the master/slave station card design method of the present invention, by the way that single-chip FPGA is arranged and rationally utilizes host computer CPU, letter Change communication device, to reduce the expense of communication, saves cost.

3. the master/slave station card design method of the present invention, different by using the mode and use of handshake plus L2 cache The mode for walking FIFO caching TLP data packets, eliminates metastable state, reduces delay, ensure that the synchronism of data.

Description of the drawings

Fig. 1 is existing open Powerlink illustratons of model；

Fig. 2 is the illustraton of model of the master/slave station cards of Powerlink of the present invention；

Fig. 3 is the structural schematic diagram of the master/slave station cards of the Powerlink of the present invention；

Fig. 4 is the inner function module block diagram of the master/slave station cards of the Powerlink of the present invention and host computer；

Fig. 5 is to block deformed structural schematic diagram by the master/slave stations Powerlink of the present invention；

Fig. 6 is the illustraton of model of the master/slave station cards of Powerlink in Fig. 5；

Fig. 7 is the inner function module block diagram of the master/slave station cards of Powerlink and host computer in Fig. 5；

Fig. 8 is the Powerlink main websites HDL module frame charts of the present invention；

Fig. 9 is that data move towards flow chart inside FPGA during the PCIe of the present invention reads and writes；

Figure 10 is state transition figure of the handshake of the present invention in receiving engine；

Figure 11 is state transition figure of the handshake of the present invention in sending engine；

Figure 12 is the state transition diagram of the asynchronous FIFO Read-write Catrol of the present invention；

Figure 13 is the three axis servo drive system networking schematic diagrams realized using the master/slave station cards of Powerlink of the present invention；

Figure 14 is the system circulation period schematic diagram that communication is completed using the master/slave station cards of Powerlink of the present invention；

Figure 15 is that the interrupt signal that the master/slave station cards of Powerlink of this application invention complete communication shakes oscillogram.

Specific implementation mode

In order to make the purpose , technical scheme and advantage of the present invention be clearer, with reference to the accompanying drawings and embodiments, right The present invention is further elaborated.It should be appreciated that described herein, specific examples are only used to explain the present invention, not For limiting the present invention.

Embodiment 1

Referring to Fig. 2, the master/slave station card illustratons of model of Powerlink of the present invention, compare with Fig. 1, the present invention is in design and in fact When the master/slave station card of existing Powerlink industry real-time ethernets communication, Powerlink industry real-time ethernet Communication Models by Client layer+Powerlink industry real-time ethernets communicate IP kernel (hereinafter referred to as IP kernel) and form, wherein IP kernel=inner nuclear layer+MAC Layer, and pass through the communication of the soft interface such as realization of AXI_EPC interfaces client layer and IP kernel.

The event registers module of IP kernel is defined according to network state machine state and data link DLL state machine states It institute's generation event and is deposited in Powerlink communications, to determine whether above-mentioned state machine state redirects, and guides data transmit-receive And coding/decoding module work.

The data transmit-receive and coding/decoding module of IP kernel are responsible for the Powerlink data frames that reception Mac is forwarded and are solved Then code whither forwards important communication data according to network state and state of data link decision.Receiving user's layer data Afterwards, data transmit-receive and parsing module can determine data being inserted into corresponding types according to network state and state of data link Powerlink data frames are forwarded with completing framing coding to MAC.

It is indexed in the object dictionary of client layer foundation CANopen agreements in this layer, and client layer end PDO is connect by soft Mouth is mapped to synchrodata caching/asynchronous data caching of IP kernel inner nuclear layer one by one.

Such as Fig. 2, the master/slave station card user layer that Powerlink industry real-time ethernets of the invention communicate operates in upper On machine CPU, is generally programmed and realized by high-level [computer；The IP kernel of the present invention operates on FPGA, by close to machine language Hardware description language programming realize and emulation.

The master/slave station card design method for realizing the communication of Powerlink industry real-time ethernets of the present embodiment, please refers to figure 3 and Fig. 4 needs to design Powerlink stack user layers, designs master/slave station card, and the master/slave station card is designed as main website card When, the client layer and the master/slave station card meet individual features, when the master/slave station card is designed as slave station card, the user Layer and the master/slave station card will also meet individual features.

The master/slave station card includes CPU in piece, software interface, Powerlink industry real-time ethernets communication IP kernel；Institute CPU design Powerlink stack user layers in piece are stated, the client layer includes controller one, object dictionary, interrupts generator One, process data object module, Service Data Object module；The IP kernel includes inner nuclear layer and MAC layer, and the inner nuclear layer includes Interrupt generator two, synchrodata cache module, asynchronous data cache module, controller two.

Wherein, when the master/slave station card is designed as main website card, described interior CPU, the software interface, the IP kernel are equal It operates on FPGA, the master/slave station card meets following characteristics.

The process data object module will need the number of synchronization process by soft interface according to the synchrodata channel According to the synchrodata cache module is sent to, the Service Data Object module is by the soft interface according to the asynchronous number The data of asynchronous process will be needed to be sent to the asynchronous data cache module according to channel；

Wherein, within the synchronization time, the controller two is received according to Powerlink agreement handles from the MAC layer Data frame decoding go out synchronous response information, and be sent to the synchrodata cache module for the controller one read；Institute It states in asynchronous time, the data frame decoding received from the MAC layer is gone out asynchronous answer by the controller two according to Powerlink agreements Information is answered, and is sent to the asynchronous data cache module and is read for the controller one.

The client layer may also include network state machine, and the inner nuclear layer further includes state of data link machine, event deposit Device.The network state machine is used to manage the communication state of Powerlink industry real-time ethernets, and main website searches at least one Slave station and corresponding slave station feedback response message when be network active state, the communication state in network active state, Powerlink industry real-time ethernets are activated.The state of data link machine is used to define the different data of the inner nuclear layer Processing state makes the controller two handle corresponding data in different data processing states.The event registers are used In the different conditions according to the network state machine and the state of data link machine, records corresponding event and store.

Management equipment equipped with the client layer and the main website card equipped with the IP kernel constitute the core component of main website, described Main website communication when the means of communication be：The control information of application program can pass sequentially through client layer, soft in the management equipment Interface, inner nuclear layer, MAC layer, Powerlink network interfaces are output to the industrial control equipment being connect with slave station, realize to the industry control The control of equipment.Poll phase is communicated in Powerlink, the slave station feedback response message gives the main website.The main website card It is connect by PCIe interface with the management equipment, and is connect by Powerlink network interfaces with the slave station.

When the master/slave station card is designed as slave station card, described interior CPU, the software interface, the IP kernel are also run On FPGA, the master/slave station card meets following characteristics.

After the MAC layer first receives the Powerlink synchrodata trigger frames Soa from main website, the middle stopping pregnancy is triggered Raw device two generates interrupt trigger signal；The generator one that interrupts is generated according to the interrupt trigger signal for interrupting generator two It interrupts, the interruption represents a Powerlink period and starts；The controller one is logical according to the down trigger synchrodata Road, the synchrodata channel are：Auxiliary of the process data object module in the object dictionary according to CANopen agreements Under, the channel between the synchrodata cache module of foundation.

The MAC layer receives the Powerlink synchrodatas from main website again, and the controller two is to the synchrodata It is decoded the Powerlink data frames that extraction needs synchronous transfer according to Powerlink agreements；The synchrodata caches mould Block is sent to institute by the Powerlink data frames for needing synchronous transfer, by soft interface according to the synchrodata channel Process data object module is stated, is transferred for the controller one.

The Powerlink asynchronous data trigger frame Soa from main website, the controller two are received after the MAC layer Asynchronoud data channel is triggered according to the Powerlink asynchronous datas trigger frame Soa, the asynchronoud data channel is：The service For data object module under auxiliary of the object dictionary according to CANopen agreements, foundation caches mould with the asynchronous data Channel between block.

The MAC layer receives the Powerlink asynchronous datas from main website again, and the controller two is to the asynchronous data It is decoded the Powerlink data frames that extraction needs asynchronous transmission according to Powerlink agreements；The asynchronous data caches mould Block is sent by the Powerlink data frames for needing asynchronous transmission, by the soft interface according to the asynchronoud data channel To the Service Data Object module, transferred for the controller one.

Within the synchronization time, the controller one receive synchronous transfer Powerlink data frames after according to Powerlink agreements send out synchronous response information, and are sent to the synchrodata cache module and are read for the controller two, The controller two is provided to the synchronous response information coding with Powerlink agreements at synchronous response frame, by the MAC layer It sends；In the asynchronous time, after the controller one receives the Powerlink data frames of asynchronous transmission, according to Powerlink agreements send out asynchronous response message, and are sent to the asynchronous data cache module and are read for the controller two, The controller two is encoded into asynchronous acknowledgement frame with Powerlink agreements regulation to the asynchronous response message, by the MAC layer It sends.

Industrial control equipment equipped with the client layer and the slave station card equipped with the IP kernel constitute the core component of slave station, described Slave station communication when the means of communication be：The Powerlink networks that the control information that main website transmits can pass sequentially through slave station card connect Mouth, MAC layer, inner nuclear layer, soft interface, client layer make industrial control equipment finally execute required movement according to the control information received. Poll phase is communicated in Powerlink, the industrial control equipment feeds back response message to management equipment.The slave station card and the master It stands and is connected by Powerlink network interfaces.

Embodiment 2

For the master/slave station card design method for realizing the communication of Powerlink industry real-time ethernets of embodiment 1, work( Energy structure and design method are as follows.

Step 1：The main control chip of the card is made of FPGA, and other primary electron components have：Power management chip, Network transceivers physical layer PHY, FLASH chip, DDR3 memories, clock chip etc..

Such as, the fpga chip for supporting PCIe HSSI High-Speed Serial Interfaces is chosen, using hardware description language inside the FPGA Build the inner nuclear layer and MAC layer of CPU, Powerlink protocol stack (master/slave station) in piece.

The inner nuclear layer at the master/slave stations Powerlink is key problem in technology using the realization of HDL hardware description languages.Main website inner nuclear layer Predominantly main website core, wherein including data transmission and reception buffer module, interrupting generation module, timer module, main website DLL state machine modules, main website NMT state machine modules, MAC module, PHY chip management module and other register modules.From Inner nuclear layer of standing is mainly slave station core, and inside modules include data transmission and reception buffer module, interrupt generation module, timing It device module, slave station DLL state machine modules, slave station NMT state machine modules, MAC module, PHY chip management module and other posts Buffer module.Its core is DLL state machine modules and NMT state machine modules.The responsible connection of Mac layers at the master/slave stations Powerlink The FPGA and the responsible physical chip with 100,000,000 Powerlink network interfaces.

Step 2：Fpga chip, which has, supports PCIe HSSI High-Speed Serial Interfaces.Using hardware description language inside the FPGA structure Build the inner nuclear layer and MAC layer of CPU, Powerlink protocol stack in piece (master/slave station).

Step 3：It is continuing with hardware description language structure soft interface driving in FPGA described in step 1, makes CPU in piece It is correctly connect by soft interface with Powerlink protocol stacks inner nuclear layer described in step 2.

When the mono- DW of PCIe (Double Word) reads and writes, an effective DW number is read and write in the TLP data packets of every 4 DW According to.When the more DW of PCIe based on above-mentioned basis read and write, handshake may be used and add the mode of L2 cache metastable to eliminate State, can also using asynchronous FIFO cache TLP data packets by the way of by delay lock TLP packets and wrap between.Both the above side Read-write wait state need to be all separately provided as data buffer storage state in formula in reading and writing data.It hereinafter, will be to handshake State transition setting in state transition and asynchronous FIFO when use is introduced, this is the focused protection of the present invention One of technology.

The rd_en_i signals of internal storage access module are added to reading to enable, by the rd_addr_i signals of internal storage access module Upgrade to 16 with wr_add_i signals；The rd_be_i signals of internal storage access module use total data, internal storage access module Wr_be_i signals use low four figures evidence.

Step 4：Writing the master/slave station card insertions of the Powerlink and enter management equipment --- the CAL of host computer drives：PCIe interface The user application of driving and Powerlink protocol stacks (master/slave station).

In the combination of card+host computer, the host computer that computer advanced language (such as C language) can be used to write and realize PCIe interface drives.Host computer corresponding virtual address in being driven by access equipment, to access corresponding physical address, with this Achieve the purpose that access the interface.

In card+host computer combination, computer advanced language (such as C language) can be used to write and realize Powerlink The client layer and user application of protocol stack (master/slave station).

Step 5 (a)：Further, it after the combination of the card+host computer connects and is configured to main website, is applied on host computer CPU The control information of program can pass sequentially through the ends host computer CPU PCIe interface, card FPGA ends PCIe interface, application layer, soft interface, interior Stratum nucleare, MAC layer, the ends card FPGA Powerlink network interfaces are output to other Powerlink slave station equipments, realize to described The control of Powerlink slave stations.

Step 5 (b)：Further, after the combination of the card+host computer connects and is configured to slave station, prepare with it is described from The control information of application program can pass sequentially through the Powerlink slave stations in other Powerlink master devices of communication of standing Equipment --- the ends card FPGA Powerlink network interfaces, block on FPGA at the Powerlink protocol stacks MAC layer on card FPGA Powerlink protocol stacks inner nuclear layer, the ends card FPGA soft interface, the Powerlink stack users layer on card FPGA, the ends card FPGA PCIe interface, the ends host computer CPU PCIe interface, the user application such as APP on host computer CPU, the slave station equipment are final Required movement is executed according to the control information received.In addition, communicating poll phase in Powerlink, slave station equipment also can be anti- Response message is presented to master device.

No matter the card is configured to main website or slave station, and the rd_en_i signals of internal storage access module, which are added to reading, to be enabled, will The rd_addr_i signals and wr_add_i signals of internal storage access module upgrade to 16；The rd_be_i of internal storage access module believes Number total data, the wr_be_i signals of internal storage access module is used to use low four figures evidence.

When being configured to main website, frame sequence is generated by mode as defined in protocol stack in a communication cycle, and monitor from It stands reaction；Slave station monitors the sequence of the frame received in a cycle, and is fed back by mode as defined in protocol stack.

In the combination of card+host computer, PCIe interface driving and the Powerlink protocol stacks for running on host computer are (master/slave Stand) client layer and user application write and realize using computer advanced language (such as C language)；Run on card FPGA On Powerlink protocol stacks inner nuclear layer and MAC layer be all made of HDL hardware description languages and write and realize.

In the more DW read-writes of PCIe, use handshake plus the mode of L2 cache to eliminate metastable state.And using asynchronous The mode of FIFO caching TLP data packets is by delay lock between TLP packets and packet.

No matter the card is configured to main website or slave station, is arranged MSI_GEN modules in card FPGA, MSI_GEN modules be used for PCIe provides interruption；When receiving POWERLINK interruptions, MSI_GEN modules are supplied to the interruption that the period is 1ms is counted PCIe is connected each TLP by the caching of asynchronous FIFO so that interrupt signal does not generate interference.

Embodiment 3

One, program analysis

(1), two schemes framework

The master/slave station card structures of Powerlink in the first scheme in FPGA by logical code as shown in figure 5, completed The inner nuclear layer and MAC layer of Powerlink protocol stacks, then be connected with the CPU of host computer by PCIe interface, where run Powerlink stack user layers.It is the PCIe slots that PC machine network interface card is connected to by PCIe golden fingers specific to main website card, then Two Powerlink Ethernet interfaces of the board can be used to be equipped with setting for type Powerlink slave station cards with other for PC machine It is standby to realize communication, and application control is realized to Powerlink slave station equipments using the host computer in PC machine.

The master/slave station cards (such as Fig. 3) of Powerlink of second scheme are that the extension on the first scheme basis is set Meter, it is also more increasingly complex on Software for Design.It does not change compared to external structure in Fig. 5, only the CPU in FPGA pieces On be integrated with Ethernet Powerlink application level functions, this has shared the partial task of host computer, shorten system circulation It period, can be helpful in terms of promoting traffic rate.

Powerlink main websites card can replace the network interface card of PC machine, PCIe slots mutually replaceable.It is only to use at this time Powerlink industry real-time ethernets communicate, rather than common ethernet communication.And Powerlink slave stations card can be installed to Networking is helped in the equipment such as servo-driver.The board PCB design of two above version is essentially identical, and difference exists In protocol stack implementation method and software architecture.

(2), hardware selection refers to

Method described in the invention is to realize that the Powerlink industry real-time ethernets with PCIe interface are logical based on FPGA Master/slave station card is interrogated, therefore, the FPGA of current any mainstream vendor's production can be selected in master chip, such as the ECP3 systems of Lattice companies It arranges, Cyclone IV GX series, the Spartan 6T series even ZYNQ series etc. of Xilinx companies of altera corp.

The first scheme runs Powerlink inner nuclear layer C codes using FPGA, and client layer hardware is run using the CPU of PC Description language code.According to the above demand, by taking Xilinx companies chip as an example, Xilinx Spartan can be selected in FPGA 6xc6slx25t chips, and without using chip external memory.

Second scheme will run entire protocol stack code, including C and hardware description language using FPGA.FPGA pieces at this time The operation of interior CPU needs to match memory, it is therefore desirable to more resource guarantees.According to the above demand, it is with Xilinx companies chip Example, FPGA can be adjusted to Xilinx Spartan 6xc6slx45t chips, and it is that 2GB is big that memory space, which can be selected, in chip external memory Small DDR3SDRAM memories, and paid the utmost attention to corresponding to fpga chip model recommended by the manufacturer.

Two, it implements

(1), traffic model

Powerlink industry real-time ethernet based on being developed on common commercial Basic Ethernet, and Powerlink traffic models are also to be developed according to the osi model of standard, and only it only has three layers：Application layer, data Chain link layer and physical layer.

Powerlink inner nuclear layers (Powerlink Kernel Layer) are realized used here as HDL hardware description languages, are made Realize that its client layer (Power User Layer), physical layer are configured using the corresponding of common Ethernet with C language, without Do special change.The specific implementation principle of two versioning schemes will be illustrated from the angle of traffic model below.

Powerlink based on FPGA blocks V1 versions in master/slave station, as shown in FIG. 6 and 7.In the master/slave station card of this version FPGA is only responsible for operation Powerlink protocol stacks inner nuclear layer and PCIe drivings, is not necessarily to chip external memory.By taking main website card as an example, such as Shown in Fig. 7, the PC machine of dotted portion description is as host computer, for running motion control App and Powerlink stack user Layer identification code；Powerlink client layers and Powerlink inner nuclear layers are communicated by PCIe interface；Bold portion description FPGA is responsible for running Powerlink inner nuclear layers and MAC layer Verilog code；Motion control information passes through PCIe data by PC machine Frame is transferred to FPGA, is decoded by PCIe_EP_Ctrl modules, then is transmitted to inner nuclear layer by PCIe_to_EPL interfaces, then is packaged into Powerlink data frames are transferred to other Powerlink controlled nodes (slave station) by Powerlink network interfaces, be finally completed to from The real-time control stood using (such as servo-driver).

Powerlink based on FPGA blocks V2 versions in master/slave station, as shown in Figures 2 and 4.In the main website card of this version FPGA is responsible for running entire Powerlink protocol stacks main website, i.e. Powerlink client layers and inner nuclear layer, at this time in FPGA pieces Integrated CPU (CPU can be stone, can also be the soft core such as Microblaze), piece are also required to configure storage resource for CPU outside (DDR3).As shown in figure 4, by taking the main website card of the soft core versions of the Microblaze in Xilinx FPGA as an example, soft nucleus CPU in piece Microblaze is responsible for running Powerlink user's layer identification code, and by AXI bus marco whole systems, as DDR3 controllers, PCIe controller etc..Inner nuclear layer logical code is connect with client layer by AXI_EPC interfaces, then connect MAC layer and Powerlink network interfaces complete building for Powerlink protocol stacks.PCIe slots are for connecting PC machine, in motion control application In, user issues motion control commands to AXI_PCIe by PC machine by PCIe interface, and information is decoded and passed here It send to bus and eventually arrives at client layer caching.Control information can be transmitted by the main website entirely put up to other Powerlink slave station equipments.

(2), CAL interfaces

Data interaction between Powerlink stack users layer and inner nuclear layer is needed through specific CAL interfaces come real It is existing.The master/slave station card of first version described in the present embodiment uses the PCIe_to_EPL interfaces based on PCIe buses, the The master/slave station card of two versions uses soft interface, i.e. the AXI_EPC interfaces based on AXI buses.

1, PCIe_to_EPL interfaces

The network card interface of PC machine is usually PCI or PCIe interface, and it is this kind of that the present embodiment adds PCIe on the basis of protocol stack HSSI High-Speed Serial Interface can facilitate this equipment to be docked with PC machine, to substitute PC machine network interface card.PCIe_to_EPL interface masters herein It is responsible for connecting the Powerlink inner nuclear layers write of Verilog HDL codes and PCIe_EP_Ctrl this PCIe controller.

(1) Powerlink protocol stacks HDL module interfaces

1) main website

Be illustrated in figure 8 the part the Powerlink HDL i.e. master station module block diagram of inner nuclear layer, inside include that data are sent out Send and receive buffer module, interrupt generation module, timer module, main website DLL state machine modules, main website NMT state machine modules, MAC module, PHY chip management module and other register modules.Its core is DLL state machine modules and NMT state machine moulds Block.The signal for needing to be connected to external network interface is removed, other signals for requiring connect to PCIe are as shown in the table.

1 New_Powerlink_MN_IP_Interface of table

Signal name	Bit wide (Bit)	Input/output (FPGA)	Function
				iHostRead	1	Input	Powerlink reads enabled
iHostWrite	1	Input	Powerlink writes enabled
				iHostByteenable	4	Input	Byte is enabled
iHostAddress	16	Input	Powerlink address signals
				oHostData	32	Output	Output data
iHostData	32	Input	Input data
				oHostWaitRequest	1	Output	Reading and writing response

Powerlink main websites generate frame sequence by mode as defined in protocol stack in one cycle, and monitor the anti-of slave station It answers.

2) slave station

Powerlink slave station inner nuclear layer inside modules include data transmission and reception buffer module, interrupt generation module, Timer module, slave station DLL state machine modules, slave station NMT state machine modules, MAC module, PHY chip management module and its Its register module.Its core is DLL state machine modules and NMT state machine modules.Powerlink slave stations monitor in a cycle The sequence of the frame of reception, and react by mode as defined in protocol stack.

(2), PCIe internal storage access

It is trend of the data inside FPGA during PCIe reads and writes as shown in Figure 9：The lower left corner is that PCIe drives IP kernel, right Side PCIe App include the sequential and memory access module for sending and receiving engine, they all interact number by AXI buses According to finally passing out FPGA by serial differential signals line again.

PCIe communicates optional 32/64 position datawire, and Powerlink communicates optional 8/16/32 position datawire, therefore in order to just In unification, the two selects 32 position datawires.

Internal storage access module is the data interaction core of PCIe App, and data judge by receiving engine parsing to memory Read-write, then make corresponding actions.It runs through and just data and handshake is provided, give and send and receive engine；It writes just Handshake is sent to and sends and receivees engine.

It writes data and reads data by here, reaching selected RAM storages, then from specified RAM.If can be herein Read-write is chronologically correctly connect with the signal in table 2, you can completes the read-write of PCIe to Powerlink.

2 PIO_EP_MEM_ACCESS_Interface of table

Signal name	Bit wide (Bit)	Input/output (memory)	Function
				rd_addr_i	11	Input	Read address
rd_be_i	4	Input	It is enabled to read byte
				rd_data_o	32	Output	Read data
wr_addr_i	11	Input	Write address
				wr_be_i	8	Input	The section that writes is enabled
wr_data_i	32	Input	Write data
				wr_en_i	1	Input	It writes enabled
wr_busy_o	1	Output	Write busy signal

Lack reading enable signal herein, indicates to read to enable continuously effective, but we need a controllable reading enabled.Cause This, rd_en_i is added to read enabled.

The address signal bit wide of script not enough matches Powerlink addressing bit wides, needs to increase.By PCIe protocol it is found that The 2 to 31st of second DW of TLP packets can regard significant address signal, therefore rd_addr_i and wr_add_i are upgraded to 16, the 2 to 15th of the m_axis_rx_tdata directly transmitted by AXI buses when receiving provides, then adds status two 0. When sending due to only sending low 6 effective addresses, it is not required to change.Specifically how read/write address is selected, it is enabled by reading and writing It determines.Rd_be_i uses total data, wr_be_i that low four figures evidence, the enabled selection of byte is used also to be enabled certainly by reading and writing It is fixed.

(3), the more DW read-writes of PCIe and cross clock domain synchronize

When single DW (Double Word) read-write, an effective DW data are read and write in the TLP data packets of every 4 DW.In this way The benefit done is often to have read and write an effective DW, is put into wait state, has been communication when read-write next time arrives State has arrived next TLP packets, therefore need not do clock synchronization.But doing so can so that data access efficiency is low, And minimum 36 bytes of Powerlink data frames, maximum is more than 1K.Current this read-write mode is clearly to be unsatisfactory for great Rong Data transmission is measured, therefore more DW read-writes can just be met the requirements.

More DW read-writes are to repeat the operation with effect DW after judging to write DW length.But data can be brought at this time Synchronous problem, the user clock of PCIe be 62.5M, and data access is all to refer to this clock, and Powerlink protocol stacks Clock is 50M.If wanting to synchronize the two, fast clock has to wait for slow clock.Following two methods technically can be used, when By the way of handshake plus L2 cache, metastable state is eliminated；Second is that caching TLP data using DC_FIFO (asynchronous FIFO) The mode of packet is by delay lock between TLP packets and packet.Below will the DW of PCIe read and write basis on from two above in terms of More DW read-write theories are described.

1) handshake

Under the premise of each two at interface both ends docking signal all uses and eliminates metastable state way, also it is in the present embodiment Memory read-write has prepared two pairs of handshake altogether：Wr_busy_o, Wr_compl_o are exported to reception engine (such as Figure 10)；Rd_ Busy_o, Rd_compl_o are exported to transmission engine (such as Figure 11).Signal description is as shown in the table：

3 handshake list of table

Handshake name	Bit wide	Explanation
			Wr_busy_o	1	Busy signal is write, expression is write process and carried out
Wr_compl_o	1	Write complete signal
			Rd_busy_o	1	Busy signal is read, indicates that read procedure is carrying out
Rd_compl_o	1	Run through signal

It is as shown in Figure 10 state transition figure of the handshake in receiving engine, state transition condition is illustrated It is as follows.

S_1:PIO_32_RX_RST_STATE, original state indicate to receive reset state.Reception can be detected under this state The TLP Packet types arrived if type described in S_2, and detect that Req_len_o signal values are 1, then jump to S_4 states；If The TLP packets received are type described in S_3, and detect that Req_len_o signal values are 1, then also jump to S_4 states；If Conditions above is unsatisfactory for, then is continually maintained in S_1 states.

S_2:One of PIO_32_RX_MEM_WR32_FMT_TYPE, TLP type of data packet indicates 32 memory write shapes State.If the condition Req_len_o of redirecting is unsatisfactory for, the waiting of S_1 states can be jumped back to automatically.

S_3:One of PIO_32_RX_IO_WR32_FMT_TYPE, TLP type of data packet indicates 32 and writes I/O state.If When the condition Req_len_o of redirecting is unsatisfactory for, the waiting of S_1 states can be jumped back to automatically.

S_4:PIO_32_RX_IO_MEM_WR32_DW1 receives first DW of TLP packets.If detecting m_ under this state Axis_rx_tvalid signals and m_axis_rx_tready signals are effective simultaneously, then jump to S_5 states；If conditions above is not Meet, is then continually maintained in S_4 states.

S_5:PIO_32_RX_IO_MEM_WR32_DW2 receives second DW of TLP packets.If detecting m_ under this state Axis_rx_tvalid signals and m_axis_rx_tready signals are effective simultaneously, then jump to S_6 states；If conditions above is not Meet, is then continually maintained in S_5 states.

S_6:PIO_32_RX_IO_MEM_WR32_DW3 receives TLP packet thirds DW.If detecting Wr_ under this state Busy_i signals are effective, and it is invalid to write complete signal Wr_comple_i, then jumps to S_8 states；If detecting Wr_busy_ I invalidating signals then jump to S_7 states；If conditions above is unsatisfactory for, it is continually maintained in S_6 states.

S_7:PIO_32_RX_WR32_WRITE, write state.If detecting under this state, Wr_comple_i signals are effective, And m_axis_rx_ready signals are effective, then jump back to S_6 states；If detecting, Wr_comple_i signals are effective, and M_axis_rx_ready invalidating signals then jump to S_9 states；Detect Wr_comple_i invalidating signals, then after continuation of insurance more It holds in S_7 states；If conditions above is unsatisfactory for, S_8 states are jumped to.

S_8:PIO_32_RX_WR32_WAIT writes wait state.If detecting under this state, Wr_busy_i signals continue Effectively, then S_8 states are continually maintained in；Otherwise, S_7 states are jumped to.

S_9:PIO_32_RX_WAIT_STATE indicates to receive wait state, waits for the DW for being loaded with valid data.This state If lower detect that tlp_type is wr, and when wr_busy_i invalidating signals, then jumps back to S_1 states；If detecting tlp_ Type is rd, and when compl_done_i signals are effective, then jumps back to S_1 states；When conditions above is unsatisfactory for, then continue It is maintained at S_9 states.

As shown in Figure 10, it is state transition figure of the handshake in sending engine, specifically to state transition condition It is bright as follows.

S_10:PIO_32_TX_RST_STATE, original state indicate to send reset state.If detecting under this state Req_compl_q signals are effective, and when req_compl_with_data_q invalidating signals, show that the TLP packets to be sent are S_ 11 types, then state transition to S_13；If detecting, Req_compl_q signals are effective, and req_compl_with_ When data_q signals are effective, show that the TLP packets to be sent are type described in S_12, then state transition to S_13；If the above item Part is unsatisfactory for, then is continually maintained in S_10 states.

S_11:One of PIO_32_CPL_FMT_TYPE, TLP type of data packet is selected by S_10 states.

S_12:One of PIO_32_CPLD_FMT_TYPE, TLP type of data packet is selected by S_10 states.

S_13:PIO_32_TX_CPL_CPLD_DW1 sends first DW.If detecting S_axis_tx_ under this state Tready signals are effective, then jump to S_14 states.If being unsatisfactory for conditions above, it is continually maintained in S_13 states.

S_14:PIO_32_TX_CPL_CPLD_DW2 sends second DW.If detecting S_axis_tx_ under this state Tready signals remain valid, and cpl_w_data invalidating signals, then jump to S_17 states；If detecting S_axis_tx_ Tready signals remain valid, and cpl_w_data signals are also effective, while rd_busy_i signals are also effective, then jump to S_16 states；If detecting, S_axis_tx_tready signals remain valid, and cpl_w_data signals are also effective, still Rd_busy_i invalidating signals then jump to S_15 states；If conditions above is unsatisfactory for, it is continually maintained in S_14 states.

S_15:PIO_32_TX_DATA_READ, read states.Signal Rd_comple_i is run through if detecting under this state Effectively, then S_17 states are jumped to；Otherwise, S_15 states are continually maintained in.

S_16:PIO_32_TX_DATA_WAIT reads wait state.If detecting under this state, Rd_busy_i signals have Effect, then jump to S_15 states；Otherwise, S_16 states are continually maintained in.

S_17:PIO_32_TX_CPLD_DW3 sends third DW.If detecting S_axis_tx_tready under this state Signal is effective, and count value of the value of Re_len_i equal to 1 or length_cnt is equal to req_len_i, then jumps to S_ 18 states；If detecting, S_axis_tx_tready signals are effective, and the value of Re_len_i is not equal to 1 or length_cnt Count value be not equal to req_len_i, and when rd_busy_i invalidating signals, then jump back to S_15 states；If detecting S_ Axis_tx_tready signals are effective, and count value of the value of Re_len_i not equal to 1 or length_cnt is not equal to Req_len_i, and when rd_busy_i signals are effective, then jump back to S_16 states；If conditions above is unsatisfactory for, continue It is maintained at S_17 states.

S_18:PIO_32_TX_WAIT_STATE indicates to send wait state.If detecting S_axis_tx_ under this state Tready signals remain valid, then jump back to S_10 states；Otherwise, S_18 states are continually maintained in.

2) asynchronous FIFO

FIFO (First In First Out) is wide in fpga logic because of the characteristics of possessing data " first in first out " It is general to be used as data cache module.In addition to carrying out the first synchronous method, can also use second will delay from each two DW it Between change to the method between each two TLP packets.Module for caching TLP packets is doubleclocking FIFO, is also asynchronous FIFO.

Such processing mode is also the MSI interrupt that can be more convenient to add PCIe, while to ensure that data synchronize accurately Property is prepared.Add two asynchronous FIFOs in the present embodiment, be each responsible for read-write Powerlink data, reversely from the point of view of i.e. write-read PCIe data.FIFO bit wides are set as 32, depth 1KB..At this time memory read-write access carried out directly in FIFO, receive and Engine is sent without wait state is arranged again.It is asynchronous FIFO Read-write Catrol state transition diagram as shown in figure 12.

S_19:STATE_RST, original state indicate read-write reset state.If detecting read command rd_cmd under this state Effectively, then S_22 states are jumped to；If detecting, write order is effective, and it is not empty to read FIFO, i.e. Rd_fifo_empty_i signals When invalid, then S_20 states are jumped to；Conditions above is all unsatisfactory for, then is continually maintained in the waiting of S_19 states.

S_20:RD_FIFO_WR_PLK reads FIFO and writes Powerlink states.If detecting DW counter numbers under this state When value DwCnt is equal with the value of req_len_i, and detect iHostAck effectively or DwCnt value be 1 when, then jump to S_21 states；Conditions above is all unsatisfactory for, then is continually maintained in S_20 states.

S_21:RD_FIFO_WR_PLK_END, reading FIFO write Powerlink and terminate state.It is write if detecting under this state Command signal is invalid, and detects that oHostWrite signals are effective or iHostAck signals are effective, then jumps back to S_19 shapes State；Conditions above is all unsatisfactory for, then is continually maintained in S_21 states.

S_22:WR_FIFO_RD_PLK writes FIFO and reads Powerlink states.If detecting DW counter numbers under this state When value DwCnt is equal with the value of req_len_i, and when iHostAck signals and oHostRead signals effective simultaneously, then redirect To S_23 states；Conditions above is all unsatisfactory for, then is continually maintained in S_22 states.

S_23:WR_FIFO_RD_PLK_END writes FIFO readings Powerlink and terminates state.If detecting reading under this state Command signal rd_cmd is invalid, then jumps back to S_19 states；Otherwise S_23 states are continually maintained in.

2, AXI_EPC interfaces

(1), parameter setting

Interface in second scheme between Powerlink stack users layer and inner nuclear layer is AXI_EPC.Such as 4 institute of table It is shown as the interface internal parameter setting details.

List is arranged in 4 AXI_EPC interface parameters of table

(2) connection setting

As shown in table 5, AXI_EPC interface signals connect details with Powerlink kernel layer signals.

5 AXI_EPC interface signals of table connect details with Powerlink kernels

EPC signal names	Function describes	Connect kernel layer signal	Remarks
				PRH_Addr	Address signal	oHostAddress	PRH_Addr moves to right two, then is accessed after high two zero paddings
PRH_BE	Byte is enabled	oHostByteenable
				PRH_Rd_n	It reads enabled	oHostRead
PRH_Wr_n	It writes enabled	oHostWrite
				PRH_Rdy	Ready signal	Net_VCC	It draws high
PRH_Data_I	Data input	iHostReaddata	32
				PRH_Data_O	Data export	oHostWritedata	32
PRH_CS_n	Chip selection signal	/	It does not use

(3), interrupt mechanism

1, MSI interrupt

MSI interrupt is the exclusive interrupt modes of PCIe in fact, because in the first main website card scheme, Powerlink associations View stack inner nuclear layer and client layer need to communicate, and the mode of period control is exactly using interruption.It can be in the present embodiment for PCIe On the basis of individually add MSI_GEN modules, it is internal only following signal correctly to be configured.

6 MSI_GEN module by signal of table

Signal name	Bit wide (Bit)	Input/output (MSI_GEN)	Remarks
				user_clk	1	input	62.5MHz
user_reset	1	input
				oIrq	1	input	Powerlink is interrupted
cfg_interrupt	1	output
				cfg_interrupt_rdy	1	input
cfg_interrupt_assert	1	output
				cfg_interrupt_di	8	output
cfg_interrupt_do	8	input
				cfg_interrupt_mmenable	3	input
cfg_interrupt_msienable	1	input	MSI interrupt is enabled
				cfg_command	16	input

Powerlink is received herein to interrupt, and has then been prepared the interruption that the counting period is 1ms in MSI_GEN and has been supplied to PCIe is well connected each TLP so that interrupt signal is not interfered it by the caching of asynchronous FIFO.

2, XIntc interrupt control units

When using second scheme, PCIe is not involved in Powerlink protocol stack internal interrupt processing procedures.Agreement at this time Stack interruption need to transfer to independent interrupt control unit to complete.By taking the Microblaze core systems of Xilinx as an example, which can only Response is individually interrupted, it is therefore desirable to add additional interrupt control unit to handle multiple interruptions, which is named as XIntc。

After the hardware of the interrupt control unit is configured, CPU need to be enabled with C language in software aspects and is interrupted.

(4), platform drives

Powerlink stack users layer passes through target.c access interface equipment：If there are operating system, directly visit Ask driving of the corresponding equipment under the operating system；If without operating system, the equipment is directly accessed.Stack user layer C Code can be able to be the stones such as STM32, X86 or ARM, be built in even FPGA in the CPU operations of many different frameworks Soft core, if the Microblaze of Xilinx is the soft nucleus CPU of ARM frameworks.It is flat X86-based CPU can be run with upper mounting plate Platform and ARM framework CPU platforms.

1, X86-based CPU platforms carry the PC machine platform of Windows systems and Intel's x86 processors, need to finish writing Corresponding PCIe drivings under windows, you can access the master/slave station card apparatus of PCIe by accessing driving.Host computer passes through visit It asks corresponding virtual address in device drives, to access corresponding physical address, achievees the purpose that do the interface earliest with this.

2, ARM frameworks CPU platforms, herein only by taking the Microblaze soft-core processor platforms of xilinx companies as an example, it It is the processor based on ARM frameworks.Operating system is not run in this version.But essence is also to access memory on accessing principle, It only accesses object and becomes equipment itself.

Three, using debugging

(1), the demo of dynamic triaxial servo is driven

Can use host computer or digital control mainboard as communication main website in practical applications, connection PLC or servo-drive etc. from Station equipment carries out production practices.The three axis servo drive system groups to be realized using the master/slave station cards of Powerlink as shown in figure 13 Net matters figure also identifies the original using the communication of Preq/Pres poll answer-modes between Powerlink master-salve stations in figure Reason.Main website MN is by Preq data frames to each slave station poll, and slave station is responded with respective Pres data frames, and expression will participate in this Cycle synchronisation communicates.

(2), cycle period and shake

It is as shown in figure 14 system cycle period, free time is largely shortened, and the minimal circulation period reaches 200us, and Shake at this time is very small, and signal is opposite to tend towards stability.

It is signal jitter waveform as shown in figure 15, shake at this time has had been lowered to 1us or so.

Lead in conclusion two kinds of design schemes embody two kinds of Powerlink industry real-time ethernets with PCIe interface The innovation realization thinking of protocol stack is interrogated, while developing the corresponding CAL interfaces PCIe_to_EPL and AXI_EPC of two schemes The interaction of stack user layer and inner nuclear layer is completed well.Main website card all superior performances that two methods are realized, single-chip Solution is relatively more convenient, but cost also accordingly increases, and hardware board design can be general, and user can be according to reality Demand chooses corresponding method.

Embodiment 4

Realize what the master/slave station card design method of Powerlink industry real-time ethernets communication was realized with embodiment 1 Powerlink it is master/slave station have the advantages that stable, quick and at low cost in communication, solve Powerlink industry in real time with Too low-response is interrogated by Netcom, transmits unstable, the high problem of communication cost.

The master/slave station card for realizing the communication of Powerlink industry real-time ethernets of embodiment 4, uses FPGA to realize, CPU, software interface, Powerlink industry real-time ethernets communicate IP kernel in design piece in FPGA.It is designed on CPU in piece Powerlink stack user layers, the client layer include controller one, object dictionary, interrupt generator one, process data pair As module, Service Data Object module.The IP kernel includes inner nuclear layer and MAC layer, the inner nuclear layer include interrupt generator two, Synchrodata cache module, asynchronous data cache module, controller two.

Wherein, when the master/slave station card is designed as main website card, the master/slave station card meets following characteristics：

Wherein, when the master/slave station card is designed as slave station card, the slave station card connects industrial control equipment, the master/slave station card Meet following characteristics：

After the MAC layer first receives the Powerlink synchrodata trigger frames Soc from main website, the middle stopping pregnancy is triggered Raw device two generates interrupt trigger signal；The generator one that interrupts is generated according to the interrupt trigger signal for interrupting generator two It interrupts, the interruption represents a Powerlink period and starts；The controller one is logical according to the down trigger synchrodata Road, the synchrodata channel are：Auxiliary of the process data object module in the object dictionary according to CANopen agreements Under, the channel between the synchrodata cache module of foundation；

The MAC layer receives the Powerlink synchrodatas from main website again, and the controller two is to the synchrodata It is decoded the Powerlink data frames that extraction needs synchronous transfer according to Powerlink agreements；The synchrodata caches mould Block is sent to institute by the Powerlink data frames for needing synchronous transfer, by soft interface according to the synchrodata channel Process data object module is stated, is transferred for the controller one；

The master/slave station card for realizing the communication of Powerlink industry real-time ethernets of the present embodiment, can carry out alternative Design：It is designed to the main website card of Powerlink industry real-time ethernets communication, or is designed to the real-time ether of Powerlink industry The slave station card of Netcom's news；When the master/slave station card is designed as main website card, connect master device, the master/slave station block be designed as from Stand card when, connect slave station equipment, the main website card passes through Powerlink network interfaces and connects the slave station card.

The foregoing is merely illustrative of the preferred embodiments of the present invention, is not intended to limit the invention, all essences in the present invention All any modification, equivalent and improvement etc., should all be included in the protection scope of the present invention made by within refreshing and principle.

Claims

1. a kind of design method of master/slave station card that realizing the communication of Powerlink industry real-time ethernets, which is characterized in that institute It includes CPU in piece, software interface, Powerlink industry real-time ethernets communication IP kernel to state master/slave station card；Described interior CPU is set Powerlink stack user layers are counted, the client layer includes controller one, object dictionary, interrupts generator one, process data Object module, Service Data Object module；The IP kernel includes inner nuclear layer and MAC layer, and the inner nuclear layer includes interrupting generator Two, synchrodata cache module, asynchronous data cache module, controller two；

The generator one that interrupts generates interruption according to the triggering for interrupting generator two, and interruption sequential is consequently formed, described The time for interrupting two neighboring interruption in sequential is a Powerlink period, and the Powerlink periods include synchronization process Time, asynchronous process time and free time；

The controller one receives the control information collection in a Powerlink period, the control information collection control and the master It stands connected at least one slave station, the control information collection includes at least one control corresponding at least one slave station Information；The controller one after receiving the interrupt, will be in the control information first within the synchronization process time Need the data of synchronization process to be sent to the process data object module, by the control within the asynchronous process time Need the data of asynchronous process to be sent to the Service Data Object module in information, and during idle time in be not processed；

The object dictionary assists the process data object module to establish and synchrodata caching according to CANopen agreements Synchrodata channel between module assists the Service Data Object module to establish between the asynchronous data cache module Asynchronoud data channel；

The process data object module will need the data of synchronization process by software interface according to the synchrodata channel It is sent to the synchrodata cache module, the Service Data Object module is by the software interface according to the asynchronous number The data of asynchronous process will be needed to be sent to the asynchronous data cache module according to channel；

The controller two completes following data framing according to Powerlink agreements：It is first same needing within the synchronization time The data composition Powerlink data frames one of step processing, and the Powerlink data frames one are sent to the MAC layer, after Needing the data of asynchronous process to form Powerlink data frames two in the asynchronous time, and by the Powerlink numbers It is sent to the MAC layer according to frame two；

The interruption generator two is tied after the controller two completes the data framing, and in the current Powerlink periods The interruption generator one is triggered when beam.

2. the design method of the master/slave station card of Powerlink industry real-time ethernets communication is realized as described in claim 1, It is characterized in that, within the synchronization time, the controller two is according to Powerlink agreements being received from the MAC layer Data frame decoding goes out synchronous response information, and is sent to the synchrodata cache module and is read for the controller one；Described In asynchronous time, the data frame decoding received from the MAC layer is gone out asynchronous response by the controller two according to Powerlink agreements Information, and be sent to the asynchronous data cache module and read for the controller one.

3. the design method of the master/slave station card of Powerlink industry real-time ethernets communication is realized as described in claim 1, It is characterized in that, the client layer further includes network state machine, the inner nuclear layer further includes state of data link machine, event deposit Device；

The network state machine is used to manage the communication state of Powerlink industry real-time ethernets, and main website searches at least one A slave station and corresponding slave station feedback response message when be network active state, the communication state in network active state, Powerlink industry real-time ethernets are activated；

The state of data link machine is used to define the different data processing state of the inner nuclear layer, makes the controller two not With data processing state when handle corresponding data；

The event registers are used for the different conditions according to the network state machine and the state of data link machine, record phase It answers event and stores.

4. the design method of the master/slave station card of Powerlink industry real-time ethernets communication is realized as described in claim 1, It is characterized in that, described interior CPU, the software interface, the IP kernel operate on FPGA.

5. the design method of the master/slave station card of Powerlink industry real-time ethernets communication is realized as described in claim 1, It is characterized in that, the main website card constitutes the core component of main website, the means of communication of the main website in communication with management equipment For：In the management equipment control information of application program can pass sequentially through PCIe interface, client layer, software interface, inner nuclear layer, MAC layer, Powerlink network interfaces are output to the industrial control equipment being connect with slave station, realize the control to the industrial control equipment；Institute It states main website card to connect by PCIe interface with the management equipment, and is connect by Powerlink network interfaces with the slave station.

6. the design method of the master/slave station card of Powerlink industry real-time ethernets communication is realized as claimed in claim 5, It is characterized in that, communicating poll phase in Powerlink, the slave station feedback response message gives the main website.

7. a kind of design method of master/slave station card that realizing the communication of Powerlink industry real-time ethernets, which is characterized in that institute It includes CPU in piece, software interface, Powerlink industry real-time ethernets communication IP kernel to state master/slave station card；Described interior CPU is set Powerlink stack user layers are counted, the client layer includes controller one, object dictionary, interrupts generator one, process data Object module, Service Data Object module；The IP kernel includes inner nuclear layer and MAC layer, and the inner nuclear layer includes interrupting generator Two, synchrodata cache module, asynchronous data cache module, controller two；

Wherein, when the master/slave station card is designed as slave station card, meet following characteristics：

After the MAC layer first receives the Powerlink synchrodata trigger frames Soc from main website, the interruption generator is triggered Two generate down trigger information；The generator one that interrupts is according in the interrupt trigger signal generation for interrupting generator two Disconnected, the interruption represents a Powerlink period and starts；The controller one is logical according to the down trigger synchrodata Road, the synchrodata channel are：Auxiliary of the process data object module in the object dictionary according to CANopen agreements Under, the channel between the synchrodata cache module of foundation；

The MAC layer receives the Powerlink synchrodatas from main website again, the controller two to the synchrodata according to Powerlink agreements are decoded the Powerlink data frames that extraction needs synchronous transfer；The synchrodata cache module will The Powerlink data frames for needing synchronous transfer are sent to by software interface according to the synchrodata channel described Process data object module is transferred for the controller one；

The Powerlink asynchronous data trigger frame Soa from main website are received after the MAC layer, the controller two is according to institute Powerlink asynchronous data trigger frames Soa triggering asynchronoud data channels are stated, the asynchronoud data channel is：The service data Object module the object dictionary according to CANopen agreements auxiliary under, foundation with the asynchronous data cache module it Between channel；

The MAC layer receives the Powerlink asynchronous datas from main website again, the controller two to the asynchronous data according to Powerlink agreements are decoded the Powerlink data frames that extraction needs asynchronous transmission；The asynchronous data cache module will The Powerlink data frames for needing asynchronous transmission, are sent to by the software interface according to the asynchronoud data channel The Service Data Object module, is transferred for the controller one.

8. the design method of the master/slave station card of Powerlink industry real-time ethernets communication is realized as claimed in claim 7, It is characterized in that, within the synchronization time, the controller one receive after the Powerlink data frames of synchronous transfer according to Powerlink agreements send out synchronous response information, and are sent to the synchrodata cache module and are read for the controller two, The controller two is provided to the synchronous response information coding with Powerlink agreements at synchronous response frame, by the MAC layer It sends；In the asynchronous time, after the controller one receives the Powerlink data frames of asynchronous transmission, according to Powerlink agreements send out asynchronous response message, and are sent to the asynchronous data cache module and are read for the controller two, The controller two is encoded into asynchronous acknowledgement frame with Powerlink agreements regulation to the asynchronous response message, by the MAC layer It sends.

9. the design method of the master/slave station card of Powerlink industry real-time ethernets communication is realized as claimed in claim 7, It is characterized in that, the slave station card constitutes the core component of slave station, communication of the slave station in communication with the industrial control equipment Method is：The control information that main website transmits can pass sequentially through Powerlink network interfaces, MAC layer, inner nuclear layer, software interface, use Family layer, makes industrial control equipment finally execute required movement according to the control information received；The slave station card passes through with the main website Powerlink network interfaces connect.

10. the design method of the master/slave station card of Powerlink industry real-time ethernets communication is realized as claimed in claim 9, It is characterized in that, communicating poll phase in Powerlink, the industrial control equipment feeds back response message to management equipment.