CN203178411U - Collection system for partial discharge array signals - Google Patents

Abstract

The utility model discloses a collection system for partial discharge array signals. The collection system for the partial discharge array signals includes a mainboard provided with at least two bus slots, a synchronous sampling control signal producing circuit and a system power source, wherein the bus slots are connected with each other through a custom bus and the synchronous sampling control signal producing circuit provides synchronous sampling control signals; an AD sampling board inserted in one of the bus slots and used for converting input analog signals to digital signals and storing the digital signals; and a DSP signal processing board inserted in the other of the bus slots and used for reading and analyzing storage data of the AD sampling board for obtaining original sampling data.

Description

A kind of acquisition system of shelf depreciation array signal

Technical field

The utility model relates to signal acquiring system, relates in particular to a kind of local discharge signal acquisition system.

Background technology

Partial Discharge Detection is the important means of power equipment insulation diagnosis, because it can reflect the insulation status of electric system electrical equipment timely and effectively, in the extensive widespread usage of power domain quilt.At present, basically all be the research of carrying out partial discharge monitoring and monitoring technology at the concrete power equipment of transformer station both at home and abroad, main detection principle and the method for using comprises pulse current method, superfrequency (UHF, Ultra High Frequency) method, supercritical ultrasonics technology, chemical method, optical method etc., wherein superfrequency method and supercritical ultrasonics technology are practical feasible methods.

Usually, the partial discharge monitoring for substation equipment mainly is to carry out at concrete single equipment such as GIS, transformer, capacitive apparatus.Adopt these methods that the local discharge signal of power equipment is detected, need at first local discharge signal to be gathered

The utility model content

The purpose of this utility model provides a kind of local discharge signal acquisition system, and this system can sample to local discharge signal accurately and efficiently, thereby provides the basis for the analysis of local discharge signal.

According to above-mentioned utility model purpose, the utility model proposes a kind of local discharge signal acquisition system, it comprises:

One mainboard which is provided with at least two bus slots, synchronous sampling control signal generation circuit and a system power supply, and described bus slot is connected to each other by self-defined bus, and described synchronized sampling control signal produces circuit the synchronized sampling control signal is provided;

One is plugged in the AD(analog to digital conversion on the described bus slot) sampling plate, its analog signal conversion with input is digital signal and storage;

One is plugged in the DSP(DigitalSignalProcessor on the described bus slot, digital signal processor) signal-processing board, it reads the storage data of described AD sampling plate and analyzes and obtains original sampling data.

When a plurality of local signals are carried out synchronized sampling, use the zero crossing waveform of power frequency component as the synchronized sampling control signal.

The said system power supply can comprise :+5VAI ,-5VAI ,+3V3A ,+3V3D.Wherein, + 5VAI ,-5VAI is the insulating power supply of the local discharge signal modulate circuit in the AD sampling plate, because for simulating signal, can adopt the linear voltage stabilization chip to realize, to guarantee minimum voltage ripple, preceding step voltage is by transformer step-down and the inversion of arrangement bridge.+ 3V3A ,+3V3D uses to AD sampling plate and DSP signal-processing board, because the total current of every plank is little, chip and system radiating can meet the demands, therefore consider from the angle that reduces system noise as far as possible, can use the linear voltage stabilization chip, preceding step voltage also is by transformer step-down and the inversion of arrangement bridge.

Further, in the acquisition system of above-mentioned shelf depreciation array signal, described AD sampling plate comprises:

Portion of at least one road bureau discharge signal modulate circuit that is located thereon;

At least one AD module that is located thereon, described AD module and the corresponding connection of described local discharge signal modulate circuit;

A CPLD(Complex Programmable Logic Device who links to each other with described self-defined bus with described AD module who is located thereon, CPLD);

A memory module that is connected with described AD module with described CPLD that is located thereon.

The control core of above-mentioned AD sampling plate is CPLD, by it produce the AD module various control signals, memory module write sequential, to the pre-service of sampled signal, self-defined bus interface sequence etc.The differential analog signal of input transfers single-ended signal to via amplifier, then carries out filtering via low-pass filter, follows filtered signal and send into the AD module after signal transformer is isolated, AD module this moment commencing signal sampling work under the control of CPLD.Simultaneously, the data bus of the data bus of AD module and CPLD, memory module connects together, the sampling output data that CPLD can flexible processing AD modular converter like this.Both data can have been read in and carry out some filtering processing among the CPLD, and again data deposited in the local cache, or directly provide the write control signal of storer, sampled data had been write local cache.Adopt CPLD replaced C PU, can well improve the behavior in service of system.The AD module requires that the Gao Yaoneng of sample frequency reaches that 50MHz is above, binary channels, sampling resolution 14bit.

Further, described memory module comprises SRAM(Static RAM, static memory).The memory array that comprises SRAM is served as jumbo local storage, and sampled data is carried out buffer memory, waits for that the equipment of rear end is taken sampled data away.

Further, in the acquisition system of above-mentioned shelf depreciation array signal, described local discharge signal modulate circuit comprises: an operational amplifier and a low-pass filter that is connected with described operational amplifier, described operational amplifier transfers differential signal to single-ended signal, and described low-pass filter carries out filtering with described single-ended signal and handles and export to described AD module.

Further, in the acquisition system of above-mentioned shelf depreciation array signal, described local discharge signal modulate circuit also comprises: a transformer, and it is connected with described low-pass filter, and the single-ended signal that described transformer transmits low-pass filter transfers differential signal to and exports to described AD module again.

Further, in the acquisition system of above-mentioned shelf depreciation array signal, described local discharge signal modulate circuit has two-way, and described AD module has two.

Further, in the acquisition system of above-mentioned shelf depreciation array signal, described AD sampling plate also comprises a MCU(Micro Control Unit who links to each other with CPLD who is located thereon, and micro-control unit claims single-chip microcomputer again).

Further, in the acquisition system of above-mentioned shelf depreciation array signal, described DSP signal-processing board comprises:

A DSP(Digital Signal Processor who links to each other with described self-defined bus who is located thereon, digital signal processor);

A synchronous dynamic RAM that links to each other with described DSP that is located thereon (SDRAM, Synchronous Dynamic Random Access Memory);

A flash memory (FLASH) that links to each other with described DSP that is located thereon;

A network interface that links to each other with described DSP that is located thereon.

The data cached of AD sampling plate read and is stored among the SDRAM by DSP by self-defined bus; FLASH is used for the storage program; Data among the SDRAM are carried out denoising in DSP, sample analysis generates original sampling data, are sent in the host computer by network interface.

Further, in the acquisition system of above-mentioned shelf depreciation array signal, described DSP signal-processing board also comprises: a usb host interface module that links to each other with described DSP that is located thereon.

Further, in the acquisition system of above-mentioned shelf depreciation array signal, described DSP signal-processing board also comprises: the data with described DSP links to each other with described usb host interface module that are located thereon are selected module, this module also provides and the direct-connected interface of main frame, selects data channel on demand.

Further, in the acquisition system of above-mentioned shelf depreciation array signal, described DSP signal-processing board also comprises: a monitoring module that links to each other with described DSP that is located thereon.This monitoring module can be house dog, is used for the monitoring module supervisory control system running.

The acquisition system of shelf depreciation array signal described in the utility model, on the basis of satisfying the requirement of GIS local discharge signal acquisition system front end, take into account cost, performance and versatility, not only can be used for GIS local discharge signal acquisition system, also may be used on the system that other have similar local discharge signal sample requirement.

Description of drawings

Fig. 1 is the structural representation of AD sampling plate under a kind of embodiment of the acquisition system of shelf depreciation array signal described in the utility model.

Fig. 2 is the wiring diagram of AD9248 chip among a kind of embodiment of the utility model.

Fig. 3 is the wiring diagram of IS61LV51216 chip among a kind of embodiment of the utility model.

Fig. 4 is the structural representation of DSP signal-processing board under a kind of embodiment of local discharge signal acquisition system described in the utility model.

Fig. 5 is TMS320C6713B and MT48LC16M16A2 interface synoptic diagram among a kind of embodiment of the utility model.

Fig. 6 is the wiring diagram of the asynchronous memory controller of TMS320C6713B and AM29LV160D chip among a kind of embodiment of the utility model.

Fig. 7 is the wiring diagram of TMS320C6713B and SRAM among a kind of embodiment of the utility model.

Fig. 8 be among a kind of embodiment of the utility model network interface chip under Direct BusI/F with the line graph of TMS320C6713B.

Fig. 9 is HPI interface and the main frame wiring diagram of TMS320C6713B among a kind of embodiment of the utility model.

Figure 10 is the wiring diagram of EZ-USB FX2 and TMS320C6713B among a kind of embodiment of the utility model.

Figure 11 is synchronous signal circuit figure among a kind of embodiment of the utility model.

Figure 12 is among a kind of embodiment of the utility model+5VAI ,-the 5VAI power circuit diagram.

Figure 13 is among a kind of embodiment of the utility model+3VAI ,-the 3VAI power circuit diagram.

Figure 14 is 1.2V power circuit diagram among a kind of embodiment of the utility model.

Embodiment

Below in conjunction with Figure of description and specific embodiment local discharge signal acquisition system described in the utility model is described in further detail.

Local discharge signal acquisition system in the present embodiment comprises: mainboard, which is provided with at least two bus slots, synchronized sampling control signal generation circuit and system power supply, bus slot is connected to each other by self-defined bus, and the synchronized sampling control signal produces circuit the synchronized sampling control signal is provided; Be plugged in the AD(analog to digital conversion on the bus slot) sampling plate, its analog signal conversion with input is digital signal and storage; Be plugged in the DSP(DigitalSignal Processor on the bus slot, digital signal processor) signal-processing board, it reads the storage data of AD sampling plate and analyzes and obtains original sampling data.

Wherein, use the zero crossing waveform of power frequency component as the synchronized sampling control signal.Figure 11 has shown a kind of synchronized sampling control signal circuit diagram.As shown in figure 11, first diode is in parallel with second diode reverse, one end and the first resistance R 528(resistance 1K) end is connected the IN as power frequency component input end Vsync, other end ground connection; The other end of first resistance R 528 and the first voltage stabilizing diode D514(model 1N5819) negative pole, the first resistance R 513(resistance 5K1) an end, the second resistance R 515(resistance 5K1) an end, voltage comparator U507(model LM211) 2 pin link to each other; The other end ground connection of the first voltage stabilizing diode D514; The other end of first resistance R 513 and the 3rd resistance R 512(resistance 20K) an end link to each other and be connected voltage+5VD; The other end of second resistance R 515 and the 4th resistance R 511(resistance 3K6) the other end link to each other and ground connection; The other end of the other end of the 3rd resistance R 512 and the 4th resistance R 511 links to each other and is connected to 3 pin of voltage comparator U507; 8 pin of voltage comparator U507 meet voltage+5VD, and 1 pin links to each other with 4 pin and ground connection, 7 pin and the 5th resistance R 527(resistance 2K) an end and the 6th resistance R 514(resistance 100) an end link to each other; The other end of the 5th resistance R 527 links to each other with voltage+3V3D; The other end of the 6th resistance R 514 and the first capacitor C 515(appearance value 220pF) an end and Schmidt trigger input not gate U513(model SN74LVC1G17) 2 pin link to each other; The other end ground connection of first capacitor C 515; 5 pin of Schmidt trigger input not gate U513 meet voltage+3V3D, 3 pin ground connection, and 4 pin are as the output of synchronous control signal SYNC.

Wherein, voltage comparator U507 plays comparer, and the sinusoidal signal of importing is shaped to square wave, and certainly, the signal of this moment has very big distortion, also is not suitable for using.The output waveform of the voltage comparator U507 of Schmidt trigger input not gate U513 is done further shaping to reach spendable degree.

In addition, system power supply comprises :+5VAI ,-5VAI ,+3V3A ,+3V3D.

Figure 12 is+5VAI ,-the 5VAI power circuit diagram.One end of second capacitor C 500 and the positive pole of the negative pole of the second voltage stabilizing diode D500, the first electrochemical capacitor E506, an end of the 4th capacitor C 502, negative pole and the first voltage stabilizing chip U502(model LM7805CK of the 3rd diode D502) 1 pin link to each other, and connect voltage+9VAI; The positive pole of the 3rd diode D502 links to each other with 2 pin of the first voltage stabilizing chip U502, an end of the 6th capacitor C 504, the positive pole of the 3rd electrochemical capacitor E508, an end of the 7th resistance R 504, and as the output of voltage+5VAI; The other end of the 7th resistance R 504 links to each other with the positive pole of the first light emitting diode D506; One end of the other end of second capacitor C 500 and the 3rd capacitor C 501, the positive pole of the second voltage stabilizing diode D500, the negative pole of the second voltage stabilizing diode D501, the negative pole of the first electrochemical capacitor E506, the positive pole of the second electrochemical capacitor E507, the other end of the 4th capacitor C 502, one end of the 5th capacitor C 503,3 pin of the first voltage stabilizing chip U502 and 4 pin, the second voltage stabilizing chip U503(model LM7905CK) 1 pin, the other end of the 6th capacitor C 504, one end of the 7th capacitor C 505, the negative pole of the 3rd electrochemical capacitor E508, the positive pole of the 4th electrochemical capacitor E509, the positive pole of the negative pole of the first light emitting diode D506 and the second light emitting diode D508 links to each other; The other end of the 3rd capacitor C 501 links to each other with the positive pole of the 3rd voltage stabilizing diode D501, the negative pole of the second electrochemical capacitor E507, the other end of the 5th capacitor C 503,3 pin of the second voltage stabilizing chip U503 and the positive pole of 4 pin, the 4th diode D503, and connects voltage+9VAI; The negative pole of the 4th diode D503 links to each other with 2 pin of the second voltage stabilizing chip U503, the other end of the 7th capacitor C 505, the negative pole of the 4th electrochemical capacitor E509 and an end of the 8th resistance R 505, and as the output of voltage-5VAI; The other end of the 8th resistance R 505 links to each other with the negative pole of the second light emitting diode D508.

Figure 13 is+3VAI ,-the 3VAI power circuit diagram.The 5th electrochemical capacitor E512(appearance is worth 22 μ F) positive pole be worth 0.1 μ F with the 8th capacitor C 510(appearance) an end and the 3rd voltage stabilizing chip U511(model TPS76833) the 3rd pin link to each other with 4 pin, and connect voltage+5V0E; The negative pole of the 5th electrochemical capacitor E512 links to each other with 1 pin with the other end of the 8th capacitor C 510 and 2 pin of the 3rd voltage stabilizing chip U511, and ground connection; 6 pin of the 3rd voltage stabilizing chip U511 are worth 100 μ F with 5 pin with an end and the 6th electrochemical capacitor E517(appearance of the 9th resistance R 519) positive pole link to each other, and as the output of voltage+3V3D; 7 pin of the 3rd voltage stabilizing chip U511 and the other end of the 9th resistance R 519, the tenth resistance R 525(resistance 22K) an end be connected; The other end ground connection of the tenth resistance R 525; The minus earth of the 6th electrochemical capacitor E517.

According to the power requirement of TMS320C6713B, except 3.3V, also need a 1.2V voltage.

Figure 14 is the 1.2V power circuit diagram.The 7th electrochemical capacitor E405(appearance is worth 22 μ F) positive pole and the 4th voltage stabilizing chip U402(model TPS76801) 3 pin link to each other with 4 pin, and connect voltage+3V3D; The minus earth of the 7th electrochemical capacitor E405; 2 pin of the 4th voltage stabilizing chip U402 meet the PwrEN#0 of DSP, GND pin ground connection, one end, the 8th electrochemical capacitor E407(appearance of 6 pin and 5 pin and the 11 resistance R 423 are worth 22 μ F) anodal and the 9th capacitor C 404(appearance be worth 0.1 μ F) an end link to each other and as the output of power supply+1V2D the other end and the 12 resistance R 400(resistance 10K of 7 pin and the 11 resistance R 423) an end link to each other; The other end ground connection of the 12 resistance R 400; The other end ground connection of the negative pole of the 8th electrochemical capacitor E407 and the 9th capacitor C 404.

The relation of output voltage and input voltage can be passed through resistance adjustment, uses following formula:

$V_O=V_{\mathrm{ref}}\×(1+\frac{R423}{R400})$

Wherein Vref=1.2246V is internal reference voltage.

Fig. 1 has shown a kind of AD sampling plate in the local discharge signal acquisition system described in the utility model, comprises two-way local discharge signal modulate circuit, a binary channels AD module 4, a CPLD5, a self-defined bus 6, a MCU7 and a SRAM8.Portion of every road bureau discharge signal modulate circuit comprises a differential operational amplifier 1, a low-pass filter 2 and a transformer 3.Differential operational amplifier 1 receives the differential signal input of measurand, transfer single-ended signal to and export to low-pass filter 2, low-pass filter 2 is exported to transformer 3 after with this single-ended signal filtering, and transformer 3 should filtered single-ended signal transfers differential signal again to and exports to AD module 4.CPLD links to each other with AD module 4, SRAM, MCU and self-defined bus, and the output signal of 4 pairs of transformers 3 of control AD module is carried out the AD conversion, processing and the buffer memory of control AD conversion output data.MCU also links to each other with self-defined bus by the I2C bus.

The AD module can realize its function by a slice AD chip, selects this chip of AD9248 of ADI company in the present embodiment.AD9248 is 14 binary channels analog-digital chips that ADI company releases, and this chip adopts the 3.3V power supply, and speed is chosen as three kinds of 20MS/s, 40MS/s and 60MS/s.AD9248 adopts a multistage differential pipeline structure that has output error correction logic, thereby high-precision 14 quantification output is provided.Twin-channel AD9248 can provide the dynamic property same with the single channel AD converter, but again than using 2 single channel AD converter to have better cross talk resistance energy.AD9248 output data time-delay t _PDMaximal value is 6ns.Corresponding to the acquisition system of 50MHz, the retention time of data is still well-to-do on the middle AD output terminal of a clock period (20ns).

Fig. 2 is the wiring diagram of AD9248.It is difference that the simulating signal input of AD9248 requires, and therefore, the signal of single-ended input becomes differential signal after signal transformer is handled; And VCom lifts voltage level, and generally getting VCom is 1/2 supply voltage; For guaranteeing the accuracy of AD conversion, it is proper to be suitable for external voltage reference, and Vref is the stable level that is produced by the voltage stabilizing chip; The sampled data output of two passages is stitched together and forms one 32 data, is connected in data bus DM_D[0..31] on; The driving clock signal of two passages of AD9248 provides by CPLD; Power supply sleep mode signal also is connected on the CPLD, accepts the control of CPLD.

SRAM in the present embodiment is as the local cache on the AD sampling plate, and present embodiment is selected IS61LV51216 for use.IS61LV51216 is the asynchronous CMOS static RAM (SRAM) of 512K16bit of 3.3V power supply, has the characteristics of high-speed low-power-consumption.Fig. 3 is the wiring diagram of IS61LV51216.IS61LV51216 is 16 chips, and present embodiment is combined into 32 with two.

CPLD present embodiment in the present embodiment is selected CPLD---the XC95144 of the XC9500XL series of Xilinx company for use.

Fig. 4 has shown a kind of DSP signal-processing board in the local discharge signal acquisition system described in the utility model, it comprises a DSP, and a SDRAM9, the FLASH10, self-defined bus 11, a network interface 12, a house dog 13, the data selector 14 that link to each other respectively with DSP, this data selector provides a host computer interface 15, links to each other with usb host chip 16 simultaneously.

DSP adopts the TMS320C6713B of TI company in the present embodiment, its inside comprises CPU and on-chip memory (also can be set to L2 cache), and some functional modules, comprise EMIF(External MemoryInterface, external memory interface), I2C bus, two Timer(clocks), the GPIO(universal I/O port) and HPI(HOST PORT INTERFACE, host port interface).

The CPU of TMS320C6713B comprises: decoding, distributor gear are read in and instructed to program.Comprising that program is got refers to unit, instruction dispatch unit and instruction decoding unit.Program is got and is referred to that the unit is linked to each other with sheet internal program storer by program bus.Program execution mechanism comprises two symmetric data path A and B, the functional unit of the general purpose register set of two symmetries, two groups of symmetries (every group four .L .S .M .D), control register group and steering logic and interrupt logic etc.Every group of data path has the bus of reading in and storing data, links to each other with data-carrier store in the sheet.Chip testing and emulated port and steering logic thereof.What the C6000 series DSP of TI adopted is Harvard structure, and namely program bus is what separate with data bus, and instruction fetch walks abreast when executing instruction like this, and the von Neumann structure of this and program bus and data bus unified addressing is distinct.The clock module based on PLL of TMS320C6713B: TMS320C6713B has in the sheet based on PLL phaselocked loop and the pll controller peripheral hardware that can control flexibly, this peripheral hardware provides a pretreater (OSCDIV1) and four frequency divider (PLLDIV0, PLLDIV1, PLLDIV2, PLLDIV3).Pll controller can produce the various piece that different frequencies is given system, comprises DSP kernel, external data bus etc.

In the present embodiment, the outside active crystal oscillator that uses 50MHz; Be set to 1 through frequency divider PLLDIV0(), obtain being still the 50MHz clock; And then be 8 frequencys multiplication of a PLL, the frequency multiplication frequency is brought up to 400MHz.PLLDIV1=2, PLLDIV2=4, PLLDIV3=4 are set respectively, and obtaining the core cpu frequency is 200MHz, and peripheral bus control is 100MHz with EMIF external interface clock ECLKOUT frequency.OSCDIV1=2 is set in addition, provides the 25MHz clock to use to other parts of system, output port is CLKOUT3.

The ram in slice of second-level storage: TMS320C6713B adopts the second level cache structure in the sheet of TMS320C6713B, and program and data have separately independently high-speed cache.First order program buffer memory in the sheet is called L1P, and first order data buffer memory is called L1D, and the second level storer of program and data sharing is called L2.L1P adopts direct mapping structure (direct mapped cache), can only can not be set to mapping register as buffer memory, does not also freeze (freeze) and straight-through (bypass) pattern.L1D adopts two-way group associative structure (2-way set associative cache), and is the same with L1P, only as buffer memory, and can not be as the storer of mapping.The application that the L2 controller is handled is from 3 direction: L1D, L1D and EDMA; Be configured to the part of SRAM among the L2, its access is just the same with general RAM, is configured to the part of buffer memory, and operation is similar with L1D.

The EMIF:DSP of TMS320C6713B must pass through EMIF when visiting chip external memory.The EMIF of C6000 series DSP has very strong interface capability, not only has very high data throughput, and can with the storer direct interface of present nearly all type, the SBSRAM(Synchronous Burst Static Random Access Memory that comprises pipeline (pipeline) structure, synchronization burst static RAM (SRAM)), SDRAM; Asynchronous device comprises SRAM, ROM and FIFO etc.

System need provide an external clock for TMS320C6713.After being imported by ECLKIN, this external clock can produce the clock signal ECLKOUT of EMIF interface.The signal multiplexing of SBSRAM interface, sdram interface and asynchronous interface.Because not needing to carry out the backstage refreshes, and allows to have simultaneously this storer of three types in the system.CE1 supports in the space three kinds of all memory interfaces.Synchronous memory interface provides 4word burst access mode.Sdram interface is more flexible, supports SDRAM configuration widely.EMIF can visit the storer of 8/16/32bit width, supports the little-endian(little-endian) and the big syllable sequence of big-endian() pattern.ROM and asynchronous memory are not distinguished.Minimum micrologic address regulation is by the output of EA pin, and EMIF is inner can be done displacement with logical address and adjust output automatically according to the word length of visit data.The access of data is always carried out according to 32bit in the TMS320C6713B sheet, and during the outer 8/16bit data of visit sheet, EMIF can finish data packings (packing) automatically and unpack (unpacking) processing.During for example to 1 32bit data of outside 8bit memory write, it is 4 8bit that EMIF can unpack packet automatically, writes destination address N, N+1, N+2 and N+3 successively.TMS320C6713B is divided into four spaces (CE2, CE3), the addressing address in each space is that 256Mbytes(such as CE0 address are 0x80000000-0x8FFFFFFF for CE0, CE1) to peripheral interface EMIF.Below four spaces of EMIF are described in detail its function and the mode of connection respectively.

1.CE0 space: SDRAM dynamic memory

The storage organization of SDRAM is more special, its elementary cell can not be addressed separately, these elementary cells are connected to same alignment (Row line) and same line (Column line), have formed a matrix structure, and this matrix structure is exactly a Bank.Most SDRAM chip is made up of 4 Bank.The principle of work of SDRAM is that RAM is controlled with identical clock frequency with CPU, makes the outer frequency of RAM and CPU synchronous, completely abolishes access latency.Thereby RAS and CAS namely control the correct page or leaf of address selection and unit that SDRAM obtains row and row.Owing to the physical arrangement characteristics of DRAM, so must keep the Refresh Data of certain intervals, this is realized by its internal hardware in addition.

The EMIF of TMS320C6713B provides the seamless link controller with nearly all type SDRAM memory interface, and single CE space can connect the SDRAM of 512Mbit at most.Consider the requirement of analyzing local discharge signal, need lot of data storage and computer memory, so native system connected the SDRAM of 64Mbytes, the address is 0x80000000-0x83ffffff.

SDRAM chip commonly used at present is 8 and 16 bit data width, operating voltage 3.3V.It is the SDRAM of MT48LC16M16A2 that present embodiment is selected the model of MICRON company, and its memory capacity is 4Megx16x4banks, and namely SDRAM inside is divided into 4 bank, and externally bus interface is 16 bit widths.Every 32M byte capacity altogether; Packing forms adopts 54 pin TSOP; Support to refresh automatically working method; 3.3V operating voltage [26] is adopted in the input and output of compatible LVTTL level.

Fig. 5 is TMS320C6713B and MT48LC16M16A2 interface synoptic diagram.DQM[3:0 wherein] combine D[31:0 by UDQM and the LDQM of two chip blocks] formed by the 16bit data line combination of two chip blocks.

The EMIF CE0 space pin function of TMS320C6713B is described as follows:

ECLKOUT offers SDRAM and reads and writes clock synchronously;

/ SDRAS ,/SDCAS ,/SDWE are respectively the read-write controllers of SDRAM;

BE[3:0] offer SDRAM as the byte mask signal of 32 bit data, connect DQM[3:0];

EA[13:2] offer SDRAM as column address, connect A[11:0];

EA[14] offer SDRAM as row address, connect A[12];

EA[16] and EA[15] offer SDRAM and select as Bank, BA1 and BA0 connected.

TMS320C6713B also provides SDCTL in addition, SDTIM, and the SDRAM control register that SDEXT etc. are special-purpose is for foundation, retention time that each control signal is set, row address, column address number, signal delay time, refresh mode etc.

2.CE1 space: FLASH procedure stores

Owing to do not have EEPROM or FLASH storer to come save routine among the TMS320C6713B, therefore must expand by peripheral interface.

In the TMS320C6713B Starting mode, wherein a kind of is that automatically the program of the asynchronous system copy 1Kbytes by acquiescence enters the DSP internal RAM from the CE1 space, then since 0 address executive routine.Present embodiment selects for use FLASH as program storage, uses the asynchronous interface mode of acquiescence to connect DSP.

Maximum address space, CE1 space remains 256Mbytes, supports the 8bit/16bit/32bit data width.Present embodiment selects for use the AM29LV160D chip of AMD to be used for program and the digital signal processing storer of tabling look-up.

The AM29LV160D chip is 1Mx16bit, altogether 2M bytes store capacity; CMOS technology, operating voltage 3.0 ± 0.3V level; Packing forms is the accurate TSOP of 48 footnotes; Chip can work under 8 or 16 two kinds of patterns; Under the power supply of 3V standard, can finish the online data programing of system and data erase operation.This chip internal structure is divided into and is divided into 34 sectors (Sector), (this family chip is divided into Top type and Bottom type two classes except the sector that startup (Boot) will be used, represent the position of bootsector respectively, adopt AM29LV160DT in the actual design, the Top type), the size of each Sector is 64KBytes.The processor read operation can directly be carried out data access to the address.Programming and programming operation must at first write the initialization command sequential, when specific period, continue to write after particular command and the particular address, and chip internal namely can carry out corresponding operating.When chip was in this kind internal state, outside other operations were invalid, but can judge whether the process of wiping or writing finishes (level of this pin replaces change in each read cycle) by the state that checks data line 6 pin.Command sequence and sequential according to standard in the reality are write test procedure, be used for finishing to data programming, the full wafer of FLASH wipe, sector erasing and other associative operation.

Because be the asynchronous read and write mode, though the addressing space 256Mbytes of CE1, all EMIF address wire EA[21:2 of the AM29LV160D chip of 16bit], the address is: 0x90000000 ~ 0x901FFFFF.

Fig. 6 is the wiring diagram of the asynchronous storage of TMS320C6713B (ASRAM) controller and AM29LV160D chip./ BY pin is used for the state (ready/busy) of output FLASH.Owing to have special control register that sequential and the control time of read-write are set in the asynchronous memory controller of TMS320C6713B, so do not use this pin.

3.CE2 space: self-defined bus interface

A most important task of DSP signal-processing board is to read the sampled data of each AD sampling plate, and the buffer memory on each AD sampling plate is exactly SRAM, and TMS320C6713B links together by the SRAM on self-defining bus and each the AD plate.SRAM capacity on every AD sampling plate is 2MByte, in the design proposal of AD sampling plate the SRAM of 16bit is expanded to 32bit simultaneously and uses, and therefore, this moment, the EMIF of DSP visited external memory in the mode of 32bit.Reference address is 0XA0000000 ~ 0XA03FFFFF.

Fig. 7 is the wiring diagram of TMS320C6713B and SRAM, and the asynchronous write signal of EMIF/AOE connects output enable/OE of SRAM; / CE1 connects chip selection signal/CE of SRAM; / AWE connects writing of SRAM and enables.

4.CE3 space: extended network interface

Network interface based on ICP/IP protocol of expansion in the DSP signal-processing board.This chip internal of TMS320C6713B is not realized the hardware capability of TCP/IP, need expand a hardware chip of realizing this function outside.Through relatively, select a network interface chip of WIZnet company for use.

Be the system extension network function, traditional way is to implant the ICP/IP protocol stack in embedded device, perhaps transplants an embedded OS with ICP/IP protocol stack.Though above-mentioned way has obtained good effect in a lot of the application, be cost to sacrifice ample resources all.And the hardware protocol stacks that this chip is realized can be finished network communication fast under the condition that takies extremely low system resource.It has following characteristics:

Hardware protocol stacks comprises TCP, IPVer.4, UDP, ICMP, ARP;

Support hardware Ethernet protocol DLC and MAC;

Support four tunnel network connections independently simultaneously;

Support the Ping order;

Protocol processes speed reaches full duplex 4～5Mbps;

Support Intel/Motorola MCU bus interface;

Support the I2C interface;

Have the MII interface of standard, can connect the bottom ethernet interface chip;

The exploitation of Socket API accelerating application can be provided;

Support full-duplex mode;

The built-in 16KB dual port RAM can be used as the data buffer;

Adopt 0.35 μ mCMOS manufacturing process.

The main pin function of chip:

TXD[0]～TXD[3]: send data at the TXD_CLK rising edge.During serial mode, TXD[0] send pin, TXD[1 as serial data]～TXD[3] invalid.

TXE: send Enable Pin.

TXD_CLK: the data tranmitting data register, clock is provided by the Ethernet interface chip.

RXD[0]～RXD[3]: receive data at the TXD_CLK negative edge.During serial mode, RXD[0] receive pin, RXD[1 as serial data]～RXD[3] invalid.

RXDV/CRS: carrier monitoring.High level is effective.

RXD_CLK: data reception clock.Clock is provided by the Ethernet interface chip.

COL: conflict detective pin.It is effective when semiduplex mode clashes.

A[14～8]/DA[6～0]: under MCU bus interface pattern as 14～8 bit address.Under the I2C pattern as 6～0 device addresses of I2C interface.

A[7～0]: 7～0 bit address lines.

D[7～0]: 8 position datawires.

INT: receive and send interrupt request.Low level is effective.

CS: chip selection signal.Low level is effective.

WR: write signal.Low level is effective.

RD: read signal.Low level is effective.

RESET: reset signal.

CLOCK: work clock.Usually provided by the Ethernet interface chip, recommended frequency is 25MHz.

EXT_CLK: external clock input signal.

LINK: whether expression has been connected to Ethernet.Low level is represented to connect effectively, and high level is represented the overtime or connection closed of T CP.

SERIAL:10BASE-T SERIAL or NIBBLE select.

FDPLX: full-duplex/half-duplex is selected.0 is full duplex, and 1 is half-duplex.

MODE[2～0]: be used for selecting the W3001A mode of operation.000 is clock module; 001 is the external clock pattern; 010 is no clock module; 011 is the I2C pattern; 1xx is test pattern.

Network interface chip has 3 kinds of different mode of operations, is respectively Direct BusI/F pattern, Indirect BusI/F pattern and I2C BusI/F pattern.The user can select according to the actual conditions of oneself.Consider the requirement of the transmission performance of system, the utility model uses Direct BusI/F pattern.

Fig. 8 be network interface chip under Direct BusI/F with the line graph of TMS320C6713B.The asynchronous control interface of TMS320C6713B (comprise/ARE ,/AWE), 8bit data bus ED[7:0], 15 bit address buses (EA[16:0]), CE3 chip selection signal/CE3 is connected the MCU interface of network interface chip.The MII interface of network interface chip then links to each other with networked physics layer control chip (Enthernet PHY).

The EDMA of TMS320C6713B:

EDMA(Enhanced Direct Memory Access, strengthen the direct memory visit) be important data access mode among the C6000DSPs, it can be under the situation that does not have CPU to participate in, and finishes data-moving in the DSP storage space by the EDMA controller.Source/the purpose of data-moving can be that on-chip memory, sheet are inside and outside if external devices.

The EDMA controller is responsible for the data transmission between the interior L2 storer of sheet and other peripheral hardwares.

The EDMA controller comprises:

Event and interruption processing register;

The event code device;

Parameters R AM;

Hardware address produces.

Event registers control is caught the EDMA event.An event is equivalent to a synchronizing signal, triggers an EDMA passage by it and begins data transmission.If a plurality of events take place simultaneously, then by the event code device they are differentiated.Deposited relevant transmission parameter among the parameters R AM of EDMA, these parameters can be admitted to address generator hardware, produce the needed address of read-write operation.

Strengthen the first level address visit and start EDMA for TMS320C6713B provides different types of characteristic: CPU or Event triggered; The connection (linking) of many group EDMA parameters; The EDMA break in service; The link of a plurality of EDMA passages (chaining) etc.

TMS320C6713B also provides another transmission mode: QDMA(quick DMA).The function class of QDMA and EDMA seemingly, but transfer efficiency is higher, is particularly suitable for needing the application scenario of quick Data transmission, for example the data-moving task in the tightly coupled loop code.In native system, data sampling also is to use the QDMA transmission to finish from the storage that FIFO reads SDRAM.

The internal mechanism of QDMA has guaranteed that application has very high submission efficient:

Fast decoding can be finished the write operation of QDMA register in the monocycle.Therefore, the QDMA application generally just can really be issued at 5 all after dates.In contrast to this, first application of EDMA need just can be issued at 36 all after dates.

After the transmission application of QDMA is sent, the content of QDMA physical register will remain unchanged.Therefore, for same QDMA transformation task, need not to reset these registers, follow-up each QDMA transmission application can be sent (this cycle is used for writing " pseudo-mapping " register) immediately at 1 all after date again.

The GPIO of TMS320C6713B:

Integrated general I/O peripheral hardware (GPIO) provides 16 pin GPIO[15:0 among the TMS320C6713B] (other signal multiplexing of part GPIO pin and chip), can be configured to input or output by the user.The GPIO pin can also produce CPU and interrupt or the EDMA synchronous event.

TMS320C6713B provides the several Control register that the function of GPIO is set, and comprises general input/output function, produces GPIO and interrupts, and triggers EDMA synchronous event etc.

After enabling in the GPEN register, corresponding GPIO pin can be used as general input and output pin.Can in the GPDIR register, select the direction of I/O.The GPIO inside modules is also integrated, and an edge detects logic, can catch the situation of change of level on the input pin in GPDH and GPDL register.

The GPIO pin is as when input, can send to CPU with following two kinds of patterns to interrupt or trigger the EDMA synchronous event.

1. direct mode operation (Pass Through Mode)

The signal of importing on the GPx pin directly triggers CPU and interrupts and the EDMA event.Level on the GPx pin changes will produce the GPINTx signal.All GPINTx can be sent to EDMA as synchronous event, but have only GPINT0 and GPINT[4:7] can trigger the CPU interruption.

2. logical schema (Logic Mode)

Under the logical schema, produce interruption or synchronous event by the logical combination at input signal edge or the logical combination of incoming signal level, at this moment also need to arrange other register certainly.

Most pins of GPIO all are multiplexing, and wherein GP2 and CLKOUT2 are multiplexing, and GP4-GP7 and external interrupt EINT4-EINT7 are multiplexing, and all the other GPx pins are all multiplexing with the HPI mouth.GPIO is as the control pin of expansion and the ExCtlIN[0..3 of self-defined bus in the effect of native system], ExCtlOUT[0..3] link to each other, be convenient to the work that DSP controls each piece AD daughter board neatly.

The interruption of TMS320C6713B:

The CPU of TMS320C6713B has 3 types of interruptions, namely/RESET(resets), maskable interrupts (NMI) and maskable interrupts (INT4-INT15).Wherein, reset interrupt has limit priority, and the maskable interruption is not second priority, and corresponding signal is the NMI signal, lowest priority interrupt INT15./ RESET, NMI and some INT4-INT15 signals are reflected on the pin of chip, and some INT4-INT15 signal is used by peripheral hardware in the sheet, and some may be useless, or use under software control.

TMS320C6713B has eight register management breaks in service.They are that state of a control register (CSR), interruption enable (IER), interrupt identification (IFR), interruption setting (ISR), interruption zero clearing (ICR), break in service list index (ISTP), maskable interrupts return pointer (NRP), interruption return pointer (IRP).

Use and interrupt considering problems such as interrupt nesting, trap.

In the present embodiment, mainly having used 6 interruption: RESET is system's reset interrupt; EINT4 provides the interrupt request of W3100A; EINT6, EINT7 offer self-defined bus, can respond the interrupt request of AD sampling plate like this; Also have an EDMA to interrupt at last.

The I2C interface of TMS320C6713B:

TMS320C6713B has two I2C modules, can simplied system structure: as being used for the local peripheral IC(of control such as ADC, DAC etc. when an I2C bus) time, another I2C bus can with system in other controller communications, user interface perhaps is provided.

The I2C universal serial bus of TMS320C6713B has following characteristics:

With Philip I2C codes and standards 2.1 editions (in January, 2000) compatibility;

Quick mode reaches as high as 400Kbps;

Noise filter;

The device addressing mode has two kinds of 7bit and 10bit;

Initiatively (Master) pattern and passive (Slave) pattern;

Event: DMA interrupts poll.

The utility model uses the I2C of MCU in I2C module and the AD sampling plate to connect together, by link together passage outside the composition data transmission channel of self-defined bus.DSP can communicate by letter with daughter board by the I2C bus like this, and can carry out the data transmission of small data quantity.

The HPI interface of TMS320C6713B:

TMS320C6713B provides the host computer control function, i.e. HPI interface (Host Port Interface).HPI interface DSP and PERCOM peripheral communication are used 16 bit parallel interfaces.Ppu can be administered the ownership of this interface and use the DMA/EDMA controller directly to visit the storage space of DSP (the interior peripheral hardware of sheet that comprises its mapping) by it.

The HPI interface pin function of TMS320C6713B sees Table 1:

Table 1HPI interface pin function

HPI provides 3 registers to finish communication between processor, is respectively:

HPI data register (HPID) is deposited the data that read between processor or write;

HPI address register (HPIA), the address (word address, so minimum two be fixed as 0) of depositing current ppu visit DSP storage space;

HPI control register (HPIC), 32 of word lengths, the corresponding same storage area of height 16 bit data, i.e. it is also identical that content unanimity and palpus maintenance writes height 16 bit data.

(be the HINT position of set HPIC register except main frame being sent out interruption, make the HINT line effective) and to remove interruption (namely removing the DSPINT sign of HPIC register) that main frame sends and need outside the DSP internal processes interferes, the DMA passage in other operating sheet is can be automatically auxiliary finishes data transmission between storage area and the HPI register.

Fig. 9 is HPI interface and the main frame wiring diagram of TMS320C6713B, and a plurality of redundant signals are provided, and purpose is to be convenient to and dissimilar processor interfaces, data HD[15:0] highway width is 16.

Main frame is operated the visit that can finish HPI according to following order:

Initialization HPIC register;

Initialization HPIA register;

Read/write data from the HPID register.

To the visit of any one register of HPI, main frame all need be on the HPI bus order carry out twice half word(and account for two bytes) access.General main frame should not interrupt twice such access, otherwise may cause losing of whole data.Before access data, must carry out initialization to HPI, comprise HPIC and HPIA register are set.Key is the HWOB position among the HPIC, the order of transmission of clear and definite MSB16 and LSB16.

HCNTL[1:0] which HPI register what indicate read-write at present is, table 2 is to specify:

The selection function explanation of table 2HCNTL0/1

The usb host interface of TMS320C6713B:

1.USB host interface chip

TMS320C6713B is not with the usb host interface, the chip that therefore needs expansion a slice to have the usb host interface function.The utility model adopts the EZ-USB FX2 single-chip microcomputer of Cypress Semiconductor company as the USB interface main control chip, and EZ-USB FX2 is that first supports the single-chip microcomputer of USB2.0 and backward compatible USB1.1 standard of while in the world.

FX2 is responsible for the control that the USB issued transaction also has microprocessor concurrently, can be used as the main control chip of USB device class device.This chip is USB2.0 transceiver, SIE(Serial Interface Engine, serial interface engine), 8051 kernels, I2C bus interface and the G PIF(General Programmable Interface that strengthen, general programmable interface) be integrated in one.Its high cost performance makes the FX2 chip obtain using widely in various USB expansion equipments such as storer, printer, scanners, and its function has comprised:

Internal USB 2.0 transceivers and serial interface engine SIE;

8051 kernels that strengthen, the highest 48MHz of clock frequency also has two UART Universal Asynchronous Receiver Transmitter (UART), three Timer and two automaticdata pointers simultaneously, supports external interrupt;

Can pass through usb bus download firmware program, also can be by the EEPROM download firmware program of I2C bus expansion.Support control transmission, interruption transmission, batch transmission and synchronous transmission;

Have 8bit or 16bit external data interface (only limiting to the encapsulation of 128 pin);

Built-in I2C interface module, frequency of operation is at 100KHz or 400KHz;

Two kinds of patterns of external interface.A kind of Master pattern is used GPIF; Another kind of Slave pattern uses integrated FIFO for the external unit read-write.

2.FX2GPIF with DSP HPI interface

FX2 provides a powerful general programmable interface GPIF and end points FIFO, not only can with outside ASIC(Application Specific Integrated Circuit, special IC) or microprocessor connect, can also realize and being connected of DSP etc.

GPIF is an internal controller, and it operates under inner 30MHz or the 48MHz clock, can come configurable clock generator by 8051.IFCLK can provide the clock source of 30MHz or 48MHz for the outside, also can provide clock by external circuit, and scope to the arbitrary value between the 48MHz, is used for synchronous GPIF and external unit at 5MHz.

G PIF is the Master main equipment of end points FIFO, and its core can be a programmable state machine of state, exports one group of control signal CTL[5:0]; One group address is selected signal GPIFADDR[8:0]; One group of input RDY[5:0] logical signal of obtaining peripheral hardware satisfies their agreement read-write requirement, and two from FX2 inside.

Figure 10 is the wiring diagram of EZ-USB FX2 and TMS320C6713B.Wherein PA3 is connected HCNTL[1:0 with PA2], in order to select the HPIC of HPI, HPIA or HPID register; CTL0-CTL2 is that read-write control line, the RDY0 that GPIF provides connects HPI/HRDY, and these control lines can be programmed by waveform, and the read-write sequence of FX2GPIF and the HPI of C6713B are complementary; INT0 interrupts connecting the output interruption/HINT of HPI mouth, and DSP can give the FX2 interrupt request like this.Other GPIF pin that does not need to control is all drawn high or ground connection by resistance, uses fixed logic.

3.USB remainder interface

Comprise reset circuit, clock circuit, wake-up circuit, IO mouth etc.

EZ-USB FX2 chip is wanted and can normally be moved, and must have some basic adjunct circuits to do assurance, comprises reset circuit, clock circuit etc.

Reset circuit has two aspect effects, and one is resetting when powering on; Another is the debug phase, adds button and makes chip reset, holding circuit.Clock circuit uses passive 24MHz crystal oscillator, and two ends are by the capacity earth of 22pf, and the two ends of crystal oscillator are connected on the XTALIN and XTALOUT of chip.Wake-up circuit does not use in native system, therefore/and the WAKEUP pin draws high always.Some IO mouths of FX2 insert among the CPLD, can read and write to DSP when needed expansion is provided.

The design of serial i 2C bus circuit:

The FX2 chip is one, and 8051 program codes wherein and deposit data are in internal RAM based on the framework of software, and main frame can download to internal RAM to code and data by usb bus.Can certainly use EEPROM to enumerate with program loads: after system powers on, whether the USB kernel at first checks EEPROM on the I2C bus, if having, and first bit data is 0Xc2, then FX2 copies the full content among the EEPROM in the internal RAM to, and begins to carry out the firmware among the RAM.Here hardware design must be noted that 2 points, one be two I2C buses must on draw, the 2nd, set the address of I2C.

Be noted that above enumerate only for specific embodiment of the utility model, obviously the utility model is not limited to above embodiment, and many similar variations are arranged thereupon.If those skilled in the art all should belong to protection domain of the present utility model from all distortion that the disclosed content of the utility model directly derives or associates.

Claims (11)

1. the acquisition system of a shelf depreciation array signal is characterized in that, comprising:

One mainboard which is provided with at least two bus slots, synchronous sampling control signal generation circuit and a system power supply, and described bus slot is connected to each other by self-defined bus, and described synchronized sampling control signal produces circuit the synchronized sampling control signal is provided;

One is plugged in the AD sampling plate on the described bus slot, and its analog signal conversion with input is digital signal and storage;

One is plugged in the DSP signal-processing board on the described bus slot, and it reads the storage data of described AD sampling plate and analyze and obtains original sampling data.

2. the acquisition system of shelf depreciation array signal according to claim 1 is characterized in that, described AD sampling plate comprises:

Portion of at least one road bureau discharge signal modulate circuit that is located thereon;

At least one AD module that is located thereon, described AD module and the corresponding connection of described local discharge signal modulate circuit;

A CPLD who links to each other with described self-defined bus with described AD module who is located thereon;

A memory module that is connected with described AD module with described CPLD that is located thereon.

3. the acquisition system of shelf depreciation array signal according to claim 2 is characterized in that, described memory module comprises SRAM.

4. the acquisition system of shelf depreciation array signal according to claim 2, it is characterized in that, described local discharge signal modulate circuit comprises: an operational amplifier and a low-pass filter that is connected with described operational amplifier, described operational amplifier transfers differential signal to single-ended signal, and described low-pass filter carries out filtering with described single-ended signal and handles and export to described AD module.

5. the acquisition system of shelf depreciation array signal according to claim 4, it is characterized in that, described local discharge signal modulate circuit also comprises a transformer, it is connected with described low-pass filter, and the single-ended signal that described transformer transmits low-pass filter transfers differential signal to and exports to described AD module again.

6. the acquisition system of shelf depreciation array signal according to claim 2 is characterized in that, described local discharge signal modulate circuit has two-way, and described AD module has two.

7. the acquisition system of shelf depreciation array signal according to claim 2 is characterized in that, described AD sampling plate also comprises a MCU who links to each other with CPLD who is located thereon.

8. the acquisition system of shelf depreciation array signal according to claim 1 is characterized in that, described DSP signal-processing board comprises:

A DSP who links to each other with described self-defined bus who is located thereon;

A synchronous dynamic RAM that links to each other with described DSP that is located thereon;

A flash memory that links to each other with described DSP that is located thereon;

A network interface that links to each other with described DSP that is located thereon.

9. the acquisition system of shelf depreciation array signal according to claim 8 is characterized in that, described DSP signal-processing board also comprises: a usb host interface module that links to each other with described DSP that is located thereon.

10. the acquisition system of shelf depreciation array signal according to claim 9 is characterized in that, described DSP signal-processing board also comprises: the data with described DSP links to each other with described usb host interface module that are located thereon are selected module.

11. the acquisition system of shelf depreciation array signal according to claim 8 is characterized in that, described DSP signal-processing board also comprises: a monitoring module that links to each other with described DSP that is located thereon.

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