CN206147623U - Gather processing card device based on large capacity FPGA - Google Patents
Gather processing card device based on large capacity FPGA Download PDFInfo
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- CN206147623U CN206147623U CN201620897831.8U CN201620897831U CN206147623U CN 206147623 U CN206147623 U CN 206147623U CN 201620897831 U CN201620897831 U CN 201620897831U CN 206147623 U CN206147623 U CN 206147623U
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Abstract
The utility model discloses a gather processing card device based on large capacity FPGA, including AD chip, FPGA and DSP, the 14bit400MSPS sampling is supported to the AD chip, and the AD chip is used for gathering and changing the intermediate frequency signal that SMA inserted, AD chip and FPGA communication, communicate between FPGA and the DSP, DSP and host computer communication, FPGA is the LX155 chip, FPGA is used for sending into data to the AD chip and analyzes to data transmission after will analyzing gives DSP, the FFT operation is carried out to the data that DSP is used for sending into FPGA to give the host computer with computation result packing transmission. The utility model discloses well AD chip sample rate reaches as high as 14bit400MSPS, chooses the LX155 chip of large capacity with FPGA+DSP framework completed number for use according to processing, FPGA again, makes the utility model discloses beneficial effect such as the volume of having data storage is big, throughput is strong can satisfy present signal processing board's the market demand.
Description
Technical field
This utility model is related to data acquisition process technical field, is specifically related to a kind of collection based on Large Copacity FPGA
Process card device.
Background technology
Data acquisition process signal acquisition process plate is mainly used in signal echo collection, radar signal reconnaissance and receives, stores up
Frequency interference, software radio etc. need the occasion of acquisition process, require in such applications data acquisition process plate can while
Possess powerful acquisition capacity, disposal ability and high speed transmission abilities.
Current acquisition process plates most of in the industry are built by monolithic ADC and fpga chip, had that sample rate is low, are adopted
Belt transect width is little, capacity is little, the low shortcoming of signal handling capacity.
The content of the invention
The purpose of this utility model is to overcome the deficiencies in the prior art, there is provided a kind of collection based on Large Copacity FPGA
Process card device, this utility model adopts FPGA+DSP frameworks, improves the signal handling capacity of this acquisition and processing card, and with compared with
Big memory capacity, solves the technical problem that current Information Collecting ＆ Processing plate cannot meet practice demand.
Utility model purpose of the present utility model is achieved through the following technical solutions：
A kind of acquisition process card device based on Large Copacity FPGA, including A/D chip, FPGA and DSP, the A/D chip
Hold 14bit/400MSPS sampling, A/D chip for the intermediate-freuqncy signal that SMA is accessed is acquired and is changed, the A/D chip with
FPGA communicates, and communicates between the FPGA and DSP, and the DSP is communicated with host computer, and the FPGA is LX155 chips, described
FPGA is parsed for sending into data to A/D chip, and the data after parsing are transferred to DSP, and the DSP is for by FPGA
The data of feeding carry out FFT computings, and operation result packing is transferred to host computer.
Intermediate-freuqncy signal is transferred to A/D chip by SMA by this utility model, and A/D chip will be sent after completing data high-speed conversion
Enter FPGA parsings, then Jing DSP carry out FFT computings, then by PC104+ bus transfers to host computer, host computer can also pass through
Order and parameter are passed under PC104+ buses to DSP and FPGA.In this utility model, A/D chip sample rate reaches as high as 14bit/
400MSPS, and data processing is completed with FPGA+DSP frameworks, FPGA selects jumbo LX155 chips, has this utility model
There are the beneficial effects such as memory data output is big, disposal ability is strong, the market demand of present signal-processing board can be met.
Further, the intermediate-freuqncy signal point two-way input A/D chip that SMA is accessed, is directly output to Jing after A/D chip all the way
FPGA, another road are input into A/D chip after a front end Rhizoma Nelumbinis are closed again, and the front end Rhizoma Nelumbinis are closed and become including the first order being sequentially connected
Depressor and second level transformator, the first order transformator are converted to difference by single-ended signal for the intermediate-freuqncy signal for accessing SMA
Sub-signal, the second level transformator be used for adjustment by first order transformator change after the positive and negative two ends of differential signal amplitude and
The concordance of phase place, the signal after the adjustment of second level transformator are input into A/D chip Jing after RC resistance-capacitance networks.Close without front end Rhizoma Nelumbinis
Signal all the way be used for the initial data that FPGA preserves A/D chip, the premenstrual end Rhizoma Nelumbinis of intermediate-freuqncy signal reduce harmonic distortion after closing, are easy to
FPGA carries out dissection process.
Further, the plug-in two groups of DDR2 controllers of the FPGA, DDR2 controllers capacity described in each group are 512MB,
Data bit width is 16bits, supports that the ping-pong operation of two groups of DDR2, DDR2 controllers are used for the initial data for caching A/D chip.
Further, the FPGA is LX155 chips, and the DSP is ADSP-TS201 chips, is hung with outside the DSP
SDRAM and FLASH.
Further, the SDRAM chips are MT48LC32M16A2TG-75IT, and the FLASH chip is
S29GL032N90TFI03。
Further, the data after the FPGA parsings are transferred to DSP by EDMA modes.
Further, also including Clock management module, the Clock management module includes a 50MHz crystal oscillator and one
40MHz, wherein 50MHz crystal oscillators provide clock for A/D chip Jing after clock chip A, and 40MHz crystal oscillators are FPGA Jing after clock chip A
Clock is provided with DSP.
Further, the DSP is communicated with host computer by PC104+ buses.
This utility model compared with prior art, has the following advantages and advantages：
In this utility model, A/D chip sample rate reaches as high as 14bit/400MSPS, and completes number with FPGA+DSP frameworks
According to process, FPGA selects jumbo LX155 chips, makes this utility model have that memory data output is big, disposal ability is strong etc. and has
Beneficial effect, can meet the market demand of present signal-processing board.In addition, the intermediate-freuqncy signal that SMA is accessed in this utility model is divided to two
Road is input into A/D chip, is directly output to FPGA all the way Jing after A/D chip, and another road is input into AD cores after a front end Rhizoma Nelumbinis are closed again
Piece, the premenstrual end Rhizoma Nelumbinis of intermediate-freuqncy signal reduce harmonic distortion after closing, and are easy to FPGA to carry out dissection process.
Description of the drawings
Accompanying drawing described herein is used for providing further understanding this utility model embodiment, constitutes the one of the application
Part, does not constitute the restriction to this utility model embodiment.In the accompanying drawings：
Fig. 1 is theory diagram of the present utility model；
Fig. 2 is front end Rhizoma Nelumbinis conjunction theory diagram in this utility model；
Fig. 3 is clock distribution schematic diagram of the present utility model.
Specific embodiment
To make the purpose of this utility model, technical scheme and advantage become more apparent, with reference to embodiment and accompanying drawing,
The utility model is described in further detail, and exemplary embodiment of the present utility model and its explanation are only used for explaining this
Utility model, is not intended as to restriction of the present utility model.
Embodiment 1：
As shown in figure 1, a kind of acquisition process card device based on Large Copacity FPGA, including A/D chip, FPGA and DSP, AD
Chip support 14bit/400MSPS sampling, A/D chip for the intermediate-freuqncy signal that SMA is accessed is acquired and is changed, A/D chip
Communicate with FPGA, communicate between FPGA and DSP, the DSP is communicated with host computer, FPGA is LX155 chips, and FPGA is used for
Data are sent into A/D chip to parse, and the data after parsing are transferred to into DSP, DSP enters for the data for sending into FPGA
Row FFT computings, and operation result packing is transferred to into host computer.
Intermediate-freuqncy signal is transferred to A/D chip by SMA by this utility model, and A/D chip will be sent after completing data high-speed conversion
Enter FPGA parsings, then Jing DSP carry out FFT computings, then by PC104+ bus transfers to host computer, host computer can also pass through
Order and parameter are passed under PC104+ buses to DSP and FPGA.In this utility model, A/D chip sample rate reaches as high as 14bit/
400MSPS, and data processing is completed with FPGA+DSP frameworks, FPGA selects jumbo LX155 chips, has this utility model
There are the beneficial effects such as memory data output is big, disposal ability is strong, the market demand of present signal-processing board can be met.
Embodiment 2：
The present embodiment is the further improvement done on the basis of above-described embodiment, as depicted in figs. 1 and 2, in the present embodiment
In, the intermediate-freuqncy signal point two-way input A/D chip that SMA is accessed is directly output to FPGA all the way Jing after A/D chip, and another road is passed through
One front end Rhizoma Nelumbinis is input into A/D chip again after closing, front end Rhizoma Nelumbinis are closed including the first order transformator and second level transformator being sequentially connected,
First order transformator is converted to differential signal by single-ended signal for the intermediate-freuqncy signal for accessing SMA, and second level transformator is used for
The amplitude and the concordance of phase place at the positive and negative two ends of differential signal after first order transformator is changed are adjusted, second level transformator is adjusted
Signal after whole is input into A/D chip Jing after RC resistance-capacitance networks.It is used for FPGA without the signal all the way that front end Rhizoma Nelumbinis are closed and preserves A/D chip
Initial data, the premenstrual end Rhizoma Nelumbinis of intermediate-freuqncy signal reduce harmonic distortion after closing, are easy to FPGA to carry out dissection process.
The VCM voltages of A/D chip are internally lifted to signal on VCM level into after A/D chip by internal offer, signal
Go.A/D chip needs to simulate 5V, digital 3.3V and simulation tri- kinds of power supplys of 3.3V, and device total power consumption is in 2.5W or so.By PC104+
The 5V of bus gave A/D chip as simulation 5V power supplys, the numeral of digital 3.3V samplings imposite after entering a series of Filtering Processing
3.3V power supplys, simulate the analog power that 3.3V power supplys are that 5V power supplys carry out after LDO Power converts separately as A/D chip, the above
Power source design, can reduce interference of the power supply to A/D chip, provide clean working power to A/D chip, it is ensured that the property of A/D chip
Can reach good state.
The numeral output mode of ADC is LVDS parallel outputs, and the data form of output is Offset Binary.The number of ADC
Word output signal should be assigned to the same BANK of FPGA, and the level of the BANK need to be designed as 2.5V.
Embodiment 3：
The present embodiment is the further improvement done on the basis of above-described embodiment, as depicted in figs. 1 and 2, in the present embodiment
In, the plug-in two groups of DDR2 controllers of FPGA, DDR2 controllers capacity described in each group are 512MB, and data bit width is 16bits,
The ping-pong operation of two groups of DDR2 is held, DDR2 controllers are used for the initial data for caching A/D chip.FPGA selects LX155 chips,
DSP selects ADSP-TS201 chips, and SDRAM and FLASH is hung with outside DSP.SDRAM selects MT48LC32M16A2TG-75IT,
FLASH selects S29GL032N90TFI03.Data after FPGA parsings are transferred to DSP by EDMA modes, and DSP passes through PC104+
Bus is communicated with host computer.
Embodiment 4：
The present embodiment is the further improvement done on the basis of above-described embodiment, as shown in Figure 1, Figure 2 and Figure 3, in this reality
Apply in example, this utility model also includes Clock management module, Clock management module includes a 50MHz crystal oscillator and a 40MHz,
Wherein 50MHz crystal oscillators provide clock for A/D chip Jing after clock chip A, and 40MHz crystal oscillators are FPGA and DSP Jing after clock chip A
Clock is provided.Clk200M clocks are the data sync clock that exports after clock chip normal work, and the clock needs to be connected to FPGA
Global clock pin on, FPGA carries out the latch of A/D data by the data sync clock, due to output be 200MHz
Synchronised clock, need to carry out the latch of A/D data according to DDR simulations in FPGA, upper lower edge locks number simultaneously, so as to realize
The data transfer rate of 400Msps.
Should avoid from power supply particularly switching power supply parts passing through during clock cabling, will also avoid crossing from the middle of BGA（Even
Except being connected to the situation of BGA pins）, while live width and spacing of clock signal etc. should also meet 50 Europe resistance requirements.Clock is walked
The situation of acute angle should be avoided in line process, so as to reduce the secondary disturbances that its reflection brings.
Above-described specific embodiment, is entered to the purpose of this utility model, technical scheme and beneficial effect
One step is described in detail, be should be understood that to the foregoing is only specific embodiment of the present utility model, is not used to limit
Fixed protection domain of the present utility model, all any modifications within spirit of the present utility model and principle, made, equivalent are replaced
Change, improve, should be included within protection domain of the present utility model.
Claims (8)
1. a kind of acquisition process card device based on Large Copacity FPGA, it is characterised in that：It is including A/D chip, FPGA and DSP, described
A/D chip supports 14bit/400MSPS samplings, and A/D chip is for the intermediate-freuqncy signal that SMA is accessed is acquired and is changed, described
A/D chip is communicated with FPGA, is communicated between the FPGA and DSP, and the DSP is communicated with host computer, and the FPGA is LX155 cores
Piece, the FPGA are parsed for sending into data to A/D chip, and the data after parsing are transferred to DSP, and the DSP is used for
The data that FPGA sends into are carried out into FFT computings, and operation result packing is transferred to into host computer.
2. the acquisition process card device based on Large Copacity FPGA according to claim 1, it is characterised in that：The SMA connects
The intermediate-freuqncy signal for entering point two-way input A/D chip, is directly output to FPGA all the way Jing after A/D chip, and another road is through a front end
Rhizoma Nelumbinis are input into A/D chip again after closing, the front end Rhizoma Nelumbinis are closed including the first order transformator and second level transformator being sequentially connected, described
First order transformator is converted to differential signal, the second level transformator by single-ended signal for the intermediate-freuqncy signal for accessing SMA
The amplitude and the concordance of phase place at the positive and negative two ends of differential signal after change by first order transformator, second level transformation
Signal after device adjustment is input into A/D chip Jing after RC resistance-capacitance networks.
3. the acquisition process card device based on Large Copacity FPGA according to claim 1, it is characterised in that：Outside the FPGA
Two groups of DDR2 controllers are hung, DDR2 controllers capacity described in each group is 512MB, and data bit width is 16bits, support two groups
The ping-pong operation of DDR2, DDR2 controllers are used for the initial data for caching A/D chip.
4. the acquisition process card device based on Large Copacity FPGA according to claim 3, it is characterised in that：The DSP is
ADSP-TS201 chips, hang with SDRAM and FLASH outside the DSP.
5. the acquisition process card device based on Large Copacity FPGA according to claim 4, it is characterised in that：The SDRAM
Chip is MT48LC32M16A2TG-75IT, and the FLASH chip is S29GL032N90TFI03.
6. the acquisition process card device based on Large Copacity FPGA according to claim 4, it is characterised in that：The FPGA solutions
Data after analysis are transferred to DSP by EDMA modes.
7. the acquisition process card device based on Large Copacity FPGA according to claim 1, it is characterised in that：Also include clock
Management module, the Clock management module include a 50MHz crystal oscillator and a 40MHz, wherein 50MHz crystal oscillators Jing clock chips
Clock is provided for A/D chip after A, 40MHz crystal oscillators are that FPGA and DSP provide clock Jing after clock chip A.
8. the acquisition process card device based on Large Copacity FPGA according to claim 1, it is characterised in that：The DSP leads to
Cross PC104+ buses to communicate with host computer.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201620897831.8U CN206147623U (en) | 2016-08-18 | 2016-08-18 | Gather processing card device based on large capacity FPGA |
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| CN201620897831.8U CN206147623U (en) | 2016-08-18 | 2016-08-18 | Gather processing card device based on large capacity FPGA |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108280038A (en) * | 2017-12-07 | 2018-07-13 | 山东超越数控电子股份有限公司 | A kind of high-speed record board management system and method |
| CN112305961A (en) * | 2020-10-19 | 2021-02-02 | 武汉大学 | Novel signal detection and acquisition equipment |
| CN114578743A (en) * | 2022-05-06 | 2022-06-03 | 四川赛狄信息技术股份公司 | Ship-borne multi-channel signal acquisition synchronous control system based on FPGA |
-
2016
- 2016-08-18 CN CN201620897831.8U patent/CN206147623U/en active Active
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108280038A (en) * | 2017-12-07 | 2018-07-13 | 山东超越数控电子股份有限公司 | A kind of high-speed record board management system and method |
| CN108280038B (en) * | 2017-12-07 | 2021-05-07 | 山东超越数控电子股份有限公司 | High-speed recording board card management system and method |
| CN112305961A (en) * | 2020-10-19 | 2021-02-02 | 武汉大学 | Novel signal detection and acquisition equipment |
| CN114578743A (en) * | 2022-05-06 | 2022-06-03 | 四川赛狄信息技术股份公司 | Ship-borne multi-channel signal acquisition synchronous control system based on FPGA |
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Address after: The new West Road 610000 in Sichuan Province, Chengdu city high tech Development Zone No. 2 Patentee after: Sichuan Di Information Technology Co., Ltd. Address before: The new West Road 610000 in Sichuan Province, Chengdu city high tech Development Zone No. 2 Patentee before: Sichuan SDRising Information Technology Co., Ltd. |