CN113489594B

CN113489594B - PCIE real-time network card based on FPGA module

Info

Publication number: CN113489594B
Application number: CN202110623596.0A
Authority: CN
Inventors: 王峰
Original assignee: Beijing Avic Shuangxing Technology Co ltd
Current assignee: Beijing Avic Shuangxing Technology Co ltd
Priority date: 2021-06-04
Filing date: 2021-06-04
Publication date: 2023-12-19
Anticipated expiration: 2041-06-04
Also published as: CN113489594A

Abstract

The invention provides a PCI E real-time network card based on an FPGA module, which comprises: the ZYNQ module comprises an FPGA chip; the PHY chip is connected with the ZYNQ module, performs data interaction with the ZYNQ module through an MI I and/or RMI interface, and is connected with an external interface; and the PCI E bus is connected with the ZYNQ module and used for transmitting the received data to the ZYNQ module for processing. The ZYNQ module comprises an FPGA chip with an ARM core; the FPGA chip is connected with the host memory through the PCI E bus, and the FPGA chip and the host memory perform data interaction through the PCI E bus. The FPGA chip with ARM core is used for processing, so that the PCI E bus communication rate of the PCI E real-time network card breaks through the bottleneck, the communication rate is improved, and the PCI E bus communication rate has the advantage of high transmission rate.

Description

PCIE real-time network card based on FPGA module

Technical Field

The invention relates to a real-time network card technology, in particular to a PCIE real-time network card based on an FPGA module.

Background

With rapid development of computer network technology, many different types of real-time network cards, such as USB real-time network card, PCI real-time network card, PCIX real-time network card, PCIE real-time network card, etc., are appeared in order to meet the demands of various application environments and application levels, and the most popular type of real-time network card in the market is the gigabit PCIE real-time network card.

The general technical scheme of the gigabit PCIE real-time network card is to select an ethernet controller chip of the real-time network card, for example, a chip such as RTL81390D, which is commonly found in the market, and perform circuit design around a main control chip. The PCIE real-time network card designed by the scheme completely meets the standard of IEEE 802.3 on a physical layer and a data link layer, and after the PCIE real-time network card is accessed to a computer, the PCIE real-time network card serves as a physical connection between the computer and a network cable.

The real-time network card designed according to the common technical proposal has lower transmission rate although the real-time network card functionally meets the basic application of the Ethernet.

Disclosure of Invention

The PCIE real-time network card based on the FPGA module is processed based on the FPGA chip with the ARM core, so that the PCIE bus communication rate of the PCIE real-time network card breaks through the bottleneck, improves the communication rate, and has the advantage of high transmission rate.

In a first aspect of the embodiment of the present invention, a PCIE real-time network card based on an FPGA module is provided, including:

the ZYNQ module comprises an FPGA chip;

the PHY chip is connected with the ZYNQ module, performs data interaction with the ZYNQ module through MII and/or RMII interfaces, and is connected with an external interface;

and the PCIE bus is connected with the ZYNQ module and used for transmitting the received data to the ZYNQ module for processing.

Optionally, in a possible implementation manner of the first aspect, the ZYNQ module includes an FPGA chip with an ARM core;

the FPGA chip is connected with the host memory through the PCIE bus, and the FPGA chip and the host memory perform data interaction through the PCIE bus.

Optionally, in a possible implementation manner of the first aspect, the FPGA chip is connected to a clock circuit.

Optionally, in a possible implementation manner of the first aspect, the device further includes a double-rate synchronous dynamic random access memory, which is respectively connected with the ZYNQ modules, and is used for performing data interaction with the ZYNQ modules.

Optionally, in one possible implementation manner of the first aspect, any one or more of a pcie2 interface, a gigabit ethernet interface, a UART serial interface, an SD card interface, and a JTAG interface, which are respectively connected to the FPGA chip, are further included for data interaction.

Optionally, in a possible implementation manner of the first aspect, the synchronous dynamic random access memory includes two;

and an address line and a control line of the synchronous dynamic random access memory are respectively connected with the ZYNQ module.

Optionally, in one possible implementation manner of the first aspect, a data transmission connection manner of 16 bits of data is adopted between one of the synchronous dynamic random access memories and the ZYNQ module;

and the other synchronous dynamic random access memory and the ZYNQ module adopt a data transmission connection mode of low 16 bits of data.

Optionally, in a possible implementation manner of the first aspect, a QSPI FLASH chip is connected to the ZYNQ module, and the QSPI FLASH chip is used for starting and mirroring the ZYNQ module.

Optionally, in one possible implementation manner of the first aspect, the ZYNQ module is connected to an eMMC FLASH chip, and the eMMC FLASH chip is used for storing any one or more of an application program, a system file, and a data file.

Optionally, in a possible implementation manner of the first aspect, the clock circuit is configured to provide an active clock, and clock pulses are provided to the ARM core and the FPGA chip respectively;

the ARM core and the FPGA chip work respectively based on the received active clocks.

The PCIE real-time network card based on the FPGA module provided by the invention is processed based on the FPGA chip with the ARM core, so that the PCIE bus communication rate of the PCIE real-time network card breaks through the bottleneck, improves the communication rate, and has the advantage of high transmission rate.

According to the technical scheme, a real-time operating system is built by fully utilizing an ARM core provided by a hardware part, and the network transceiving of big data, real-time network communication and extremely high bandwidth utilization rate are realized by utilizing the logic control capability of ARM and the real-time characteristic of the operating system.

The technical scheme of the invention ensures that the PCIE can be fully used in the network transceiving of big data. According to the common technical scheme, the PCIE bus of the real-time network card is limited by a network communication protocol and the bandwidth of the network, and can only play the transmitting and receiving capacity of 1 Gb/s. According to the technical scheme, the ARM core with the real-time operating system is used, PCIE is managed through the ARM core, PCIE 2.0x4 performance of the technical scheme is fully utilized, and the peak rate of 20Gb/s can be achieved theoretically.

Drawings

Fig. 1 is a schematic structural diagram of a PCIE real-time network card based on an FPGA module;

fig. 2 is a schematic diagram of a connection structure between an FPGA and a host through a PCIE bus;

FIG. 3 is a schematic diagram of the overall scheme of a real-time network card based on ZYNQ implementation;

fig. 4 is a schematic structural diagram of a first embodiment of a real-time network card board;

fig. 5 is a schematic structural diagram of a second embodiment of a real-time network card board;

fig. 6 is a schematic diagram of a first embodiment of a PCIE real-time network card hardware structure based on an FPGA module;

fig. 7 is a schematic diagram of a second embodiment of a PCIE real-time network card hardware structure based on an FPGA module;

FIG. 8 is a schematic diagram of a ZYNQ module and/or a ZYNQ chip;

FIG. 9 is a schematic diagram of naming rules for ZYNQ modules and/or ZYNQ chips;

FIG. 10A is a schematic diagram showing a specific configuration of DDR\DDR3 DRAM;

FIG. 10B is a schematic diagram of the hardware connections of DDR\DDR3 DRAM;

FIG. 10C is a schematic diagram of DDR\DDR3 DRAM;

FIG. 10D is a schematic diagram of the pin assignment of DDR\DDR3 DRAM.

Fig. 11A is a schematic diagram showing a specific configuration of QSPI FLASH;

FIG. 11B is a schematic diagram of a hardware connection of QSPI FLASH;

fig. 11C is a schematic diagram of QSPI FLASH;

FIG. 11D is a pin assignment diagram of QSPI FLASH;

fig. 12A is a schematic diagram of a specific configuration of eMMC FLASH;

fig. 12B is a schematic diagram of a hardware connection mode of eMMC FLASH;

FIG. 12C is a schematic diagram of eMMC FLASH;

fig. 12D is a schematic diagram of pin assignment of eMMC FLASH;

FIG. 13A is a schematic diagram of a PS system clock source;

FIG. 13B is a pin assignment diagram of a PS system clock source;

FIG. 13C is a schematic diagram of a PL system clock source;

FIG. 13D is a pin assignment diagram of a PL system clock source;

FIG. 14A is a schematic diagram of a hardware connection of a USB-UART;

FIG. 14B is a schematic diagram of a USB-UART-to-serial interface;

FIG. 14C is a schematic diagram illustrating the pin assignment of the USB-UART to serial interface;

FIG. 15 is a schematic diagram of JTAG;

FIG. 16 is a diagram illustrating default setting information of a GPHY chip;

FIG. 17A is a schematic diagram of a hardware connection of a ZYNQ PS end 1-way Ethernet PHY chip;

FIG. 17B is a schematic diagram of a ZYNQ PS-side 1-way Ethernet PHY chip;

FIG. 17C is a schematic diagram of PS-side gigabit Ethernet pin assignment;

FIG. 17D is a ZYNQ PL end 1-way Ethernet PHY chip hardware connection;

FIG. 17E is a schematic diagram of a ZYNQ PL end 1-way Ethernet PHY chip;

FIG. 17F is a schematic diagram of PL-side gigabit Ethernet pin assignment;

FIG. 18A is a schematic diagram of a hardware connection of a PCIe interface;

FIG. 18B is a schematic diagram of a PCIe interface;

fig. 18C is a schematic diagram of pin assignment of a PCIE interface FPGA;

FIG. 19A is a schematic diagram of a hardware connection of Zynq7000PS and SD card connectors;

FIG. 19B is a schematic diagram of an SD card slot;

FIG. 19C is a diagram illustrating the allocation of SD card slot pins;

FIG. 20 is a schematic diagram of the RT-NET power supply principle;

fig. 21 is a size structure diagram of a PCIE real-time network card.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The terms "first," "second," "third," "fourth" and the like in the description and in the claims and in the above drawings, if any, are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein.

It should be understood that, in various embodiments of the present invention, the sequence number of each process does not mean that the execution sequence of each process should be determined by its functions and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

It should be understood that in the present invention, "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements that are expressly listed or inherent to such process, method, article, or apparatus.

It should be understood that in the present invention, "plurality" means two or more. "and/or" is merely an association relationship describing an association object, and means that three relationships may exist, for example, and/or B may mean: a exists alone, A and B exist together, and B exists alone. The character "/" generally indicates that the context-dependent object is an "or" relationship. "comprising A, B and C", "comprising A, B, C" means that all three of A, B, C comprise, "comprising A, B or C" means that one of the three comprises A, B, C, and "comprising A, B and/or C" means that any 1 or any 2 or 3 of the three comprises A, B, C.

It should be understood that in the present invention, "B corresponding to a", "a corresponding to B", or "B corresponding to a" means that B is associated with a, from which B can be determined. Determining B from a does not mean determining B from a alone, but may also determine B from a and/or other information. The matching of A and B is that the similarity of A and B is larger than or equal to a preset threshold value.

As used herein, "if" may be interpreted as "at … …" or "at … …" or "in response to a determination" or "in response to detection" depending on the context.

The technical scheme of the invention is described in detail below by specific examples. The following embodiments may be combined with each other, and some embodiments may not be repeated for the same or similar concepts or processes.

Word definitions of the invention

ZYNQ: an expandable processing chip;

PCIE: a high-speed serial computer expansion bus standard;

RMII: simplifying the media independent interface;

PHY: the physical layer is the lowest layer of OSI, and generally refers to a chip which is interfaced with external signals;

PS system: a processing system (Processing System) which is a processing part of the SOC of the ARM;

PL system: programmable logic (Progarmmable Logic), the processing portion of the FPGA;

DDR: synchronous dynamic random access memory.

The invention provides a PCIE real-time network card based on an FPGA module, which is shown in a structural schematic diagram in FIG. 1, and comprises an application layer, a link layer and a physical layer which are sequentially connected, wherein the PCIE real-time network card comprises:

at the link layer, the system comprises a ZYNQ module and an FPGA chip;

at least one PHY chip connected with the ZYNQ module is arranged on a physical layer, the PHY chip performs data interaction with the ZYNQ module through MII and/or RMII interfaces, and the PHY chip is connected with an external interface;

and the application layer is provided with a PCIE bus which is connected with the ZYNQ module and used for transmitting the received data to the ZYNQ module for processing.

The PHY chip interacts with the ZYNQ module through an MII/RMII interface to realize the functions of link control and communication. MII (Medium Independent Interface) is a media independent interface, and is responsible for communication connection between the PHY and the network controller. According to the scheme, the RMII (Reduced Medium Independent Interface) is adopted to realize communication connection between the PHY and the network controller, and the problem that the MII interface consumes more IO pin resources is solved.

The functions implemented by the data link layer include: and (3) grouping or unpacking the data frames transmitted by the physical layer and the main station core layer, controlling the receiving and transmitting sequence of the data frames, and detecting and recovering frame errors in the transmission process.

PCIE bus is a new serial point-to-point I/O bus system, which is a full duplex point-to-point technology, the number of buses is obviously reduced, and the differential transmission mode is adopted, so that the inter-line interference is greatly reduced, and the speed is up to 5.0Gb/s. The real-time network card of the bus can be used for adapting to the requirements of a network with higher speed and higher bandwidth, so PCIE is selected to realize the main control function and is responsible for realizing the bus communication management and control system software, including the functions of completing the protocol analysis, parameter configuration and maintenance, process data interaction, system diagnosis, human-computer interaction interface and the like of the RT-NET. As shown in fig. 2, the FPGA is connected to the host memory through a PCIE bus, so as to implement data interaction between the two. Wherein HOST in fig. 2 is the HOST.

The PHY chip functions to complete data encoding, decoding, and transceiving of the physical layer. The application of the Ethernet PHY chip in the RT-NET needs to meet some requirements: and a 1000Mbit/s full duplex link is supported, and the link loss response time of the chip is small.

The ZYNQ module comprises an FPGA chip with an ARM core; the FPGA chip is connected with the host memory through the PCIE bus, and the FPGA chip and the host memory perform data interaction through the PCIE bus. The FPGA chip with ARM core can also be ZYNQ chip. The ZYNQ module mainly realizes the functions of RT-NET data link control and communication. The ZYNQ chip processor chip of the ZYNQ module can adopt XC7Z015-2CLG485I of ZYNQ7000 series of xilinux company. The PS system of the ZYNQ chip integrates two ARM Cortex-A9 processors, AMBA interconnect, internal memory, external memory interface and peripherals. The FPGA of the ZYNQ chip contains rich programmable logic units, DSPs and internal ARM.

The general scheme of the real-time network card realized based on ZYNQ is shown in fig. 3, the host interacts with the ZYNQ module through PCIE, the ZYNQ module is connected with the PHY chip through the RMII interface, and the PHY chip is connected with the slave station through the network isolation transformer and the RJ45 interface. The host computer carries out interaction of data frames through the PCIE data bus and the ZYNQ module, the ZYNQ transmits the data frames to the PHY chip, the PHY chip converts the received RT-NET data frames into differential signals and sends the differential signals to the network, and each slave station returns the data frames to the master station after responding.

In one embodiment, the real-time network card board developed based on the technical solution provided by the present invention, as shown in fig. 4 and fig. 5, may have the following indexes, including:

power supply requirements: supplying power to a PCIe slot of the chassis;

a) Plate size: the PCB size is 140mm X60 mm, and the PCB and the size structure placement schematic diagram of the double-network-port real-time network card are shown in figures 1 and 2;

b) The fixed baffle needs to provide 2 sizes of half height and full height;

c) And (3) device type selection: all devices adopt industrial grade standards;

d) FPGA manufacturer: XC7Z015-2CLG485I from XILINX;

e) Other hardware specifications are shown in table 2 below;

f) The working temperature range of the product is as follows: -30-60 ℃;

main hardware parameters and interface indicators

The real-time network card single board mainly comprises a minimum system of ZYNQ7015+2 DDR3+eMMC+ QSPI FLASH, and is configured with rich peripheral interfaces, wherein the peripheral interfaces comprise 1 PCIEx2 interface, 2 gigabit Ethernet interface, 1 UART serial interface, 1 SD card interface and 1 JTAG interface.

The hardware structure of the technical scheme of the invention is shown in fig. 6 and 7.

The ZYNQ module and/or the ZYNQ chip provided by the invention can be shown in figure 8, the PS system of the chip integrates two ARM cortex TM-A9 processors,interconnect, internal memory, external memory interface, and peripherals. These peripherals mainly include USB bus interfaces, ethernet interfaces, SD/SDIO interfaces, I2C bus interfaces, CAN bus interfaces, UART interfaces, GPIO, and the like. The PS may operate independently and start up on power up or reset.

The main parameters of the PS system part are as follows:

application processor based on ARM dual-core cortex A9, ARM-v7 architecture, up to 766MHz

Based on CPU 32kb level 1 instruction and data cache, 512kb level 2 cache, 2 CPUs sharing

On-chip boot ROM and 256KB on-chip RAM

-external memory interface supporting a 16/32bit DDR2, DDR3 interface

-two gigabit real-time network card support: divergence-aggregation DMA, GMII, RGMII, SGMII interface

Two USB2.0 OTG interfaces, each supporting a maximum of 12 nodes

Two can2.0b bus interfaces

-two SD card, SDIO, MMC compatible controllers

-2 SPI,2 UARTs, 2I 2C interfaces

-4 sets of 32bit GPIO,54 (32+22) as PS system IO,64 connected to PL

High bandwidth connections in PS and PS to PL

Wherein the main parameters of the PL logic are as follows:

logic cell Logic Cells 76K

Look-up table LUTs 46200

-flip-flops): 92400

Multiplier 18x25maccs 160

-Block RAM：3.3Mb

-4-way high speed GTP transceiver supporting pcie gen2x2

-2 AD converters, which can measure on-chip voltage, temperature sensing and up to 17 external differential input channels, 1MBPS.

The speed rating of the ZYNQ chip is-2, industry level, packaged as BGA484, pin pitch of 0.8mm, as shown in FIG. 9.

The technical scheme of the invention is provided with two DDR3 SDRAM chips (1 GB in total), and the model is H5TQ4G63AFR-PBI. The bus width of DDR3 SDRAM is 32 bits in total. The highest operating speed of DDR3 SDRAM can reach 533MHz (data rate 1066 Mbps). The DDR3 memory system is directly connected to the memory interface of the BANK 502 of the ZYNQ Processing System (PS). The specific configuration of DDR3 SDRAM is shown in FIG. 10A.

The hardware design of DDR3 needs to strictly consider signal integrity, and matching resistance/terminal resistance, routing impedance control, routing equal length control are needed to be fully considered in the circuit design and PCB pair design, so that the high-speed stable operation of DDR3 is ensured. The hardware connection of the DDR3 DRAM is shown in FIG. 10B.

The schematic diagram of the DDR3 DRAM shown in FIG. 10C, the pin assignment diagram of the DDR3 DRAM shown in FIG. 10D.

The system also comprises double rate synchronous dynamic random access memories (DDR 3 DRAM and DDR), which are respectively connected with the ZYNQ module and used for carrying out data interaction with the ZYNQ module. The synchronous dynamic random access memory comprises two memories; and an address line and a control line of the synchronous dynamic random access memory are respectively connected with the ZYNQ module. One of the synchronous dynamic random access memories and the ZYNQ module adopt a data transmission connection mode of 16 bits of data; and the other synchronous dynamic random access memory and the ZYNQ module adopt a data transmission connection mode of low 16 bits of data.

The technical scheme of the invention is provided with a Quad-SPI Flash chip with the size of 256Mbit, the model is W25Q256FVEI, and the technical scheme uses a 3.3V CMOS voltage standard. Because of the nonvolatile nature of QSPI FLASH, in use, it can serve as a boot device for the system to store a boot image of the system. These images mainly include bit files of the FPGA, application code of the ARM, and other user data files. The specific model number and associated parameters of QSPI FLASH are shown in fig. 11A.

QSPI FLASH are connected to GPIO ports of PS part BANK500 of the ZYNQ chip, and the GPIO ports of these PS ends need to be configured to function as QSPI FLASH interfaces in the system design. The hardware connection of QSPI FLASH is shown in fig. 11B.

A schematic diagram of QSPI FLASH shown in fig. 11C, and a schematic diagram of chip pin assignment of QSPI FLASH shown in fig. 11D.

The technical scheme of the invention is provided with a large-capacity eMMC FLASH chip with the size of 8GB and the model of THGBMFG6C1LBAIL, which supports the JEDEC e-MMC V5.0 standard HS-MMC interface, and the level supports 1.8V or 3.3V. The data width of eMMC FLASH and ZYNQ connection is 4bit. Due to the high capacity and nonvolatile nature of eMMC FLASH, it can be used as a system high capacity storage device, such as storage applications, system files, and other user data files. The specific model and related parameters of eMMC FLASH are shown in fig. 12A.

The eMMC FLASH is connected to GPIO ports of PS part BANK501 of the ZYNQ chip, and in the system design, the GPIO ports of these PS ends need to be configured to be SD interfaces. The hardware connection mode of eMMC Flash is shown in fig. 12B.

Fig. 12C shows a schematic diagram of eMMC Flash, and fig. 12D shows a schematic diagram of chip pin assignment of eMMC Flash.

The technical proposal of the invention provides active clocks for the PS system and the PL logic part respectively, so that the PS system and the PL logic can work independently.

With respect to a PS system clock source, the ZYNQ chip provides 33.333MHz clock input for the PS part through an X1 crystal oscillator. The input of the clock is connected to the pin ps_clk_500 of the BANK500 of the ZYNQ chip, the principle of which is shown in fig. 13A.

The clock pin assignment of the PS system clock source is shown in fig. 13B.

The technical scheme of the invention provides a single-ended 50MHz PL system clock source and 3.3V power supply. The crystal outputs are connected to the global clock (MRCC) of the FPGA BANK13, which GCLK can be used to drive the user logic circuits within the FPGA, the principle of which is shown in FIG. 13C.

The clock pin assignment of the PL system clock source is shown in FIG. 13D.

The technical scheme of the invention is provided with a UART-USB interface for debugging. The conversion chip adopts a USB-UART chip of a Silicon Labs CP2102GM, the USB interface adopts a MINI USB interface, and the conversion chip can be connected to a USB interface of a PC by a USB wire to carry out serial data communication of the core board. The hardware connection manner of the USB to serial port is shown in fig. 14A.

The principle of USB to serial is shown in fig. 14B. The ZYNQ pin assignment for UART-to-serial port is shown in fig. 14C.

The technical scheme of the invention reserves an interface of JTAG, which is used for downloading the FPGA program or solidifying the program to FLASH. In order to prevent the damage to the FPGA chip caused by hot plugging, a protection diode is added on JTAG signals to ensure that the voltage of the signals is in the range accepted by the FPGA, so that the damage to the FPGA is avoided. The principle is shown in fig. 15.

In one embodiment, the technical scheme of the invention has a 2-way gigabit Ethernet interface, wherein a 1-way Ethernet interface is a connected PS system end, and the other 1-way Ethernet interface is connected to a logic IO port of the PL. The gigabit ethernet interface connected to PL needs to be installed on the AXI bus system of ZYNQ by program call IP.

The ethernet chip provides network communication services using a KSZ9031RNX ethernet PHY chip from Micrel corporation. The ethernet PHY chip at the PS end is connected to the GPIO interface of the BANK501 at the PS end of ZYNQ. The Ethernet PHY chip at the PL terminal is connected to IO of the BANK 35. The KSZ9031RNX chip supports 10/100/1000Mbps network transmission rate, and performs data communication with the MAC layer of the Zynq7000 system through the RGMII interface. KSZ9031RNX supports MDI/MDX adaptation, various speed adaptation, master/Slave adaptation, and register management of the PHY by the MDIO bus.

The KSZ9031RNX power up will detect the level state of some specific IOs to determine its own mode of operation. Default setting information after the GPHY chip is powered up as shown in fig. 16.

When the network is connected to the gigabit ethernet, the ZYNQ and the PHY chip KSZ9031RNX communicate via the RGMII bus during data transmission, the transmission clock is 125Mhz, and the data is sampled on the rising edge and the falling edge of the clock.

When the network is connected to the hundred megaethernet, the ZYNQ and the PHY chip KSZ9031RNX communicate via the RMII bus during data transmission, with a transmission clock of 25Mhz. The data is sampled on the rising and falling edges of the clock.

The hardware connection mode of the ZYNQ PS end 1-path Ethernet PHY chip is shown in FIG. 17A. As shown in fig. 17B, the schematic diagram of the 1-path ethernet PHY chip at the ZYNQ PS end. A schematic diagram of PS-side gigabit ethernet pin assignment is shown in fig. 17C.

The hardware connection mode of the ZYNQ PL end 1-path Ethernet PHY chip is shown in figure 17D. As shown in fig. 17E, the schematic diagram of the 1-channel ethernet PHY chip at the ZYNQ PL end. A schematic diagram of PL-side gigabit ethernet pin assignment is shown in fig. 17F.

The technical scheme of the invention provides an industrial-level high-speed data transmission PCIe x4 interface, the external dimension of the PCIE card meets the electrical specification requirement of the PCIE card, and the PCIE card can be directly used on a PCIe slot of a common desktop.

The receiving and transmitting signals of the PCIe interface are directly connected with a GTP transceiver of the FPGA, and the TX signals and the RX signals of the 2 channels are connected to the FPGA in a differential signal mode, so that the single-channel communication rate can reach 5G bit bandwidth. The PCIe reference clock is provided to the development board by the PCIe slot of the computer, and the reference clock frequency is 100MHz.

The hardware connection mode of the PCIe interface according to the technical solution of the present invention is shown in fig. 18A, where the TX transmit signal and the reference clock CLK signal are connected in an AC coupling mode. PCIe x4 interface schematic as shown in fig. 18B. Fig. 18C shows a schematic diagram of pin assignment of PCIE x4 interface FPGA.

The technical scheme of the invention comprises a Micro SD card interface to provide the function of accessing the SD card memory, and the SD card interface is used for storing BOOT programs of the ZYNQ chip, a Linux operating system kernel, a file system and other user data files.

The SDIO signal is connected to the IO signal of the PS BANK501 of ZYNQ because VCCMIO of the BANK is set to 1.8V, but the data level of the SD card is 3.3V, which is connected through a TXS02612 level shifter. The hardware connection of the Zynq7000PS and SD card connectors is shown in fig. 19A.

Fig. 19B shows a schematic diagram of SD card slot. Fig. 19C shows a diagram of SD card slot pin assignment.

The power supply input voltage of the technical scheme is DC12V, and power is supplied through PCIE. The real-time network card board is converted into four paths of power supplies of +5V, +1.2V, +3.3V and 1.8V by a 1 path of DC/DC power supply chip MP2303 and a 3 path of DC/DC power supply chip MP 1482. The RT-NET power supply principle is shown in figure 20.

The size structure diagram of the PCIE real-time network card according to the technical solution of the present invention is shown in fig. 21.

The readable storage medium may be a computer storage medium or a communication medium. Communication media includes any medium that facilitates transfer of a computer program from one place to another. Computer storage media can be any available media that can be accessed by a general purpose or special purpose computer. For example, a readable storage medium is coupled to the processor such that the processor can read information from, and write information to, the readable storage medium. In the alternative, the readable storage medium may be integral to the processor. The processor and the readable storage medium may reside in an application specific integrated circuit (Application Specific Integrated Circuits, ASIC for short). In addition, the ASIC may reside in a user device. The processor and the readable storage medium may reside as discrete components in a communication device. The readable storage medium may be read-only memory (ROM), random-access memory (RAM), CD-ROMs, magnetic tape, floppy disk, optical data storage device, etc.

The present invention also provides a program product comprising execution instructions stored in a readable storage medium. The at least one processor of the device may read the execution instructions from the readable storage medium, the execution instructions being executed by the at least one processor to cause the device to implement the methods provided by the various embodiments described above.

In the above embodiments of the terminal or the server, it should be understood that the processor may be a central processing unit (english: central Processing Unit, abbreviated as CPU), or may be other general purpose processors, digital signal processors (english: digital Signal Processor, abbreviated as DSP), application specific integrated circuits (english: application Specific Integrated Circuit, abbreviated as ASIC), or the like. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. The steps of a method disclosed in connection with the present invention may be embodied directly in a hardware processor for execution, or in a combination of hardware and software modules in a processor for execution.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. PCIE real-time network card based on FPGA module, characterized by comprising:

the ZYNQ module comprises an FPGA chip;

PCIE bus, connect with said ZYNQ module, is used for transmitting the data received to the said ZYNQ module and dealing with;

the ZYNQ module comprises an FPGA chip with an ARM core;

the FPGA chip is connected with a host memory through the PCIE bus, and the FPGA chip and the host memory perform data interaction through the PCIE bus;

the PS system of the ZYNQ module integrates two ARM Cortex-A9 processors, an AMBA interconnection, an internal memory, an external memory interface and a peripheral; the peripheral equipment comprises a USB bus interface, an Ethernet interface, an SD/SDIO interface, an I2C bus interface, a CAN bus interface, a UART interface and a GPIO;

the PCIE data bus and the ZYNQ module are used for carrying out interaction of data frames, the ZYNQ module transmits the data frames to the PHY chip, the PHY chip converts the received RT-NET data frames into differential signals and sends the differential signals to a network, and each slave station returns the data frames to the master station after responding;

the double-rate synchronous dynamic random access memory is respectively connected with the ZYNQ module and used for carrying out data interaction with the ZYNQ module; the synchronous dynamic random access memory comprises two memories; the address line and the control line of the synchronous dynamic random access memory are respectively connected with the ZYNQ module; one of the synchronous dynamic random access memories and the ZYNQ module adopt a data transmission connection mode of 16 bits of data; the other synchronous dynamic random access memory and the ZYNQ module adopt a data transmission connection mode of data with low 16 bits;

the system also comprises one or more of a PCIEx2 interface, a gigabit Ethernet interface, a UART serial interface, an SD card interface and a JTAG interface which are respectively connected with the FPGA chip, and the PCIEx2 interface, the gigabit Ethernet interface, the UART serial interface, the SD card interface and the JTAG interface are used for data interaction;

the ZYNQ module is connected with a QSPI FLASH chip, and the QSPI FLASH chip is used for starting the ZYNQ module and starting a mirror image;

the ZYNQ module is connected with an eMMC FLASH chip, and the eMMC FLASH chip is used for storing any one or more of an application program, a system file and a data file;

the clock circuit is used for providing an active clock and respectively providing clock pulses for the ARM core and the FPGA chip;

the ARM core and the FPGA chip work respectively based on the received active clocks;

the host computer interacts with the ZYNQ module through PCIE, the ZYNQ module is connected with the PHY chip through the RMII interface, and the PHY chip is connected with the slave station through the network isolation transformer and the RJ45 interface access bus; the host computer carries out interaction of data frames through the PCIE data bus and the ZYNQ module, the ZYNQ transmits the data frames to the PHY chip, the PHY chip converts the received RT-NET data frames into differential signals and sends the differential signals to the network, and each slave station returns the data frames to the master station after responding;

active clocks are respectively provided for the PS system and the PL logic part, so that the PS system and the PL logic can work independently;

regarding a PS system clock source, the ZYNQ chip provides 33.333MHz clock input for the PS part through an X1 crystal oscillator; the input of the clock is connected to the pin ps_clk_500 of the BANK500 of the ZYNQ chip.

2. The FPGA module-based PCIE real-time network card of claim 1 wherein,

the FPGA chip is connected with the clock circuit.

3. The FPGA module-based PCIE real-time network card of claim 1 wherein,

the double-rate synchronous dynamic random access memory is respectively connected with the ZYNQ module and used for carrying out data interaction with the ZYNQ module.

4. The PCIE real-time network card based on FPGA module as defined in claim 3 wherein,

the synchronous dynamic random access memory comprises two memories;

5. The FPGA module-based PCIE real-time network card of claim 4 wherein,

one of the synchronous dynamic random access memories and the ZYNQ module adopt a data transmission connection mode of 16 bits of data;