CN212256301U

CN212256301U - Embedded mainboard based on intel Whiskey lake

Info

Publication number: CN212256301U
Application number: CN202021223305.6U
Authority: CN
Inventors: 程文伟; 程加钢
Original assignee: Shenzhen Jhctech Development Co ltd
Current assignee: Shenzhen Jhctech Development Co ltd
Priority date: 2020-06-28
Filing date: 2020-06-28
Publication date: 2020-12-29
Anticipated expiration: 2030-06-28

Abstract

The utility model provides an embedded mainboard based on intel Whiskey lake belongs to the mainboard structure field. The utility model discloses an adopt intel Whiskey lake's processor module, power module, M.2 interface module and independent interface module, wherein, processor module links to each other with M.2 interface module and independent interface module respectively, power module links to each other with processor module's power chip, for the power supply of whole mainboard. The utility model has the advantages that: the I/O interface with more complete functions supports 2 display interfaces, 6 USB interfaces, mSATA, M.2, double-channel DDR4 and other interfaces on a 3.5-inch mainboard.

Description

Embedded mainboard based on intel Whiskey lake

Technical Field

The utility model relates to a mainboard structure especially relates to an embedded mainboard based on intel Whiskey lake.

Background

The Intel Whiskey Lake platform is an Intel eighth generation core applied to the Internet of things

Processor families, real-time computing for applications such as digital surveillance assistance, advances in industrial and office automation, retail and new medical solutions, etc. As a new-generation processor, the Whisskey lake platform can better meet the requirement of industrial application sites on real-time performance. And 4 cores are supported, the low-power-consumption design is supported, and meanwhile, the strong performance is provided, so that an excellent platform is provided for intelligent solution development.

At present, a mainboard based on an Intel Whiskey lake platform is designed and used in the industrial control industry, the application of each manufacturer is different, and the size of the designed mainboard is different; who can design the function complete, the size accords with the requirement and the scheme that has the price/performance ratio most will have bigger competitiveness, to the higher industry thing networking scene of real-time requirement, Intel Whiskey lake platform will exert bigger advantage.

SUMMERY OF THE UTILITY MODEL

For solving the problem among the prior art, the utility model provides an embedded mainboard based on intel Whiskey lake.

The utility model discloses an adopt intel Whiskey lake's processor module, power module, M.2 interface module and independent interface module, wherein, processor module links to each other with M.2 interface module and independent interface module respectively, power module links to each other with processor module's power chip, for the power supply of whole mainboard.

The utility model discloses make further improvement, power module adopts SKYLAKE-U platform's ISL95857 series's power chip U89.

The utility model discloses do further improvement, power chip U89's pin 32 passes through resistance R543 ground connection, and pin 31 passes through resistance R544 ground connection, power chip U89's pin 38 is voltage output pin + VCCST, power chip U89's pin 38 is voltage output pin + VCCST, power chip U89's pin 5 is voltage output pin + VCCCORE, power chip U89's pin 25 is voltage output pin + VCCSA, configures through configuring resistance R543 and resistance R544 power module's three voltage output pin's power output value.

The utility model discloses make further improvement, pin 21 of power chip U89 links to each other with pin 7 of power chip U91 of treater, pin 22 of power chip U89 links to each other with pin 3 of power chip U91 of treater;

a pin 11 of the power supply chip U89 is respectively connected with a pin 7 of a power supply chip U87 of the processor and a pin 7 of the power supply chip U198, a pin 12 of the power supply chip U89 is connected with a pin 3 of a power supply chip U87 of the processor, and a pin 13 of the power supply chip U89 is connected with a pin 3 of the power supply chip U198 of the processor;

the pin 29 of the power chip U89 is connected to the pin 7 of the power chip U38 of the processor, and the pin 30 of the power chip U38 is connected to the pin 3 of the power chip U38 of the processor.

The utility model discloses make further improvement, power chip U89 is close to treater power chip sets up, power chip U89 is connected the corresponding pin setting of the power chip that the pin is close to with the power chip of treater.

The utility model discloses make further improvement, M.2 interface module compatible multiple bus, the bus includes PCIe, USB2.0 and CNVi bus.

The utility model discloses make further improvement, still include EIO daughter card, EIO daughter card links to each other with processor module.

The utility model discloses make further improvement, the EIO daughter card is equipped with the SATA interface, wherein, the EIO daughter card includes the EIO chip,

82 and 83 of EIO chip are SATA signal reception pin,

23 and 24 of EIO chip are SATA signal's transmission pin.

The utility model discloses make further improvement, the EIO chip still is equipped with GPIO, PCIe, CLK, USB, DDI2 interface that links to each other with the EIO chip.

The utility model discloses make further improvement, still include passageway A memory and passageway B memory that link to each other with the processor module, mSATA interface, BIOS module, independent interface module includes power source, HDMI interface, USB2.0, USB3.1 interface, the LAN interface that links to each other with the processor.

Compared with the prior art, the beneficial effects of the utility model are that: the I/O interface with more complete functions integrates an M.2 interface module on the basis of the existing independent interface for realizing corresponding functions, and supports 2 display interfaces, 6 USB interfaces, mSATA, M.2, double-channel DDR4 and other interfaces on a 3.5-inch mainboard; an EIO bus interface which accords with JHCECH specification is reserved, and ODM customization is facilitated.

Drawings

FIG. 1 is a block diagram of the present invention;

FIG. 2 is a schematic diagram of a power module circuit;

FIG. 3 is a power chip circuit schematic of a processor;

FIG. 4 is a schematic diagram of an EIO daughter board circuit;

fig. 5 is a schematic circuit diagram of an m.2 interface module.

Detailed Description

The present invention will be described in further detail with reference to the accompanying drawings and examples.

As shown in fig. 1, the utility model discloses an adopt intel Whiskey lake's processor module, power module, M.2 interface module and independent interface module, wherein, processor module links to each other with M.2 interface module and independent interface module respectively, power module links to each other with processor module's power chip, for the power supply of whole mainboard.

The main board of the embodiment also integrates a channel A memory, a channel B memory, a mSATA interface and a BIOS module which are connected with the processor module, wherein the channel A memory of the embodiment is an onboard memory, and the channel B memory of the embodiment is a card slot and supports memory banks. The dual-channel memory is compatible with various memory designs on the basis of meeting performance requirements, and is better in stability.

The independent interface module of the embodiment comprises a power interface, an HDMI interface, a USB2.0 interface, a USB3.1 interface and a LAN interface which are connected with the processor. A power-on mode selection switch and a CMOS data cleaning switch are arranged on a coastline, so that the coastline can be conveniently set by a customer on site; and the arrangement of the CPU temperature indicating lamp on the coastline is convenient for a user to monitor the working state of the machine.

In addition, the present embodiment is further provided with an EIO daughter board, which reserves an EIO bus interface conforming to the JHCTECH specification, and facilitates the customization of ODM (Original Design Manufacturer). The EIO is an Ethernet device which simultaneously integrates I/O control and an RS232/RS485 serial server, simultaneously has the functions of switching value output, switching value acquisition, a serial server and the like, and can simultaneously replace an I/O card and the serial server. And two user communication interfaces of Socket and virtual serial port are simultaneously supported, and a user can communicate with the EIO through TCP/IP connection according to the Socket standard. The EIO can also be virtualized into common serial port equipment through VSPM virtual serial port software, and the software compiling difficulty can be effectively reduced. The EIO adopts international Modbus TCP as a communication protocol and can be seamlessly combined with various configuration software. Compared with the traditional computer + I/O control card structure, the structure has more functions and more stable work.

In this example, an I/O interface with more complete functions is designed with such a small size of 146mmX101mm, and an m.2 interface module is integrated on the basis of an existing independent interface for realizing corresponding functions, and 2 display interfaces, 6 USB interfaces, mSATA, m.2, dual-channel DDR4 and other interfaces are supported on a 3.5-inch motherboard.

As shown in fig. 2 and 3, the power supply module of this example is compatible with the power supply chip of the Whiskey lake processor by using the power supply chip U89 of the ISL95857 series of the SKYLAKE-U platform.

The pin 32 of the power chip U89 is grounded through a resistor R543, the pin 31 is grounded through a resistor R544, the pin 38 of the power chip U89 is a voltage output pin + VCCST, the pin 38 of the power chip U89 is a voltage output pin + VCCST, the pin 5 of the power chip U89 is a voltage output pin + VCCCORE, the pin 25 of the power chip U89 is a voltage output pin + VCCSA, and power output values of three voltage output pins of the power module are configured by configuring resistance values of the resistor R543 and the resistor R544.

The pin 21 of the power chip U89 is connected with the pin 7 of the power chip U91 of the processor, and the pin 22 of the power chip U89 is connected with the pin 3 of the power chip U91 of the processor; a pin 11 of the power supply chip U89 is respectively connected with a pin 7 of a power supply chip U87 of the processor and a pin 7 of the power supply chip U198, a pin 12 of the power supply chip U89 is connected with a pin 3 of a power supply chip U87 of the processor, and a pin 13 of the power supply chip U89 is connected with a pin 3 of the power supply chip U198 of the processor; the pin 29 of the power chip U89 is connected to the pin 7 of the power chip U38 of the processor, and the pin 30 of the power chip U38 is connected to the pin 3 of the power chip U38 of the processor.

The configuration VR of this example by configuring the resistance values of the pins 31PROG2 and 32PROG1 is shown in tables 1 and 2:

TABLE 1

TABLE 2

From the table, it is known that VR a is supplying + VCCGT, single phase max 35a.vr B is supplying + VCCCORE, two phase power, max 70A, VR C is supplying + VCCSA, and max 10A is required.

Wherein the DC load line of + VCCCORE is 1.8m Ω; the AC load line is 1.8m Ω; IccMax10mS maximum current is 70A; the thermal design current must be maintained at 48A; the TDP (maximum thermal power consumption) of the processor is usually 15W;

the DC load line of + VCCGT is 3.1m Ω; the AC load line is 3.1m omega; IccMax10mS maximum current of 31A; the thermal design current must be maintained at 18A; typically the TDP of a processor is 15W;

the DC load line for the + VCCSA is 10.3m Ω; the AC load line is 10.3m omega; IccMax10mS maximum current is 6A; the thermal design current is maintained at 4A; typically the TDP of a processor is 15W.

In addition, the power module of the embodiment is reasonably arranged and wired to meet the requirements of power supply technical parameters. Specifically, the driving paths of the power chip U87 and each of the power chips ISL95808 and NTMFS4C05N of the processor are as short as possible, the MLCC at the end of the CPU is as close to the pin of the power supply pin of the CPU as possible, the feedback loop is as short as possible, and the number of VIAs of GND is sufficient to satisfy the transient response of the large current of the power supply. Thus, the power chip U89 of this example is located next to the processor power chip, with the power chip U89 located near the power chip connection pins of the processor.

As shown in fig. 5, the m.2 interface module of this example is a new host interface scheme, and can be compatible with multiple communication protocols, and the module is compatible with multiple buses, including PCIe, USB, CNVi buses, and the like.

In the example, signals USB _ P10 and USB _ N10 of USB2.0 are led to an M.2 interface; PCIE _ M2_ RX1-, PCIE _ M2_ RX1+, PCIE _ M2_ TX1-, CIE _ M2_ TX1+ of PCIE3.0 are led to the M.2 interface; signals CNV _ WR _ D1_ DN, CNV _ WR _ D1_ DP, CNV _ WR _ DO _ DN, CNV _ WR _ DO _ DP, CNV _ WR _ CLK _ DN, CNV _ WR _ CLK _ DP, CNV _ WT _ D1_ DN, CNV _ WT _ D1_ DP, CNV _ WT _ DO _ DN, CNV _ WT _ DO _ DP, CNV _ WT _ CLK _ DN, CNV _ WT _ CLK _ DP are introduced to the m.2 interface. Meanwhile, the power-on time sequence of the CNVi is set in the embodiment, so that the CNVi can be used normally.

As shown in fig. 4, the EIO daughter card of this example is provided with a SATA interface, where the EIO daughter card includes an EIO chip,

pins

82 and 83 of the EIO chip are SATA signal receiving pins, and

pins

23 and 24 of the EIO chip are SATA signal sending pins. The EIO chip is also provided with GPIO, PCIe, CLK, USB and DDI2 interfaces connected with the EIO chip.

This example guarantees SATA3.0 bandwidth (6Gb/s) by introducing the SATA interface to the design on the EIO daughter card. Since SATA3.0 signals are asynchronous sensitive signals, SATA3.0 is required to be routed 2 Vias: 2000mil to 8000mil or 3 Vias: 2000mil-7007.87 mil. The SATA signal of this example is guided to the daughter card through a high speed carrier, with a minimum of 4 VIAS, and a length of 2000 mils, which is more than 8000 mils. The wiring of the embodiment is far away from an easily interfered source, a power supply, a clock and the like as far as possible, and meanwhile, the wiring is short as far as possible, so that the performance of the product is more stable and reliable.

The utility model discloses a to the research design of the embedded mainboard scheme of 3.5 inches of Intel Whiskey lake standard, this kind of mainboard can sell as the veneer, also can adorn and use on the panel computer or the box computer. The platform product can play a greater advantage in the application of the industrial Internet of things, not only enriches the product line of the department of China, but also improves the market competitiveness of the product of the department of China; meanwhile, the method has a positive promoting effect on the development of the industrial Internet of things.

The project can successfully realize the research and design of the scheme of the 3.5-inch embedded mainboard of the Intel Whiskey lake standard, and realizes double-channel DDR4 slots, double display, double gigabit network ports, 2 USB3.1 and M.2E-Key expansion and the like in the limited space of the 3.5-inch mainboard, so that the volume is small, and the functions are complete. At present, the method has wide application scenes in the fields of industrial Internet of things with higher real-time requirements, machine vision and artificial intelligence.

The above-mentioned embodiments are the preferred embodiments of the present invention, and the scope of the present invention is not limited to the above-mentioned embodiments, and the scope of the present invention includes and is not limited to the above-mentioned embodiments, and all equivalent changes made according to the present invention are within the protection scope of the present invention.

Claims

1. An embedded mainboard based on intel Whiskey lake, its characterized in that: the intelligent mainboard comprises a processor module, a power supply module, an M.2 interface module and an independent interface module, wherein the processor module adopts an Intel Whiskey lake, the processor module is respectively connected with the M.2 interface module and the independent interface module, and the power supply module is connected with a power supply chip of the processor module and supplies power for the whole mainboard.

2. The intel Whiskey lake based embedded motherboard of claim 1, wherein: the power supply module adopts an ISL95857 series power supply chip U89 of SKYLAKE-U platform.

3. The intel Whiskey lake based embedded motherboard of claim 2, wherein: the pin 32 of the power chip U89 is grounded through a resistor R543, the pin 31 is grounded through a resistor R544, the pin 38 of the power chip U89 is a voltage output pin + VCCST, the pin 38 of the power chip U89 is a voltage output pin + VCCST, the pin 5 of the power chip U89 is a voltage output pin + VCCCORE, the pin 25 of the power chip U89 is a voltage output pin + VCCSA, and power output values of three voltage output pins of the power module are configured by configuring resistance values of the resistor R543 and the resistor R544.

4. The intel Whiskey lake based embedded motherboard of claim 3, wherein: the pin 21 of the power chip U89 is connected with the pin 7 of the power chip U91 of the processor, and the pin 22 of the power chip U89 is connected with the pin 3 of the power chip U91 of the processor;

5. The intel Whiskey lake based embedded motherboard of claim 4, wherein: the power chip U89 is arranged next to the processor power chip, and the power chip U89 is arranged close to the corresponding pin of the power chip near the power chip connecting pin of the processor.

6. The intel Whiskey lake based embedded motherboard of claim 1, wherein: the M.2 interface module is compatible with various buses, and the buses comprise PCIe buses, USB2.0 buses and CNVi buses.

7. The intel Whiskey lake based embedded motherboard of any of claims 1-6, wherein: the system further comprises an EIO sub-card, and the EIO sub-card is connected with the processor module.

8. The intel Whiskey lake based embedded motherboard of claim 7, wherein: the EIO daughter card is provided with a SATA interface, wherein the EIO daughter card comprises an EIO chip, pins 82 and 83 of the EIO chip are SATA signal receiving pins, and pins 23 and 24 of the EIO chip are SATA signal sending pins.

9. The intel Whiskey lake based embedded motherboard of claim 7, wherein: the EIO chip is also provided with GPIO, PCIe, CLK, USB and DDI2 interfaces connected with the EIO chip.

10. The intel Whiskey lake based embedded motherboard of any of claims 1-6, wherein: the system also comprises a channel A memory and a channel B memory which are connected with the processor module, an mSATA interface and a BIOS module, wherein the independent interface module comprises a power interface, an HDMI interface, a USB2.0 interface, a USB3.1 interface and a LAN interface which are connected with the processor.