CN103616934A

CN103616934A - FPGA core circuit board structure

Info

Publication number: CN103616934A
Application number: CN201310649296.5A
Authority: CN
Inventors: 柴志雷; 阳文敏; 王芝斌; 丁帅
Original assignee: Jiangnan University
Current assignee: Jiangnan University
Priority date: 2013-12-06
Filing date: 2013-12-06
Publication date: 2014-03-05

Abstract

The invention belongs to the field of embedded type core circuit boards, and relates to the field of computer hardware, in particular to an FPGA core circuit board structure. The problems of an existing core board or an existing processing platform are effectively solved, and the characteristic that an FPGA chip can be programmed and the advantage of processing the parallelism of data especially mass data are brought into full play. The FPGA core circuit board structure comprises a circuit board and is characterized in that the FPGA chip is arranged on the circuit board, and a plurality of DDR3 chips, a Flash chip, crystal oscillator chips, an electrical level conversion chip and sockets are connected with the FPGA chip and arranged at the positions, surrounding the FPGA chip, of the circuit board.

Description

A kind of fpga core board structure of circuit

Technical field

The present invention relates to computer hardware field, belong to embedded core circuit plate field, be specially a kind of fpga core board structure of circuit.

Background technology

Along with society and scientific and technical development, people are larger for the demand of data volume and quantity of information, the arrival of large data age, and for the needs of high speed high-definition image video, we more and more find that traditional data processing and image processing platform can not meet people far away for the processing speed of data and the demand of image effect, even if having now core board deal with data and image based on DSP and GPU, but its poor expandability and expensive, cause cost performance low, be not well positioned to meet people's demand.

Summary of the invention

In order to overcome the above problems, meet people for the demand of data processing speed and extensibility, the invention provides a kind of fpga core board structure of circuit, effectively solve the problem existing in existing core board or processing platform, fully played the programmable feature of fpga chip and to the data advantage that particularly concurrency of large data is processed.

Its technical scheme is such: it comprises circuit board, it is characterized in that, on described circuit board, fpga chip is set, on described fpga chip described circuit board around, the multi-disc DDR3 chip being connected is set, Flash chip, crystal oscillator chip with described fpga chip, level transferring chip, socket.

It is further characterized in that, connects four described DDR3 chips around described fpga chip;

Described fpga chip connects three described crystal oscillator chips, two single-end user's clocks that described crystal oscillator chip is 100MHz wherein, the system differential clocks that crystal oscillator chip is 100M described in a slice;

Described fpga chip connects five groups of wire jumpers, and described in five groups, wire jumper comprises that control wire jumper is put in four assembly and one group of pin is controlled wire jumper, and described in four groups, four Switch switches of wire jumper connection are controlled in configuration;

Described fpga chip connects Debug/JATG interface and ten LED display lamps;

Described FPGA connects the described socket of three row 50x2;

Described fpga chip is Spartan-6 XC6SLX150T.

Adopt after structure of the present invention, adopt multi-disc DDR3 as stored memory, reading out data can walk abreast simultaneously, data throughout is large, the problem of having determined and having existed in existing core board or processing platform, integrated circuit structure is enriched perfect, can independently use, can use in conjunction with other core boards or platform extension again, fully play the programmable feature of fpga chip and to the data advantage that particularly concurrency of large data is processed.

Accompanying drawing explanation

Fig. 1 is fpga core board structure of circuit schematic diagram of the present invention.

Embodiment

As shown in fig. 1, a kind of fpga core board structure of circuit, it comprises circuit board, and fpga chip is set on circuit board, four DDR3 chips, Flash chip, three crystal oscillator chips, level transferring chip, Debug/JATG interface, five groups of wire jumpers, a four way switch, LED display lamp, three row 50x2 sockets, fpga chip model is Spartan-6 XC6SLX150T, is encapsulated as FGG676, and chip internal programmable resource and IO pin are many, and price is not high, and cost performance is higher, fpga chip around connects DDR3 that four capacity are 1Gb as stored memory, every DDR3 internal memory adopts 15 address wires to input as address, 16 data lines are exported as data, 14 control signal wires, four DDR3 reading out data that can simultaneously walk abreast, data throughout is large, bandwidth is high, DDR3 has higher external transfer rate and advanced address/command and the topological structure of control bus, adopt DDR3 internal memory can on the basis of controlling cost, reduce power consumption and thermal value, versatility compatibility is relatively good, and frequency of operation is also higher, the pre-stored bit stream configuration file of Flash chip, under FPGA active arrangement pattern, connects after power supply, by self initializing program, the file configuration in Flash is entered to FPGA, makes FPGA work, realizes corresponding function, single-end user's clock that in three crystal oscillator chips two are 100MHz, by pin FPGA_CLK0 and FPGA_CLK1, export to user, a slice crystal oscillator chip is SI500D in addition, for FPGA system provides the differential clocks of 100MHz, by pin SYSCLK_N and SYSCLK_P, export to system and drive as clock, and to adopt ultralow shake crystal clock generator CDCM61002 be MGT(Multi-Gigabit Transceiver) differential clock signal is provided, level transferring chip adopts PTH08T230W module, it can meet circuit board power demands and the low electromagnetic interference (EMI) requirement of system to power supply, PTH08T230W module can supply input voltage 4.5V to 14V, output 0.7V to 5.5V scope is used, the AC power that is input as 12V is converted to respectively to 1.2V VCCINT power supply, 1.5V DDR3 power supply, 3.3V GMII and 3.3V GPMC, 3.3V crystal oscillator power supply, 3.3VMGT power supply etc., Debug/JATG interface is set on circuit board, can communicates by letter with CPU by serial SPI mode, debugging core board, Debugging message can show by host computer, on circuit board, there are five groups of wire jumpers, wire jumper J9, J10, J11, J12 is configuration control wire jumper, one group of four Switch switch S 1, S2, S3, S4, is controlled and is selected the configuration mode of FPGA by switch, coordinate wire jumper function, and after its combination, state is such: when switch S 1 is 0, S2 is that 1, S3 is that 0, S4 is 0 o'clock, wire jumper J9, J10, J11, J12 connects 1,2 pin, configuration mode is initiatively, FPGA after powering on initiatively from Flash file reading configure, data are serials, when switch S 1 is that 0, S2 is that 0, S3 is that 1, S4 is 1 o'clock, wire jumper J9, J10, J11, J12 connects 2,3 pins, and configuration mode is passive, and FPGA is passive receives configuration information from ARM or CPU, and data are serials, when switch S 1 is that 1, S2 is that 0, S3 is 1, S4 is 1 o'clock, wire jumper J9, J10, J11, J12 connects 2,3 pins, configuration mode is passive, and FPGA is passive receives configuration information from ARM or CPU, and data walk abreast, so core board configuration mode is various, not only support active arrangement but also support passive configuration, not only support series arrangement but also support parallel deployment, configuration feature enriches powerful, pin is controlled wire jumper J6, and HSWAPEN works as wire jumper state for connecing 1 in FPGA initialization and layoutprocedure, 2 o'clock, allly from circuit board, draw the user I/O pin getting off and be all drawn as high-impedance state, when wire jumper state connects 2,3 o'clock, all user I/O pins that get off that draw were all drawn as high level state, ten LED lamps are set on circuit board, powerful, not only can be used as display system duty, such as, power-up state, init state, configuration starting state, configuration completion status etc., can also be programmed, be that LED is able to programme, LED lamp is programmed into design, program, in order to show running status or the result of design, program, the socket of three row 50x2 is set on circuit board, (as shown in dotted line frame in Fig. 1, be positioned at below core board), totally 300 pins, the pin that do not used by system from fpga chip draws, remove ground connection and power pin, also have nearly 220 user I/O pins, these pins may be programmed to peripheral hardware, as USB interface, SD card interface etc., can expand, can use flexibly, such as, in monitoring field, can connect high-definition camera, as VGA video input mouth, then to video image rough handling, or be connected on other embedded platforms, be ARM, DSP or GPU, performance FPGA parallel computation advantage, can be used as intermediate data processing module, for the treatment of can the large algorithm part of parallel data amount, output intermediate result is given other core boards, or also can be extended to network interface card interface, for communications industry, the present invention can be used for various to system bulk, reliability, high speed processing, the occasion that requirement of real-time is higher, such as video is monitored in real time, the fields such as guided missile navigation, there is higher practicality, especially, in field of machine vision, image/video Processing Algorithm field, advantage is outstanding.

Fpga core board structure of circuit of the present invention, given full play to the advantage of fpga chip parallel computation, the ability with supercomputing, in image processing field and other data in enormous quantities, need field to be processed, comparable traditional core core improves the processing speed of data greatly, there is again more than 200 the user I/O pin of reaching able to programme simultaneously, can be used for multiple occasion, there is extensibility advantage flexibly, in conjunction with other platforms, use, can realize mutual supplement with each other's advantages, keep counting yield at a high speed and good real-time, improve the performance of system works, in embedded high-performance, calculate field use wider.

Claims

1. a fpga core board structure of circuit, it comprises circuit board, it is characterized in that, on described circuit board, fpga chip is set, on described fpga chip described circuit board around, the multi-disc DDR3 chip being connected is set, Flash chip with described fpga chip, crystal oscillator chip, level transferring chip, socket.

2. a kind of fpga core board structure of circuit according to claim 1, is characterized in that, described fpga chip connects four described DDR3 chips around.

3. a kind of fpga core board structure of circuit according to claim 1, it is characterized in that, described fpga chip connects three described crystal oscillator chips, two single-end user's clocks that described crystal oscillator chip is 100MHz wherein, the system differential clocks that crystal oscillator chip is 100M described in a slice.

4. a kind of fpga core board structure of circuit according to claim 1, it is characterized in that, described fpga chip connects five groups of wire jumpers, and described in five groups, wire jumper comprises that control wire jumper is put in four assembly and one group of pin is controlled wire jumper, and described in four groups, four Switch switches of wire jumper connection are controlled in configuration.

5. a kind of fpga core board structure of circuit according to claim 1, is characterized in that, described fpga chip connects Debug/JATG interface and ten LED display lamps.

6. a kind of fpga core board structure of circuit according to claim 1, is characterized in that, described FPGA connects the described socket of three row 50x2.

7. a kind of fpga core board structure of circuit according to claim 1, is characterized in that, described fpga chip is Spartan-6 XC6SLX150T.