CN102495568A - Development board of network multi-core processor on test board based on four field programmable gate arrays (FPGA) - Google Patents
Development board of network multi-core processor on test board based on four field programmable gate arrays (FPGA) Download PDFInfo
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Abstract
The invention discloses a development board of a network multi-core processor on a test board based on four field programmable gate arrays (FPGA). Four FPGA chips are interconnected to form an entire interconnected structure; each FPGA chip is provided with a GTX transmission channel and a GPIO transmission channel which are respectively connected with the other three FPGA chips; and each FPGA chip is provided with a power management module, a board level clock drive module and a memory system. Date input and output ports of the development board are respectively arranged on the second and the fourth FPGA chips; and the data input and output ports are full-duplex differential 2.5Gbps fiber interfaces. The emulated memory bandwidth of the development board reaches 759.2Gbps which is far from being achieved by the current circuit designs of the other development boards with multiple FPGAs; with the interconnection of the chips, the throughput is above 30Gbps; and the development board provides enough hardware resource for FPGA hardware designers so as to test and realize the design of a prototype chip of a VL (very large) multi-core processor based on NoC.
Description
Technical field
The present invention relates to integrated circuit technique; For being used for the development board of multi-core network processor design/checking; Be applicable to the design verification of VLSI (very large scale integrated circuits) software-hardware synergism; Be the platform of network-on-chip polycaryon processor software-hardware synergism testing authentication, be specially a kind of development board of the checking network-on-chip polycaryon processor based on four FPGA.
Background technology
Because the single-chip processor based on traditional SOC(system on a chip) SoC (System-on-Chip) is faced with very big problem at aspects such as core frequency, chip-on communication, power consumption and areas; Polycaryon processor based on network-on-chip NoC (Network-on-Chip) arises at the historic moment, and has solved the problems that the former faced from architectural framework.The NoC interconnection structure has advantages such as parallel communications, favorable expandability and handling capacity between IP be big, and solved polycaryon processor architectural question and perplex bus-structured global clock problem.Therefore, the NoC interconnection structure is the most promising solution of polycaryon processor system.
At present; Fpga chip is as carrying and verify the approach based on the polycaryon processor hardware designs of NoC; Become the research focus, but along with the scale of hardware designs constantly increases, the hardware resource of monolithic FGPA can not satisfy the polycaryon processor demand based on NoC on the one hand; Consider on the other hand based on the intensive computing of the most data-oriented of the polycaryon processor of NoC, to imitative deposit and sheet between the data communication throughput require very high.
Summary of the invention
The problem that the present invention need solve: existing monolithic FPGA development board can not satisfy the demand of the required hardware resource of VLSI designs; How development board design faces regarded as output controlling plate hardware resource; The polycaryon processor that satisfies NoC to imitative deposit and sheet between the requirement of data communication throughput, and guarantee the problem of development board stable operation.
Technical scheme of the present invention is: based on the development board of the checking network-on-chip polycaryon processor of four FPGA; Connect and compose full interconnect architecture between four fpga chips; Each sheet fpga chip all is provided with the GTX transmission channel and is connected with other three fpga chips respectively with the GPIO transmission channel; Said GTX transmission channel by 4 the tunnel independently the RocketIO passage form, the GTX transmission channel provides 64 bit wides, 125MHz; The data transmission of 10Gbps, the GPIO transmission channel is made up of the general I/O GPIO of 10 pairs of single-ended mode; Every fpga chip is respectively equipped with power management module, plate level timepiece drive module and storage system, and storage system comprises 3 groups 16 DDR3SDRAM, 2 36 SRAM and 2 24 s' Flash; Be respectively equipped with the data input and the data output interface of development board on second fpga chip and the 4th fpga chip, said data input and data output interface are the 2.5Gbps light mouth of full duplex difference.
Fpga chip is an Xilinx XC6VLX550T fpga chip; Be provided with the general I/O GPIO interface of full duplex difference high speed GTX interface LVDS and single-ended mode; The GTX transmission channel connects through the LVDS interface; The GPIO transmission channel connects through the GPIO interface, and the jtag interface of 4 fpga chips is connected into daisy chain, through the JTAG chain type and combine the iMPACT software arrangements FPGA of Xilinx.
The power management module of fpga chip is: outside voltage stabilizing power supply 12V; Adopt DC-DC Switching Power Supply and LDO linear stabilized power supply; The 12V power supply of outside voltage stabilizing power supply is converted to the power supply of 0.75V, 1.0V, 1.5V, 1.8V, 2.5V, 5V through the DC-DC Switching Power Supply, and the 5V power supply is converted to 1.2V and 3.3V power supply through the LDO linear stabilized power supply.
Plate level timepiece drive module comprises two kinds of real-time clocks; A kind of is external active crystal oscillator; The EG-2101CA125M that adopts EPSON company is that the GTX transmission channel of each chip provides the differential clocks of 125MHz to drive; Another kind utilizes the passive crystal oscillator of 25MHz and the low noise frequency synthesizer ICS843001I-22 of ICS company; Produce the 200MHz differential clocks through configuration and the output frequency of regulating the ICS843001I-22 chip, and through clock chip ICS8543BGT tell four the tunnel offer every fpga chip storage unit, to DDR3SDRAM the reference difference clock is provided.
In the storage unit; By 2 bit wides is 8bit; Capacity is that the MT41J256M8HX-15E chip composition of 2Gb obtains the DDR3SDRAM that a pool-size is 4Gb bit wide 16bit; The data of 2 MT41J256M8HX-15E die chips, clock, read-write flash signal and data mask signal are controlled respectively by FPGA, and address and control command signal are shared; 2 Flash are BPI NOR Flash; Capacity is 256Mbit; Bit wide is 16bit; A slice Flash wherein has the bit file of bit file and the software program design of hardware designs program, in the development board initialization procedure, when development board powers on back or fpga chip self reset key when effective; The bit file of bit file that development board is designed program from said Flash loaded with hardware and software program design is realized configuration and programming to FPGA BPI mode to the local program storer of each FPGA.
The PCB structural sheet of development board is clipped in signals layer between stratum and the bus plane.
The present invention has designed a kind of network-on-chip polycaryon processor checking development board based on four FPGA, satisfies hardware resource requirements, is that prior art does not all reach.Innovation part one of the present invention is, integrated 12 groups of DDR3SCRAM are with 3 groups on the every fpga chip on a development board, and it is imitative deposits bandwidth and reach 759.2Gbps, and this is that the circuit design of other many FPGA development board at present is far inaccessiable; Two, adopt the totally interconnected and totally interconnected dual mode of GPIO transmission channel of GTX transmission channel between fpga chip simultaneously; The GTX transmission channel has the data amount transmitted of 4 * 3.125Gbps; The totally interconnected transmission command that is used for of GPIO transmission channel, its chip interconnect throughput is greater than 30Gbps.The development board of the integrated four Xilinx XC6VLX550T fpga chips of the present invention can provide abundant hardware resource and port for FPGA hardware designs personnel; So that checking and realization based on the prototype chip design of the polycaryon processor of NoC, are also calculated the condition that provides on network-on-chip NoC, studying multi-core parallel concurrent later on.
The present invention can handle respectively needing task for processing to divide the processing unit that a plurality of subtasks are assigned on the different fpga chips, thus the parallelization that the realization task is handled; Data signaling rate and lock in time etc. are not only depended on the communication speed of processing unit itself between its task; The communication interconnected network that also depends on the connection processing unit; So four chips of development board of the present invention utilize the full duplex difference high speed GTX interface LVDS (Low-Voltage Differential Signaling) that FPGA provides and the High Speed General I/O GPIO of single-ended mode, realize the full internet structure between sheet; Wherein the Aurora agreement is followed in the data communication of difference high speed GTX interface LVDS, realize the high-speed transfer of the mass data between FPGA, and the high speed GPIO of single-ended mode provides the self defined interface space for FPGA developer.
The present invention has designed a kind of integrated development board of four Xilinx XC6VLX550T fpga chips, can abundant hardware resource be provided for FPGA hardware designs personnel, so that checking and realize the prototype chip design based on the ultra-large polycaryon processor of NoC.
Advantage of the present invention:
1) logical resource that enriches, the 4 total logical resource of FPGA: 549888*4=2199552;
2) storage resources that enriches, 24 DDR3 amount to 48Gb, and the outer SRAM of sheet reaches 256Mb, and ram in slice amounts to 115.8Mb.
3) the storage port throughput is big: DDRIII 400MHz*16*12=76.8Gbps, the outer SRAM 167MHz*64*4=42.752Gbps of sheet;
4) FPGA design flexibility, highly versatile: can adopt different processors, also can adopt identical processor, like ARM etc.;
5) support of emulation integrated software well: the third-party Modelsim of simulation software can accomplish functional simulation well, and the ISE of Xilinx company then can accomplish comprehensively well.
Description of drawings
Fig. 1 is the The general frame of development board of the present invention.
Fig. 2 is the FPGA subsystem diagram.
Fig. 3 is a system power supply design proposal block diagram.
Fig. 4 is low noise frequency synthesizer circuit figure.
Fig. 5 is that FPGA is connected with the interface of DDR3.
Fig. 6 is a BPI Flash Interface design.
Fig. 7 is the development board sterogram.
Embodiment
The development board of the present invention's design has 2 innovative points: the one, and imitate and deposit bandwidth much larger than other many FPGA development boards, the 2nd, inter-chip communication throughput super large.
Like Fig. 1; 4 Xilinx XC6VLX550T chips (FF1759) are arranged on the mainboard of the present invention, and it is interconnected entirely that chip chamber adopts high speed GTX IO interface and common I/O to realize, so that realize the pipeline parallel method of NoC polycaryon processor deal with data; Xilinx is different to the title method of the high speed serialization transceiver in different generations; V4 period be MGT, early stage V5LXT/SXT is GTP, the V5FXT band that went out afterwards be GTX.The present invention is for following versatility of FPGA mainboard; Adopt full interconnect architecture, each fpga chip all is provided with 3 big group GTX IO interfaces and links to each other with the corresponding GTX IO interface of other 3 fpga chips respectively, and GTX IO interface is LVDS here; Each FPGA connects the existing GTX IO of other 3 FPGA has GPIO to connect again; GTX IO interface connects and to obtain the GTX transmission channel, every group of GTX transmission channel of FPAG chip by 4 the tunnel independently the RocketIO passage form, 64 bit wides are provided; 125MHz; The data transmission of 10Gbps, the transmission channel that GPIO connects is made up of the general I/O GPIO of 10 pairs of single-ended mode, and the GTX transmission channel can be arranged to a lot of patterns such as Rocket IO pattern.As shown in Figure 1,4 fpga chips are interconnected entirely, and throughput reaches 10Gbps between sheet, in the full interconnect architecture; FPGA1 and FPGA2, FPGA3, FPGA4 connects respectively, FPGA2 and FPGA1; FPGA3, FPGA4 connects respectively, FPGA3 and FPGA1, FPGA2; FPGA4 connects respectively, FPGA4 and FPGA1, and FPGA2, FPGA3 connects respectively; Overall architecture of the present invention is an isomorphism symmetrical structure, and each fpga chip all has identical power management module, plate level timepiece drive module and storage system.As shown in Figure 2, every fpga chip is respectively equipped with power management module, plate level timepiece drive module and storage system, and storage system comprises 3 groups 16 DDR3SDRAM, 2 36 SRAM and 2 24 s' Flash; In addition, be respectively equipped with the data input and the data output interface of development board on second fpga chip and the 4th fpga chip, said data input and data output interface are the 2.5Gbps light mouth of full duplex difference.
RocketIO is in practical application, and the design of input clock, the setting of PLL parameter and PCB circuit and layout are the most important factor that influences the data transmission effect, and the present invention has carried out optimal design, makes the inter-chip communication throughput with super large of development board.Below main power management module, plate level timepiece drive module and the storage system of describing fpga chip of the present invention, and the PCB structural sheet of briefly describing development board of the present invention self distributes.
Usually, power supply is designed with two kinds of implementations: low pressure difference linearity stabilized voltage supply LDO and Switching Power Supply DC-DC.The characteristics of LDO are that the power supply precision is high, noise is little, relatively are suitable for the precision circuit power supply, and its shortcoming is that output power is often big inadequately, and the conversion efficiency of power is on the low side.The characteristics of DC-DC are that power conversion efficiency is high, and bigger power can be provided, but its power supply noise of LDO of comparing can increase, so DC-DC generally uses as the entire system stabilized voltage supply or directly supplies power as high power device.
In order to make system of the present invention have more stability and extendability, the load capacity of power-supply management system of the present invention is the twice of existing estimating power consumption at least.Because system of the present invention needs 0.75V, 1.0V, 1.2V, 1.5V, 1.8V, 2.5V and 3.3V stabilized voltage supply; Consider the power consumption of total system of the present invention; The present invention mainly adopts the Switching Power Supply that this efficient of DC-DC is high, output power is big; The partial circuit that local power consumption is less, accuracy requirement is high then adopts the LDO linear stabilized power supply, fully combines Switching Power Supply and linear stabilized power supply advantage separately to carry out the design of system power supply.The chip of DC-DC Switching Power Supply has adopted the LTM4601 of Linear Techn Inc.; The outside voltage stabilizing power supply 12V of system of the present invention.Power source design of the present invention is as shown in Figure 3, and the 12V power supply of outside voltage stabilizing power supply is converted to the power supply of 0.75V, 1.0V, 1.5V, 1.8V, 2.5V, 5V through the DC-DC Switching Power Supply, and the 5V power supply is converted to 12V and 3.3V power supply through the LDO linear stabilized power supply.
The present invention has realized two kinds of real-time clock RTC schemes.A kind of is external active crystal oscillator, and the EG-2101CA125M that selects EPSON company for use is that the difference high speed GTX interface of total system provides the differential clocks of 125MHz to drive; A kind of in addition is to utilize the passive crystal oscillator of 25MHz and the low noise frequency synthesizer ICS843001I-22 of ICS company; Can produce the 200MHz differential clocks accurately through configuration and adjusting chip; And through clock chip ICS8543BGT tell four the tunnel offer the DDR3SDRAM of every FPGA institute carry the reference difference clock, the chip physical circuit is referring to Fig. 4.The second way is because the scalable of its clock output frequency makes it have more dirigibility, also just lays a good groundwork for the versatility of whole flat and extensibility.
The capacity that every FGPA chip of the present invention is circumscribed with 3 groups of companies of Micron Technology (Micron) is 2Gb, and the monolithic bit wide is the storer of the MT41J256M8HX-15E (DDR3-1033) of 8bit, by two data buss of forming the 16bit width.XC6VLX550T FPGA can support the SSTL15 level standard, can carry out seamless link with DDR3SDRAM, and the interface of FGPA and DDR3SDRAM is as shown in Figure 5.
Just provided wherein being connected of one group of DDR3 and FPGA among Fig. 5, the FPGABANK that it connected is that the software I SE of the official development environment locking through Xilinx company obtains.The level standard of the different B ANK of FPGA, the user can oneself definition, and the present invention comes to each BANK input power supply with reference to the UCF file that ISE generates, and supplies power such as the power supply of the VCCO use 1.5V of BANK28 and BANK38.The data of two DDR3 chips, clock, read-write flash signal and data mask signal use FPGA to control respectively, and address and control command signal are shared.
The FPGA that adopts among the present invention is based on the SRAM framework and realizes logical design, so after power down, programming information is lost immediately.Fpga chip all must be downloaded the configuration data programming file that is generated by design document at every turn again when powering up.Every fpga chip of development board of the present invention is circumscribed with two identical BPI NOR Flash, and capacity is 256Mbit, and bit wide is 16bit.A slice Flash interface wherein uses in the system initialization process; When system powers on back or FPGA prototype chip reset key when effective; The bit file that the Flash loaded with hardware of system outside sheet designed program is realized configuration and programming to the FPGABPI mode to the local program storer of each FPGA; In addition, also be used for the bit file of load software program design at this a slice Flash.
The XC6VLX550T fpga chip that the present invention adopts can be supported the LVCOMS2.5V level standard, can carry out seamless link with BPINORFlash, and the interface of FPGA and BPINORFlash is as shown in Figure 6.
Two interfaces that BPI NOR Flash links to each other with FPGA among Fig. 6 are specific BANK, are respectively BANK24 and BANK34; The data line of Flash links to each other with FPGA BANK24 with control signal, and address signal links to each other with BANK34, and reset signal wherein links to each other with the PROG B of BANK0, and hardware designs personnel can set up the level standard of corresponding BANK on their own.In addition, in the present invention, 4 fpga chips also are linked to be traditional daisy chain through jtag interface; So that can and combine the iMPACT software arrangements FPGA of Xilinx through the JTAG chain type; Daisy chain is used for downloading design, just conspires to create 1 daisy chain to the jtag interface of 4 fpga chips, like this; Whole development board is programmed through an interface with regard to needing only; And the RocketIO passage is used for to the hardware and software communication usefulness that pours into, and realizes the data in high speed transmission, thereby has improved versatility of the present invention.
PCB structural sheet distribution plan of the present invention is as shown in Figure 7, and signals layer is clipped between stratum and the bus plane, strengthens anti-interference of the present invention and signal integrity.Development board is when making, and its internal layer copper is thick to be 18um, and live width is about 0.13mm, and single-ended impedance is 50ohm, and differential impedance is 100ohm.
In sum; The present invention has designed a kind of development board integrated circuit that enriches hardware resource, high-speed transfer that has; Its every FPGA is a sub-systems; Can be used as independently that module works alone, also can form an integral body provides one to have ultra-large logical resource, rich data memory bandwidth and space for the hardware designs personnel, the platform of the data transmission capabilities of high-throughput and high-speed real-time.
Claims (6)
1. based on the development board of the checking network-on-chip polycaryon processor of four FPGA; It is characterized in that connecting and composing full interconnect architecture between four fpga chips; Each sheet fpga chip all is provided with the GTX transmission channel and is connected with other three fpga chips respectively with the GPIO transmission channel; Said GTX transmission channel by 4 the tunnel independently the RocketIO passage form, the GTX transmission channel provides 64 bit wides, 125MHz; The data transmission of 10Gbps, the GPIO transmission channel is made up of the general I/O GPIO of 10 pairs of single-ended mode; Every fpga chip is respectively equipped with power management module, plate level timepiece drive module and storage system, and storage system comprises 3 groups 16 DDR3SDRAM, 2 36 SRAM and 2 24 s' Flash; Be respectively equipped with the data input and the data output interface of development board on second fpga chip and the 4th fpga chip, said data input and data output interface are the 2.5Gbps light mouth of full duplex difference.
2. the development board of the checking network-on-chip polycaryon processor based on four FPGA according to claim 1; It is characterized in that fpga chip is an Xilinx XC6VLX550T fpga chip; Be provided with the general I/O GPIO interface of full duplex difference high speed GTX interface LVDS and single-ended mode; The GTX transmission channel connects through the LVDS interface; The GPIO transmission channel connects through the GPIO interface, and the jtag interface of 4 fpga chips is connected into daisy chain, through the JTAG chain type and combine the iMPACT software arrangements FPGA of Xilinx.
3. the development board of the checking network-on-chip polycaryon processor based on four FPGA according to claim 1 and 2; The power management module that it is characterized in that fpga chip is: outside voltage stabilizing power supply 12V; Adopt DC-DC Switching Power Supply and LDO linear stabilized power supply; The 12V power supply of outside voltage stabilizing power supply is converted to the power supply of 0.75V, 1.0V, 1.5V, 1.8V, 2.5V, 5V through the DC-DC Switching Power Supply, and the 5V power supply is converted to 1.2V and 3.3V power supply through the LDO linear stabilized power supply.
4. the development board of the checking network-on-chip polycaryon processor based on four FPGA according to claim 1 and 2; It is characterized in that plate level timepiece drive module comprises two kinds of real-time clocks; A kind of is external active crystal oscillator; The EG-2101CA125M that adopts EPSON company is that the GTX transmission channel of each chip provides the differential clocks of 125MHz to drive; Another kind utilizes the passive crystal oscillator of 25MHz and the low noise frequency synthesizer ICS843001I-22 of ICS company; Produce the 200MHz differential clocks through configuration and the output frequency of regulating the ICS843001I-22 chip, and through clock chip ICS8543BGT tell four the tunnel offer every fpga chip storage unit, to DDR3SDRAM the reference difference clock is provided.
5. the development board of the checking network-on-chip polycaryon processor based on four FPGA according to claim 1 and 2; It is characterized in that in the storage unit; By 2 bit wides is 8bit; Capacity is that the MT41J256M8HX-15E chip composition of 2Gb obtains the DDR3SDRAM that a pool-size is 4Gb bit wide 16bit, and the data of 2 MT41J256M8HX-15E die chips, clock, read-write flash signal and data mask signal are controlled respectively by FPGA, and address and control command signal are shared; 2 Flash are BPI NOR Flash; Capacity is 256Mbit, and bit wide is 16bit, and a slice Flash wherein has the bit file of hardware designs program and the bit file of software program design; In the development board initialization procedure; When development board powers on back or fpga chip self reset key when effective, the bit file that development board is designed program from said Flash loaded with hardware and the bit file of software program design are to the local program storer of each FPGA, and realization is to the configuration and the programming of FPGABPI mode.
6. the development board of the checking network-on-chip polycaryon processor based on four FPGA according to claim 1 and 2 is characterized in that the PCB structural sheet of development board is clipped in signals layer between stratum and the bus plane.
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