CN216286653U

CN216286653U - Multiprocessor system, mainboard and computer equipment

Info

Publication number: CN216286653U
Application number: CN202121770517.0U
Authority: CN
Inventors: 张博
Original assignee: Loongson Zhongke Chengdu Technology Co ltd
Current assignee: Loongson Zhongke Chengdu Technology Co ltd
Priority date: 2021-07-30
Filing date: 2021-07-30
Publication date: 2022-04-12
Anticipated expiration: 2031-07-30

Abstract

The utility model provides a multiprocessor system, a mainboard and computer equipment, which relate to the field of processors, and the system comprises: at least two processors; each of the at least two processors includes: at least one PCIe port; the at least two processors are connected through respective PCIe ports; when the PCIe port of any processor is set to be in a master mode, the PCIe port of another processor connected with the processor is set to be in a slave mode, at least one PCIe port is set to be in a processor of the slave mode, and functions of the non-transparent bridge are integrated. The utility model has no external non-transparent bridge, so the power consumption consumed by the existence of the external non-transparent bridge does not exist, the power consumption of the multiprocessor system is greatly reduced, and the board carrying area overhead of the multiprocessor system is greatly reduced and the design complexity of the peripheral communication circuit of the multiprocessor system is indirectly reduced because the external non-transparent bridge does not exist.

Description

Multiprocessor system, mainboard and computer equipment

Technical Field

The present invention relates to the field of processors, and in particular, to a multiprocessor system, a motherboard, and a computer device.

Background

Multiprocessor systems are becoming mainstream servers due to their powerful computing capabilities. The multiprocessor system is a computer system in which a plurality of CPUs (central processing units) are integrated. For example: the two processor systems are the main boards of a computer system and work simultaneously by adopting 2 CPUs; the four-processor system is a computer system with 4 CPUs working on the mainboard at the same time.

In a multiprocessor system, different processors are typically connected through a PCIe (peripheral component interconnect express) non-transparent bridge, such as: the two processor systems communicate through an external non-transparent bridge. When data is transmitted between the two processors, the data address is translated through the address of the external non-transparent bridge. In the communication process, the state information between the two processors is realized through an external non-transparent bridge special register.

However, the external non-transparent bridge can be used only by one bridge, and when the number of processors increases, the number of corresponding external non-transparent bridges also needs to increase. The external non-transparent bridge not only has relatively high power consumption, but also causes large board load area overhead in the multiprocessor system, and indirectly increases the design complexity of the peripheral communication circuit of the multiprocessor system.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present invention has been made to provide a multiprocessor system, a main board, and a computer apparatus that overcome or at least partially solve the above problems.

In a first aspect, a multiprocessor system is provided, the system comprising: at least two processors;

each of the at least two processors includes: at least one PCIe port;

the at least two processors are connected through respective PCIe ports;

when the PCIe port of any processor is set to be in a master mode, the PCIe port of the other processor connected with the processor is set to be in a slave mode;

the at least one PCIe port is set to a slave mode processor that integrates the functions of a non-transparent bridge.

Optionally, the structure of the system comprises: a chained multiprocessor structure; or

A ring-type multiprocessor architecture.

Optionally, the chained multiprocessor structure comprises: a master processor and a slave processor; or

The master processor and a plurality of slave processors;

when the chain multi-processor structure is the main processor and one slave processor, the PCIe port of the main processor is set to be in the main mode, and the PCIe port of the slave processor connected with the main processor is set to be in the slave mode;

when the chain multi-processor structure is the main processor and a plurality of slave processors, the PCIe port of the main processor is set to be in the main mode, and the first PCIe port of a first slave processor connected with the main processor in the plurality of slave processors is set to be in the slave mode;

the second PCIe port of the first slave processor is set to the master mode, and the first PCIe port of the second slave processor of the plurality of slave processors connected with the first processor is set to the slave mode.

Optionally, the ring-type multiprocessor structure comprises: at least two parallel processors;

each of the at least two parallel processors comprises: two PCIe ports;

one PCIe port of the two PCIe ports of each parallel processor is set to be in the master mode, and the other PCIe port is set to be in the slave mode;

the PCIe port set as the master mode in any parallel processor is connected with the PCIe port set as the slave mode in another parallel processor, thereby forming the ring type multiprocessor structure.

Optionally, the main processor is any processor including a PCIe port;

the slave processor is a Loongson processor which comprises two PCIe ports, and one of the PCIe ports is set to be in an EP mode.

Optionally, each parallel processor is a Loongson processor, the Loongson processor includes two PCIe ports, and one of the PCIe ports is set to the EP mode.

Optionally, the at least one PCIe port is of type PCIe X1.

Optionally, each of the at least two processors comprises: and (4) a peripheral interface.

In a second aspect, a motherboard is provided, the motherboard comprising a multiprocessor system as described in any of the first aspects above.

In a third aspect, there is provided a computer device comprising a multiprocessor system as described in any one of the first aspects above.

The embodiment of the application has the following advantages:

in the utility model, a non-transparent bridge is not externally arranged, but the PCIe ports of the processors are directly based on the PCIe ports of the processors, the PCIe port of each processor is respectively set to be in a master mode or a slave mode, and the structure and the function of the multiprocessor system are realized according to the mode that the PCIe port set to be in the master mode in any processor is connected with the PCIe port set to be in the slave mode in another processor. Because the external non-transparent bridge is not provided, the power consumption consumed by the existence of the external non-transparent bridge does not exist, the power consumption of the multiprocessor system is greatly reduced, and because the external non-transparent bridge is not provided, the board carrying area overhead in the multiprocessor system is greatly reduced, and the design complexity of a peripheral communication circuit of the multiprocessor system is indirectly reduced.

Drawings

Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the utility model. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:

FIG. 1 is a block diagram of a two processor system;

FIG. 2 is a diagram of a preferred chained processor architecture using two processors in accordance with an embodiment of the present invention;

FIG. 3 is a diagram of a preferred chained processor architecture employing multiple processors in accordance with an embodiment of the present invention;

FIG. 4 is a schematic diagram of a preferred four processor ring processor configuration in accordance with embodiments of the present invention.

Detailed Description

In order to make the aforementioned objects, features and advantages of the present invention comprehensible, embodiments accompanied with figures are described in further detail below. It should be understood that the specific embodiments described herein are merely illustrative of the utility model, but do not limit the utility model to only some, but not all embodiments.

The inventors have discovered that currently connections are typically made in multiprocessor systems through PCIe external non-transparent bridges. Taking a two-processor system as an example, referring to fig. 1, a schematic diagram of a current two-processor system is shown. The two processors in fig. 1 are a CPU10 and a CPU20, which both illustratively exhibit their structures, such as a memory DDR (Double Data Rate synchronous dynamic random access memory) 30, a memory 40, a Universal Asynchronous Receiver Transmitter UART50(Universal Asynchronous Receiver/Transmitter, abbreviated UART), and other interface devices 60.

When using an external non-transparent bridge, each CPU needs to be connected to the external non-transparent bridge 80 through the HOST bridge 70. The external non-transparent bridge 80 is two peer-to-peer and independent PCIe buses that may connect with PCIe devices 90. The two processor systems communicate through an external non-transparent bridge 80. During data transmission between the two processors CPU10 and CPU20, the data addresses are translated by the external non-transparent bridge 80. During communication, state information between the processor CPU10 and the CPU20 is implemented via external non-transparent bridge 80 special registers.

The inventors have further studied on multiprocessor systems to find that the external non-transparent bridge 80 can only be used with one bridge, and as the number of processors increases, the number of corresponding external non-transparent bridges 80 also needs to increase. The external non-transparent bridge 80 has relatively high power consumption, and when a large number of external non-transparent bridges 80 are used, the power consumption of the whole multiprocessor system is greatly increased, the board-loading area overhead in the multiprocessor system is inevitably large, and the design complexity of the peripheral communication circuit of the multiprocessor system is indirectly increased.

Based on the above research findings, the inventors have creatively proposed a multiprocessor system, a motherboard, and a computer apparatus of the present invention. The technical means of the present invention will be described in detail below.

An embodiment of the present invention provides a multiprocessor system, including: at least two processors; each of the at least two processors includes: at least one PCIe port; at least two processors are connected through respective PCIe ports; when the PCIe port of any processor is set to be in the master mode, the PCIe port of another processor connected with the processor is set to be in the slave mode. If one PCIe port in any processor is set to slave mode, the processor needs to integrate the functions of the non-transparent bridge, i.e., the processor needs to integrate the functions of the non-transparent bridge in its own structure at design time.

In this embodiment of the present invention, setting the PCIe port of the processor as a master mode may be understood as setting the PCIe port of the processor as an rc (root complex) mode, and setting the PCIe port of the processor as a slave mode may be understood as setting the PCIe port of the processor as an ep (end point) mode.

Based on the above connection manner, the structure of the multiprocessor system according to the embodiment of the present invention may include: a chain multiprocessor configuration, or a ring multiprocessor configuration. The chain type multiprocessor structure is a chain type structure of a main processor and at least one slave processor, and comprises the following components: a master processor and one slave processor, or a master processor and multiple slave processors. It is understood that the master processor and one slave processor are chain structures using two processors; the main processor and the plurality of slave processors are chain type structures adopting three or more processors. The ring type multiprocessor structure is a structure in which at least two parallel processors form a ring, and the parallel processors are the same as each other and do not distinguish between master and slave.

When the chain type multiprocessor structure is a main processor and one slave processor, the PCIe port of the main processor is set to be in a main mode, and the PCIe port of the one slave processor connected with the main processor is set to be in a slave mode. Referring to FIG. 2, a schematic diagram of a preferred chain processor architecture employing two processors according to an embodiment of the present invention is shown.

In fig. 2, the main CPU100 (i.e., the main processor) is any processor including a PCIe port, that is, the main CPU100 may be a loongson CPU or any other currently known CPU, and it is only necessary to ensure that the CPU has a PCIe port. Since the PCIe port of the main CPU100 only needs to be set to the RC mode, the main CPU100 itself does not need to integrate the function of the non-transparent bridge. And the slave processor is a Loongson processor which comprises two PCIe ports, and one of the PCIe ports can be set to be in an EP mode. In the embodiment of the utility model, the PCIe port is set to be in the EP mode, and the function design of the external non-transparent bridge is integrated in the slave processor when the slave processor is designed, so that the slave processor can realize the function of the external non-transparent bridge by setting one PCIe port to be in the EP mode.

Each processor includes: peripheral interfaces, such as: the main CPU100 includes: a Memory DDR101, an SPI (Serial Peripheral Interface) FLASH (FLASH Memory) 102, a storage device 103, and other interfaces 104; the slave CPU200 (i.e., Loongson processor) includes: memory DDR201, SPI FLASH202, USB (Universal Serial Bus) device 203, I/O (input/output) interface 204, Universal asynchronous receiver transmitter UART 205, PCI device 206, I2C device 207, SPI device 208, RG45 protocol (protocol for realizing control by remote control 1000), and other devices 209.

When the master CPU100 and the slave CPU200 are connected, the PCIe port 1001 of the master CPU100 is set to the RC mode, and the PCIe port 2001 of the slave CPU200 is set to the EP mode, so that a configuration in which one main board employs two processor systems in which the master CPU100 and the slave CPU200 work together is formed.

In the embodiment of the utility model, when the chained multiprocessor structure is a main processor and a plurality of auxiliary processors, the PCIe port of the main processor is set to be in a main mode, and the first PCIe port of the first auxiliary processor connected with the main processor in the plurality of auxiliary processors is set to be in an auxiliary mode; the second PCIe port of the first slave processor is set to a master mode, and the first PCIe port of the second slave processor, which is connected with the first slave processor, among the plurality of slave processors, is set to a slave mode. Referring to FIG. 3, a schematic diagram of a chain processor architecture employing multiple processors is shown, which is preferred by the embodiment of the present invention.

For simplicity of illustration in fig. 3, all CPUs do not show specific peripherals, but only represent the peripheral interface 2000, and the main processor is exemplarily shown connected to the memory 4000. Similarly to the case of the two-processor system, when the master CPU100 and the plurality of slave CPUs are connected, the PCIe port 1001 of the master CPU100 is set to the RC mode, the first slave CPU200 (i.e., the first slave processor) is connected to the master CPU100, the first PCIe port0 of the first slave CPU200 is set to the EP mode, and the second PCIe port1 of the first slave CPU200 is set to the RC mode.

When the second slave CPU300 (i.e., the second slave processor) is connected to the first slave CPU200, the first PCIe port0 of the second slave CPU300 is set to the EP mode; assuming that there is a third slave CPU400, the second PCIe port1 of the second slave CPU300 is set to RC mode, and the first PCIe port0 of the third slave CPU400 is set to EP mode; by analogy, a structure that one main board adopts a plurality of processor systems which work together by the main CPU100 and a plurality of slave CPUs is formed. Of course, it is understood that if there is no third slave CPU400 after the second slave CPU300, the second slave CPU300 only needs to set the first PCIe port0 to be in EP mode, and does not need to set the second PCIe port1 of the second slave CPU 300.

In an embodiment of the present invention, a ring-type multiprocessor structure includes: at least two parallel processors; each of the at least two parallel processors comprises: two PCIe ports; one of the two PCIe ports of each parallel processor is set to a master mode (RC mode) and the other PCIe port is set to a slave mode (EP mode); that is, the parallel processors are actually slave processors in a chained multiprocessor configuration.

The PCIe port set as the master mode in any parallel processor is connected with the PCIe port set as the slave mode in another parallel processor, thereby forming a ring type multiprocessor structure. Since each parallel processor needs to include two PCIe ports, each parallel processor is a Loongson processor that includes two PCIe ports, and one of the PCIe ports can be set to the EP mode. Referring to FIG. 4, a schematic diagram of a preferred four processor ring processor configuration is shown in accordance with an embodiment of the present invention.

Similarly, in fig. 4, for simplicity of illustration, all CPUs do not show specific peripherals, but only the peripheral interface 2000. Since all processors are parallel, when 4 processors are connected, one of the two PCIe ports (port0 and port1) of each processor is set to the RC mode, and the other PCIe port is set to the EP mode.

For example: as shown in fig. 4, the multiprocessor system includes a first CPU500, a second CPU600, a third CPU700, and a fourth CPU800 connected in sequence; the first CPU500 is connected to the second CPU600 and the fourth CPU800, respectively, so that the first PCIe port0 of the first CPU500 is set to an EP mode, and the second PCIe port1 of the first CPU500 is set to an RC mode; the second CPU600 is further connected to the third CPU700, and then the first PCIe port0 connected to the second CPU600 and the first CPU500 is set to be in EP mode, and the second PCIe port1 connected to the second CPU600 and the third CPU700 is set to be in RC mode; the third CPU700 is further connected to the fourth CPU800, and then the first PCIe port0 connected to the third CPU700 and the second CPU600 is set to be in EP mode, and the second PCIe port1 connected to the third CPU700 and the fourth CPU800 is set to be in RC mode; the first PCIe port0 of the fourth CPU800 connected to the third CPU700 is set to the EP mode, and the second PCIe port1 of the fourth CPU800 connected to the first CPU500 is set to the RC mode. The rest two or more processors are in a ring type multiprocessor structure, and the like, so that a structure that one mainboard adopts a plurality of processor systems with a plurality of Loongson processors working together is formed.

It should be noted that, in the embodiment of the present invention, the type of the at least one PCIe port included in all processors is PCIe X1, which is a limitation in the present prior art, and in the foreseeable future, the type of the at least one PCIe port may not be limited to PCIe X1, but may be any type of port, and only the above structural requirements need to be met.

Based on the multiprocessor system, an embodiment of the present invention further provides a motherboard, where the motherboard includes the multiprocessor system described above.

Based on the multiprocessor system, an embodiment of the present invention further provides a computer device, where the computer device includes the multiprocessor system as described in any of the above.

Through the embodiment, the external non-transparent bridge is not arranged, the PCIe ports of the processors are directly set to be in the master mode or the slave mode based on the PCIe ports of the processors, and the structure and the functions of the multiprocessor system are realized according to the mode that the PCIe port set to be in the master mode in any processor is connected with the PCIe port set to be in the slave mode in another processor. Because the external non-transparent bridge is not provided, the power consumption consumed by the existence of the external non-transparent bridge does not exist, the power consumption of the multiprocessor system is greatly reduced, and because the external non-transparent bridge is not provided, the board carrying area overhead in the multiprocessor system is greatly reduced, and the design complexity of a peripheral communication circuit of the multiprocessor system is indirectly reduced.

While preferred embodiments of the present invention have been described, additional variations and modifications of these embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the embodiments of the utility model.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.

The technical solutions provided by the embodiments of the present invention are described in detail above, and the principles and embodiments of the present invention are explained herein by using specific examples, and the descriptions of the above embodiments are only used to help understanding the method and the core ideas of the present invention; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. A multiprocessor system, characterized in that the system comprises: at least two processors;

each of the at least two processors includes: at least one PCIe port;

the at least two processors are connected through respective PCIe ports;

2. The system of claim 1, wherein the structure of the system comprises: a chained multiprocessor structure; or

A ring-type multiprocessor architecture.

3. The system of claim 2, wherein the chained multiprocessor structure comprises: a master processor and a slave processor; or

The master processor and a plurality of slave processors;

the second PCIe port of the first slave processor is set to the master mode, and the first PCIe port of the second slave processor of the plurality of slave processors connected with the first slave processor is set to the slave mode.

4. The system of claim 2, wherein the ring-type multiprocessor fabric comprises: at least two parallel processors;

each of the at least two parallel processors comprises: two PCIe ports;

5. The system of claim 3, wherein the host processor is any processor that includes a PCIe port;

6. The system of claim 4, wherein each parallel processor is a Loongson processor comprising two PCIe ports, and wherein one of the PCIe ports is set to EP mode.

7. The system of any of claims 1-6, wherein the at least one PCIe port is of type PCIeX 1.

8. The system according to any of claims 1-6, wherein each of the at least two processors comprises: and (4) a peripheral interface.

9. A motherboard, characterized in that it comprises a multiprocessor system as claimed in any one of claims 1 to 8.

10. A computer device, characterized in that the computer device comprises a multiprocessor system according to any one of claims 1 to 8.