CN209928413U - COMe module and computer - Google Patents

Abstract

The utility model provides a COMe module and computer, COMe module specifically includes: the device comprises a processor based on an MIPS framework, a Loongson No. 7 bridge chip and a COMe connector; the processor based on the MIPS framework is connected with the Loongson No. 7 bridge chip through an HT bus so as to carry out data communication; the Loongson No. 7 bridge chip is connected with the COMe connector through an external interface. The embodiment of the utility model provides a complexity of buildding of COMe module not only can have been reduced to, the reliability of COMe module work can also be improved.

Description

COMe module and computer

Technical Field

The utility model relates to a computer technology field especially relates to a COMe module and computer.

Background

The ruggedized Embedded Computer has the advantages of high performance, low power consumption, small size and the like, and a common ruggedized Embedded Computer architecture has Computer On Module (COM) structures such as Compact Peripheral Component Interconnect (Compact Peripheral Component Interconnect) standard (Compact Technology Extended, ETX) and the like.

The Computer module extension standard (COM-Express, COMe) is a Computer module standard established by the international association of industrial Computer Manufacturers (pci Express Manufacturers Group, PICMG), which is an upgraded version of ETX. The COMe is an open industry standard, is a new bus Technology based on high-speed Input Output (IO) interfaces such as PCI Express, Low Voltage Differential Signaling (LVDS), gigabit net, Universal Serial Bus (USB) 2.0, Serial Advanced Technology Attachment (SATA), and is particularly suitable for implementing a customized industrial computer solution.

The COMe module has the advantages of microminiature, high integration degree, high reliability and the like, and can be widely applied to the fields of industrial automation, intelligent equipment, railway traffic, medical electronics and the like. However, the existing COMe module is usually built in a north-south bridge manner, so that the complexity of the building manner for generating the COMe module is high.

SUMMERY OF THE UTILITY MODEL

In view of the above, the present invention has been made to provide a COMe module and a computer that overcome or at least partially solve the above problems.

On the one hand, the utility model discloses a COMe module, include: a processor based on MIPS (microprocessor without internal interlocking pipeline Stages) architecture, a Loongson No. 7 bridge chip and a COMe connector; wherein the content of the first and second substances,

the processor based on the MIPS framework is connected with the Loongson No. 7 bridge chip through an HT (Hyper Transport, end-to-end bus technology) bus so as to carry out data communication;

the Loongson No. 7 bridge chip is connected with the COMe connector through an external interface.

Optionally, the MIPS architecture-based processor comprises a loongson No. 3 processor; the processing device comprises a processing device, a processor and a processor, wherein the processing device comprises a processing device and is characterized in that the No. 3 processing device of the dragon core comprises any one of a dragon core 3A1000, a dragon core 3A2000, a dragon core 3A3000, a dragon core 3A4000, a dragon core 3A5000, a dragon core 3B1000, a dragon core 3B2000 and a dragon core 3B 3000;

the Loongson No. 7 bridge piece comprises any one of a Loongson 7A1000 and a Loongson 7A 2000.

Optionally, the external interface includes: DVO (Data Voice out) Interface, GMAC (gigabit network media access control) Interface, UART (Universal Asynchronous Receiver/Transmitter) Interface, PCIE (Peripheral Component Interface) Interface, I2C (Inter-Integrated Circuit, two-wire Serial bus) Interface, SPI (Serial Peripheral Interface) Interface, HAD (High Definition Audio) Interface, USB Interface, SATA Interface, and GPIO (General-purpose input/output) Interface.

Optionally, the COMe module further includes: an analog input chip and an analog output chip; wherein the content of the first and second substances,

the analog input chip is connected with the Loongson No. 7 bridge chip through the I2C interface, and is also connected with an input acquisition interface on the COMe connector;

the analog output chip is connected with the Loongson No. 7 bridge chip through the SPI interface, and the analog output chip is further connected with an external output interface on the COMe connector.

Optionally, the COMe module further includes: DVO conversion chip and Ethernet chip; wherein the content of the first and second substances,

the DVO conversion chip is connected with the Loongson No. 7 bridge chip through the DVO interface, and the DVO conversion chip is used for converting a DVO signal output by the Loongson No. 7 bridge chip into a VGA format signal and outputting the VGA format signal to the COMe connector;

the Ethernet chip is connected with the Loongson No. 7 bridge chip through the GMAC interface, and the Ethernet chip is used for converting GMAC signals output by the Loongson No. 7 bridge chip into standard gigabit differential network signals and connecting the gigabit differential network signals to the COMe connector.

Optionally, the COMe module further includes: a transceiving control chip and a PCI control chip; wherein the content of the first and second substances,

the receiving and transmitting control chip is connected with the Loongson No. 7 bridge plate through the UART interface and is also connected with the COMe connector;

the PCI control chip is connected with the Loongson No. 7 bridge chip through the PCIE interface, and is used for converting PCIE signals output by the Loongson No. 7 bridge chip into standard PCI signals and connecting the standard PCI signals to the COMe connector.

Optionally, the COMe module further includes: SPI Nor Flash; wherein the content of the first and second substances,

and the SPI Nor Flash memory is connected with the Loongson No. 7 bridge chip through an SPI interface.

Optionally, the COMe module further includes: a first memory submodule, a second memory submodule and a third memory submodule; wherein the content of the first and second substances,

the first memory submodule and the second memory submodule are connected with the processor based on the MIPS framework;

and the third memory submodule is connected with the Loongson No. 7 bridge plate.

Optionally, the COMe module further includes: a power supply sub-module; wherein the content of the first and second substances,

the power supply sub-module is respectively connected with the processor based on the MIPS framework and the Loongson No. 7 bridge piece, and the power supply sub-module is used for connecting working voltage to the processor based on the MIPS framework and the Loongson No. 7 bridge piece.

Optionally, the COMe module further includes: a clock sub-module; wherein the content of the first and second substances,

the clock submodule is respectively connected with the processor based on the MIPS framework and the Loongson No. 7 bridge chip, and the clock submodule is used for accessing a working reference clock to the processor based on the MIPS framework and the Loongson No. 7 bridge chip.

On the other hand, the utility model also discloses a computer, include: the COMe module.

The utility model discloses a following advantage:

in the COMe module provided by the embodiment of the utility model, the MIPS architecture-based processor and the Loongson No. 7 bridge plate are adopted, so that the key hardware design of the COMe module does not need a south bridge and a north bridge, and the building complexity of the COMe module is effectively reduced; and the processor based on the MIPS framework and the Loongson No. 7 bridge piece can achieve a good adaptation effect, so that the working reliability of the COMe module built by the processor based on the MIPS framework and the Loongson No. 7 bridge piece is guaranteed.

Drawings

Fig. 1 is a schematic structural diagram of a COMe module of the present invention;

FIG. 2 is a schematic diagram of another COMe module of the present invention;

fig. 3 is a schematic diagram of the connection structure of the power supply submodule, the clock submodule, the processor based on the MIPS framework and the Loongson No. 7 bridge.

Detailed Description

In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention is described in detail with reference to the accompanying drawings and the detailed description.

Example one

Referring to fig. 1, a schematic structural diagram of a COMe module of the present invention is shown, which may specifically include: a processor 10 based on MIPS architecture, a Loongson No. 7 bridge 20 and a COMe connector 30; the processor 10 based on the MIPS architecture is connected with the Loongson No. 7 bridge chip 20 through an HT bus to perform data communication; the Loongson No. 7 bridge chip 20 is connected with the COMe connector 30 through the external interface 200. The processor 10 based on the MIPS architecture may be connected to the HT high-speed bus interface on the Loongson No. 7 bridge 20 through its own HT high-speed bus interface, and the HT high-speed bus interface on the processor 10 based on the MIPS architecture is connected to the HT high-speed bus interface on the Loongson No. 7 bridge 20 through an HT bus.

In the COMe module provided by the embodiment of the utility model, through adopting the processor 10 based on the MIPS framework and the Loongson No. 7 bridge piece 20, because the Loongson No. 7 bridge piece realizes the functions of the south and north bridge pieces only through the form of one bridge piece, the key hardware design of the COMe module does not need the south bridge and the north bridge, and the complexity of building the COMe module is effectively reduced; moreover, the processor 10 and the Loongson No. 7 bridge chip 20 based on the MIPS framework can achieve a good adaptation effect, so that the working reliability of the COMe module built by the processor 10 and the Loongson No. 7 bridge chip 20 based on the MIPS framework is guaranteed.

In the embodiment of the present invention, the processor 10 based on the MIPS framework can be any one of the loongson 3a1000 processor (LS3a1000), loongson 3a2000 processor (LS3a2000), loongson 3a3000 processor (LS3a3000), loongson 3a4000 processor (LS3a4000), loongson 3a5000 processor (LS3a5000), loongson 3B1000 processor (LS3B1000), loongson 3B2000 processor (LS3B2000), loongson 3B3000 processor (LS3B 3000).

Taking a Loongson 3A3000 processor as an example, the processor is internally integrated with 4 64-bit four-emission superscalar GS464e high-performance processor cores; the split shared three-level Cache (composed of 4 individual modules, each module having a capacity of 2MB) with 8MB integrated inside; cache consistency of multi-core and I/O DMA access is maintained through a directory protocol; 2 DDR3 controllers with 64-bit Error Checking and Correcting (ECC) integrated inside; 2 16-bit HT controllers are integrated; each 16-bit HT interface is split into two 8-way HT ports for use; 32-bit 33MHzPCI is integrated inside; and 1 LPC interface, 2 UART interfaces, 1 SPI interface and 16 GPIO interfaces are integrated.

Specifically, the No. 7 bridge pieces 20 of the dragon core can be any one of 7a1000 bridge pieces of the dragon core and 7a2000 bridge pieces of the dragon core. Taking the 7a1000 Loongson bridge plate as an example, the Loongson bridge plate can provide north and south bridge functions for a Loongson processor, and specifically comprises the following steps: 16-bit HT 3.0 interface, support two-way bridge piece mode: a 2D/3D Graphics Processor (GPU); a display controller supporting a two-way DVO display; a 16-bit DDR3 display controller; 3 x8 PCIE 2.0 interfaces, each x8 interface can be split into 2 independent x4 interfaces; 2 x4 PCIE 2.0 interfaces, which can be split into 6 independent x1 interfaces; 3 SATA 2.0 interfaces; 6 USB2.0 interfaces; 2 RGMII gigabit network interfaces (GMAC interfaces); HDA/AC97 configurable interface; supporting the RTC; support for HPET; a UART interface; an I2C interface; an LPC interface; an SPI interface; a GPIO interface; support the ACPI specification; JTAG boundary scans are supported.

In practical application, the MIPS-based processor and the Loongson No. 7 bridge chip are adopted, so that the key hardware design of the COMe module does not need a south bridge and a north bridge, and the building complexity of the COMe module is effectively reduced; and the processor based on the MIPS framework and the Loongson No. 7 bridge piece can achieve a good adaptation effect, so that the working reliability of the COMe module built by the processor based on the MIPS framework and the Loongson No. 7 bridge piece is guaranteed.

Alternatively, the external interface 200 may include: DVO interface 201, GMAC interface 202, UART interface 203, PCIE interface 204, I2C interface 205, SPI interface 206, HDA interface 207, USB interface 208, SATA interface 209, and GPIO interface 210.

In the embodiment of the present application, the external interface 200 may further include an I2C interface 205 and an SPI interface 206 in addition to the general DVO interface 201, the GMAC interface 202, the UART interface 203, the PCIE interface 204, the HDA interface 207, the USB interface 208, the SATA interface 209, and the GPIO interface 210, and compared with the problem that the existing COMe module does not include a digital-analog interface, the types of interfaces provided by the COMe module provided in the embodiment of the present invention are rich, that is, conversion between a digital signal and an analog signal may be realized through the I2C interface and the SPI interface, so that the richness of external devices on the COMe module may be improved.

It should be noted that the external interface 200 is only used to indicate an interface group required by the Loongson No. 7 bridge 20 when being connected to the COMe connector 30, and does not indicate that a special external interface 200 is integrated inside the Loongson No. 7 bridge 20. When the Loongson No. 7 bridge chip 20 is applied to other scenes and connected with other devices, the external interface 200 thereon can also be referred to as a name related to other devices.

The processor 10 and the Loongson No. 7 bridge piece 20 based on the MIPS framework can be suitable for various application fields, and the processor 10 and the Loongson No. 7 bridge piece 20 based on the MIPS framework are adopted, so that a more flexible extension form is provided for a user, and the design cycle of constructing a computer product by the processor 10 based on the MIPS framework is shortened; moreover, the COMe module can be adapted to expansion boards of various types of industrial control computers, and the requirement of a user for reinforcement and expansion based on the COMe module is met.

Specifically, the processor 10 based on the MIPS architecture and the Loongson No. 7 bridge 20 may be connected through an HT high-speed bus interface, which has a width operating in a 16-bit mode. In practical applications, the HT high-speed bus may be an HT1 high-speed bus or an HT0 high-speed bus, and is suitable for different MIPS-based processors 10, for example, chip No. 7 may be connected to a processor in the loongson 3A series (for example, any one of processors including loongson 3A1000, loongson 3A2000, loongson 3A3000, and loongson 3A4000) through an HT1 bus, and chip No. 7 may be connected to a processor in the loongson 3B series (for example, any one of processors including loongson 3B1000, loongson 3B2000, and loongson 3B3000) through an HT0 bus, which is not limited by the embodiments of the present invention.

In the embodiment of the present invention, the COMe module can further include: a power supply sub-module; the power supply sub-module is respectively connected with the processor 10 based on the MIPS framework and the Loongson No. 7 bridge piece 20, and the power supply sub-module can be used for connecting working voltage to the processor 10 based on the MIPS framework and the Loongson No. 7 bridge piece 20. Specifically, the power supply sub-module may be further configured to control a power-on sequence of the interfaces in the processor 10 and the Loongson No. 7 bridge 20 based on the MIPS architecture according to actual needs.

Specifically, the voltage output interface of the power supply sub-module may be connected to a power supply interface of the processor 10 based on the MIPS architecture, and the voltage output interface of the power supply sub-module may also be connected to interfaces such as a power supply interface of the No. 7 bridge 20, the GPIO interface 210, and the memory interface.

Illustratively, the connection structure of the power supply sub-module with the MIPS architecture based processor 10 and the Loongson No. 7 bridge 20 is shown in FIG. 3. The processor 10 based on the MIPS architecture and the Loongson No. 7 bridge piece 20 both include a power supply interface, and the power supply sub-module is respectively connected with the power supply interface of the processor 10 based on the MIPS architecture and the power supply interface of the Loongson No. 7 bridge piece 20.

The power supply sub-module may be a power supply module composed of multiple DCDC switching power supplies and multiple LDO (low dropout regulator) linear power supplies, and may provide operating voltages with different voltage values for the processor 10 and the Loongson No. 7 bridge plate 20 of the MIPS architecture. The DCDC switching power supply and the LDO linear power supply are both the existing power supply modules, and a user can select a specific model according to the requirement; illustratively, the DCDC (direct current power supply) switching power supply may be implemented by an existing RT8809 power supply, ADP5052 power supply, IR3894 power supply, or the like; the LDO linear power supply can be implemented by the existing LM317, ICL7660, TPS51200, etc., and will not be described herein.

Optionally, the power supply interface of the processor 10 based on the MIPS architecture includes a plurality of sub power supply interfaces, each sub power supply interface is connected to a component requiring a working voltage, and the sub power supply interfaces are interfaces connected to a Core processor (Core), an HT bus, a memory controller, an IO, and the like. Similarly, the power supply interface of the Loongson No. 7 bridge chip 20 also includes a plurality of sub power supply interfaces, each of which is connected to a component requiring a working voltage, and the sub power supply interfaces are, for example, interfaces connected to a Core processor (Core), an HT bus, a memory controller, an IO, an RTC (Real-Time Clock, Real-Time Clock chip), and the like.

In practical application, the power supply sub-module may be further connected to other chips on the COMe module, and is configured to access operating voltages to the other chips.

In the embodiment of the present invention, the COMe module may further include a clock sub-module; the clock submodule is respectively connected with the processor 10 based on the MIPS framework and the Loongson No. 7 bridge chip 20. The clock submodule may be used to access a working reference clock to the MIPS architecture based processor 10 and the Loongson No. 7 bridge 20.

Specifically, the clock submodule may be connected to the processor 10 based on the MIPS architecture through its own clock signal output interface, and is accessed to the processor core clock, and the clock submodule may also be connected to the HT bus, and is accessed to the HT bus reference clock, and meanwhile, the clock submodule may also be connected to the SATA interface 209 and the PCIE interface 204 of the Loongson No. 7 bridge 20 through its own clock signal output interface, so as to be accessed to the SATA clock and the PCIE clock.

Illustratively, the connection structure of the clock submodule with the MIPS architecture based processor 10 and the Loongson No. 7 bridge 20 is shown in FIG. 3. The processor 10 based on the MIPS architecture and the Loongson No. 7 bridge chip 20 both include a clock interface, and a clock signal output interface of the clock sub-module is connected with the clock interface of the processor 10 based on the MIPS architecture and the clock interface of the Loongson No. 7 bridge chip 20 respectively.

The clock submodule can be a clock module consisting of an active crystal oscillator, a passive crystal oscillator and a clock Buffer; it can provide clock signals of processor core clock, DDR clock, HT bus reference clock, SATA clock, PCIE clock, etc. for processor 10 of MIPS architecture and Loongson No. 7 bridge 20. The active crystal oscillator, the passive crystal oscillator and the clock Buffer are all existing devices, and a user can select a specific model according to the requirement.

In practical application, the clock sub-module may be further connected to other chips on the COMe module through its own clock signal output interface, and is configured to access a working reference clock to the other chips.

In the embodiment of the present invention, the COMe module further includes: a first memory submodule 101, a second memory submodule 102 and a third memory submodule 211; the first memory submodule 101 and the second memory submodule 102 are connected with the processor 10 based on the MIPS architecture; the third memory submodule 211 is connected to the Loongson No. 7 bridge 20.

Specifically, the first Memory submodule 101, the second Memory submodule 102 and the third Memory submodule 211 may be DDR3 (Double-Data-Rate) Memory granules or SO-DIMM (Small Outline dual inline Memory Module) Memory banks, which is not limited in the embodiment of the present invention.

The embodiment of the utility model provides an in the COMe module that provides, integrated treater, bridge piece, memory, COMe connector, integrated including to the external interface: DVO interface, GMAC interface, UART interface, PCIE interface, I2C interface, SPI interface, HDA interface, USB interface, SATA interface and GPIO interface, etc. are commonly used mainstream peripheral equipment, so that a computer module with composite PICMG specification is realized; and moreover, a flexible COM-Express extension form is provided for users, the richness of external equipment on a COMe module can be improved, and the design cycle of a computer product constructed by a processor based on an MIPS framework can be shortened.

Referring to fig. 2, a schematic structural diagram of another COMe module of the present invention is shown, and as shown in fig. 2, the COMe module further includes: DVO conversion chip 401 and ethernet chip 402; wherein, the data input interface of the DVO conversion chip 401 is connected to the Loongson No. 7 bridge 20 through the DVO interface 201, the data output interface of the DVO conversion chip 401 is further connected to a Video Graphics Array (VGA) interface 301 on the COMe connector 30, and the DVO conversion chip 401 is configured to convert a DVO signal output by the Loongson No. 7 bridge 20 into a VGA format signal and output the VGA format signal to the COMe connector 30; the data input interface of ethernet chip 402 is connected to loongson No. 7 bridge 20 via GMAC interface 202, the data output interface of ethernet chip 402 is also connected to GEB0 interface 302 on COMe connector 300, and ethernet chip 402 can be used to convert GMAC signals output by loongson No. 7 bridge 20 into standard gigabit differential network signals and connect to COMe connector 30.

Illustratively, the DVO conversion chip 401 may be implemented by an ADV7125 chip; the ethernet chip 402 may be implemented by a marvell 88E1510 chip.

As shown in fig. 2, the COMe module may further include: a transceiver control chip 403 and a PCI control chip 404; wherein, the data input interface of the transceiving control chip 403 is connected with the Loongson No. 7 bridge chip 20 through the UART interface 203, and the data output interface of the transceiving control chip 403 is also connected with the COMe connector 30; the data input interface of the PCI control chip 404 is connected to the Loongson No. 7 bridge 20 through the PCIE interface 204, and the data output interface of the PCI control chip 404 may be configured to convert the PCIE signal output by the Loongson No. 7 bridge 20 into a standard PCI signal and connect to the COMe connector 30.

For example, the transceiver control chip 403 may be implemented by a MAX3160 chip; PCI controller chip 404 may be implemented as a PI7C9X110 chip.

In practical applications, a standard interface 203 (including any one of an RS232 interface, an RS484 interface, or an RS422 interface) may be disposed on the COMe connector 30, the transceiving control chip 403 may be a programmable multi-protocol transceiving device, and the transceiving control chip 403 may implement interconversion between the UART interface 203 and the standard RS232 interface and the standard RS484 interface. PCI control chip 404 may be used for access control for PCI interface 304.

The COMe module shown in fig. 2 may further include: an analog input chip 405 and an analog output chip 406; wherein, the data input interface of the analog input chip 405 is connected with the Loongson No. 7 bridge chip 20 through the I2C interface 205, and the data output interface of the analog input chip 405 is also connected with the input acquisition interface 305 (analog IN) on the COMe connector 30; the data input interface of the analog output chip 406 is connected to the Loongson No. 7 bridge chip 20 through the SPI interface 206, and the data output interface 406 of the analog output chip is also connected to the external output interface 306 (analog OUT) on the COMe connector 30.

In practical applications, the analog input chip 405 may be used for input control of analog signals, and the analog output chip 406 may be used for output control of analog signals.

For example, the analog input chip 405 may be implemented by an AD7993 chip; the analog output chip 406 may be implemented by an LTC2664 chip.

As shown in fig. 2, the HAD interface 207 of the external interface 200 may be connected to the HAD interface 307 of the COMe connector 30, the USB interface 208 of the external interface 200 may be connected to the USB2.0 6308 of the COMe connector 30, the SATA interface 209 of the external interface 200 may be connected to the mSata 3 interface 309 of the COMe connector 30, and the GPIO interface 210 of the external interface 200 may be connected to the GPIO 8 interface 310 of the COMe connector 30.

Specifically, the PCIE interface 204 may specifically include a PCIE x8 interface, a PCIE x1 interface, and a PCIE x4 interface, where the PCIE x1 interface may be connected to the PCI control chip 404 and the Loongson No. 7 bridge chip 20, the PCIE x8 interface is connected to PCIE 2 on the COMe connector 30, and the PCIE x4 interface is connected to a PCIE 1 interface on the COMe connector 30.

In practical applications, the COMe module may further include: the apparatus comprises a monitoring chip (watchdog)103, a first Flash memory 104, a hardware/software subsystem (Enhanced Joint Test Action Group, EJTAG)105, a buzzer 106, a UART conversion chip 107 and a debugging serial port 108, wherein the monitoring chip 103, the first Flash memory 104, the EJTAG105, the buzzer 106 and the UART conversion chip 107 are all connected with a processor 10 based on the MIPS architecture, and the debugging serial port 108 is connected with the UART conversion chip 107.

In practical applications, the monitoring chip 103 may be used to monitor the operating status of the processor 10, the first Flash memory 104 may be used to hold data permanently without current supply, the EJTAG105 may be used to support debugging on the processor 10, and the buzzer 106 may be used as a sounding device.

In practical applications, the COMe module may further include: SPI Nor Flash 212; wherein, the data transmission interface of the SPI NorFlash flash memory 212 is connected with the SPI interface of the Loongson No. 7 bridge chip 20. In practical application, the SPI NorFlash flash memory 212 is connected to the Loongson No. 7 bridge piece 20, and can store data on the Loongson No. 7 bridge piece 20, so that the data on the Loongson No. 7 bridge piece 20 is not lost after power failure.

As shown in fig. 2, the COMe module may further include: a second Flash memory 213, the second Flash memory 213 being connected to the bridge chip 20, the second Flash memory 213 being operable to permanently retain data without a current supply.

To sum up, the COMe module of the embodiment of the present invention includes the following advantages at least:

in the COMe module provided by the embodiment of the utility model, the MIPS architecture-based processor and the Loongson No. 7 bridge plate are adopted, so that the key hardware design of the COMe module does not need a south bridge and a north bridge, and the building complexity of the COMe module is effectively reduced; and the processor based on the MIPS framework and the Loongson No. 7 bridge piece can achieve a good adaptation effect, so that the working reliability of the COMe module built by the processor based on the MIPS framework and the Loongson No. 7 bridge piece is guaranteed.

The embodiment of the utility model provides a still provide a computer, specifically can include: the COMe module.

Finally, it should also be noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other like elements in a process, method, article, or terminal that comprises the element.

The above detailed description is made on a COMe module and a computer provided by the present invention, and the detailed examples are applied herein to explain the principles and embodiments of the present invention, and the description of the above embodiments is only used to help understand the method and the core idea of the present invention; meanwhile, for the general technical personnel in the field, according to the idea of the present invention, there are changes in the specific implementation and application scope, to sum up, the content of the present specification should not be understood as the limitation of the present invention.

Claims (11)

1. A COMe module, comprising: the device comprises a processor based on an MIPS framework, a Loongson No. 7 bridge chip and a COMe connector; wherein the content of the first and second substances,

the processor based on the MIPS framework is connected with the Loongson No. 7 bridge chip through an HT bus so as to carry out data communication;

the Loongson No. 7 bridge chip is connected with the COMe connector through an external interface.

2. The COMe module of claim 1, wherein the MIPS architecture-based processor comprises a Loongson processor # 3; the processing device comprises a processing device, a processor and a processor, wherein the processing device comprises a processing device and is characterized in that the No. 3 processing device of the dragon core comprises any one of a dragon core 3A1000, a dragon core 3A2000, a dragon core 3A3000, a dragon core 3A4000, a dragon core 3A5000, a dragon core 3B1000, a dragon core 3B2000 and a dragon core 3B 3000;

the Loongson No. 7 bridge piece comprises any one of a Loongson 7A1000 and a Loongson 7A 2000.

3. The COMe module of claim 1, wherein said external interface comprises: DVO interface, GMAC interface, UART interface, PCIE interface, I2C interface, SPI interface, HDA interface, USB interface, SATA interface and GPIO interface.

4. The COMe module of claim 3, further comprising: an analog input chip and an analog output chip; wherein the content of the first and second substances,

the analog input chip is connected with the Loongson No. 7 bridge chip through the I2C interface, and is also connected with an input acquisition interface on the COMe connector;

the analog output chip is connected with the Loongson No. 7 bridge chip through the SPI interface, and the analog output chip is further connected with an external output interface on the COMe connector.

5. The COMe module of claim 3, further comprising: DVO conversion chip and Ethernet chip; wherein the content of the first and second substances,

the DVO conversion chip is connected with the Loongson No. 7 bridge chip through the DVO interface, and the DVO conversion chip is used for converting a DVO signal output by the Loongson No. 7 bridge chip into a VGA format signal and outputting the VGA format signal to the COMe connector;

the Ethernet chip is connected with the Loongson No. 7 bridge chip through the GMAC interface, and the Ethernet chip is used for converting GMAC signals output by the Loongson No. 7 bridge chip into standard gigabit differential network signals and connecting the gigabit differential network signals to the COMe connector.

6. The COMe module of claim 3, further comprising: a transceiving control chip and a PCI control chip; wherein the content of the first and second substances,

the receiving and transmitting control chip is connected with the Loongson No. 7 bridge plate through the UART interface and is also connected with the COMe connector;

the PCI control chip is connected with the Loongson No. 7 bridge chip through the PCIE interface, and the PCI control chip is used for converting a PCIE signal output by the Loongson No. 7 bridge chip into a standard PCI signal and connecting the standard PCI signal to the COMe connector.

7. The COMe module of claim 3, further comprising: SPI Nor Flash; wherein the content of the first and second substances,

and the SPI Nor Flash memory is connected with the Loongson No. 7 bridge chip through an SPI interface.

8. The COMe module of any one of claims 1-7, further comprising: a first memory submodule, a second memory submodule and a third memory submodule; wherein the content of the first and second substances,

the first memory submodule and the second memory submodule are connected with the processor based on the MIPS framework;

and the third memory submodule is connected with the Loongson No. 7 bridge plate.

9. The COMe module of claim 8, further comprising: a power supply sub-module; wherein the content of the first and second substances,

the power supply sub-module is respectively connected with the processor based on the MIPS framework and the Loongson No. 7 bridge piece, and the power supply sub-module is used for connecting working voltage to the processor based on the MIPS framework and the Loongson No. 7 bridge piece.

10. The COMe module of claim 8, further comprising: a clock sub-module; wherein the content of the first and second substances,

the clock submodule is respectively connected with the processor based on the MIPS framework and the Loongson No. 7 bridge chip, and the clock submodule is used for accessing a working reference clock to the processor based on the MIPS framework and the Loongson No. 7 bridge chip.

11. A computer, comprising: the COMe module of any of claims 1 to 10.

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