CN103581070B - A kind of satellite communication mobile terminal base band processing system and application process thereof - Google Patents
A kind of satellite communication mobile terminal base band processing system and application process thereof Download PDFInfo
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- CN103581070B CN103581070B CN201310508570.7A CN201310508570A CN103581070B CN 103581070 B CN103581070 B CN 103581070B CN 201310508570 A CN201310508570 A CN 201310508570A CN 103581070 B CN103581070 B CN 103581070B
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D30/00—Reducing energy consumption in communication networks
- Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks
Abstract
The present invention relates to a kind of satellite communication mobile terminal base band processing system, including framework based on AXI bus, this framework uses 32 system bus 1 to carry out high-speed equipment interconnection, to realize concurrent full internet data and to control mutual；And connect basic module and low-speed serial peripheral hardware by 32 BITBUS network 2, and by bus switching bridge, system bus 1 and system bus 2 are interconnected, it is achieved the equipment that high-speed bus is interconnected can carry out data and control mutual basic module and low-speed serial peripheral hardware.The present invention is reasonable in design, simple in construction, flow process understands, solves a difficult problem for interconnection on multinuclear interconnection and sheet, compares the design of this field existing level, chip specific aim is higher, area is less, and power consumption is lower, have employed simultaneously and carries out hardware module interconnection based on the reusable bus interface module of IP, add motility, reduce cost and design risk.
Description
Technical field
The present invention relates to wireless communication technology field, especially a kind of band processing system, a kind of satellite
Communication terminal band processing system.
A kind of method that the invention still further relates to applied satellite communication terminal band processing system.
Background technology
At present, in a satellite communication system, user terminal provides the function obtaining service from the interface of satellite system.
Baseband processor is the part that user terminal is most crucial, is mainly used to launch and receive baseband signal.During transmitting, audio signal
Or application processor data compilation becomes to be used for the base band code launched；During reception, the base band code received be interpreted as audio signal or
Application processor data.Chnnel coding, modulation, molding filtration, regularly transmission etc. operate to have needed upstream transmitter to include, with
Time needed downlink receiver function to include frame synchronization before process, demodulate, solve rate-matched, decoding etc. operation.Due to place
Reason process is complicated, requires higher to baseband chip in terms of speed, disposal ability, power consumption.
Traditional terminal baseband chip uses a general dsp to complete physical layer base band signal process, in addition combined with one
CPU such as arm processor completes protocol stack and processes, and uses the mode of the more additional bus bridges of static memory to complete knot between the two
Structure connects.Along with scientific and technological progress and application demand are growing, satellite communication system require higher data-handling capacity and
Lower power consumption.The framework using a general dsp and a CPU can not meet application needs.Then, multicore architecture birth
Raw, use multiple general dsp core to combine mainstay framework that more than one arm processor mode is current baseband chip.But
Being that this framework can introduce new problem, due to being continuously increased of core, the interconnection communication issue between different IPs is the most notable.With
Time, bring bigger pressure also can to bus and storage system, power consumption also can increase therewith.It addition, the compatible current master of general dsp
The functional module of Flow Technique scheme, is applied in specific standard agreement mobile terminal certainly exist substantial amounts of redundancy logic, from
And increase system area and power consumption, also can increase cost simultaneously.
Summary of the invention
It is an object of the invention to provide one and overcome the deficiencies in the prior art, it is possible to eliminate redundancy logic, reduce chip face
Amass the satellite communication terminal band processing system with power consumption and application process thereof.
The technical scheme is that
A kind of satellite communication mobile terminal base band processing system, including framework based on AXI bus, this framework uses 32
System bus 1 carries out high-speed equipment interconnection, to realize concurrent full internet data and to control mutual；And by 32 BITBUS network 2 even
Connect basic module and low-speed serial peripheral hardware, and by bus switching bridge, system bus 1 and system bus 2 are interconnected, real
The equipment that existing high-speed bus is interconnected can carry out data and control mutual basic module and low-speed serial peripheral hardware；Described high speed
Equipment includes radio frequency interface, system DMA, interior reception ASIP, launches to share on ASIP, hardware accelerator, OR processor core, sheet and deposit
Storage, MAC interface and sheet external memory interface；Described basic module and low-speed serial peripheral hardware include clock circuit, reset, timing control
System, low power consumption control, intercore communication control, interrupt control, general-purpose interface and I2C/SPI/UART/I2S.
Described interior reception ASIP and transmitting ASIP all includes that kernel and subsystem, described kernel include program storage, instruction
Acquisition, instruction decoding, data path 0-7 and data storage, the storage of its Program performs instruction for store ASIP；Instruction obtains
Take according to instruction address obtain ASIP perform instruction；Instruction decoding is after obtaining instruction, is decoded instruction, obtains
Take concrete instruction format；It is to perform to operate accordingly according to concrete instruction that instruction performs；Data path 0-7 is that instruction is held
Data channel parallel during row；Data storage is to use RAM and CACHE form, the result that storage instruction performs；Described son
System includes bus, bit wide coupling, kernel bag, data storage, register file, semaphore and directly accesses control, Qi Zhongzong
Line, for carrying out data exchange outside ASIP, supports AMBA AXI protocol；Program storage has been the programmed instruction of kernel
Storage；Kernel bag is to provide encapsulation and interface, state control, kernel example and the JTAG TAP function of kernel；Data storage is
Use RAM and CACHE form, complete the data storage of kernel；Register file is to provide the form of depositor, it is provided that outside right
The software interactive interface of ASIP；Directly access the control controlling to be to provide the DMA to data access.
Described bus structures are that bus IP has multiple main frame and from equipment interface, can multiple hardware modules be connected
Together, it is achieved chip-on communication.
Described OR processor has special purpose interface, more preferably to realize and bus couple processor, memorizer and peripheral module
Sheet on interconnect.
Native system is provided with single clock control module, it is achieved the regulation of dynamic clock frequency and idle mode functionality.
A kind of method of above-mentioned satellite communication terminal band processing system application, including up transmitting and downlink reception, its
Feature is that the method for described up transmitting comprises the following steps:
A1. upper layer information starts physical layer emission process, starts timing control module simultaneously;；
A2. chnnel coding by a special ASIP；
A3. after ASIP completes coding, radio frequency interface module the data after ASIP processes are read；
A4. radio frequency interface is shaped the operations such as filtering, up-sampling to launching data；
A5. judge whether timing controlled arrives the benchmark transmission time of communication standard, after arrival, open radio frequency interface, will
Data send, and otherwise continue waiting for；
Described descending receiving method comprises the following steps:
B1. upper layer information starts physical layer reception process, starts timing control module simultaneously；
B2. judge whether timing controlled arrives communication benchmark and receive the time, if arriving, then opens radio frequency interface, under reception
Row data, otherwise, proceed synchronization control, until arriving fiducial time；
B3. radio frequency interface module carries out the process such as interpolation, time-domain filtering to data；
B4. the data that radio frequency interface has been processed by system DMA move ASIP internal storage to；
B5. use special downlink reception ASIP to carry out data process, complete synchronization, channel estimation, equilibrium, data solution
Adjust, solve rate-matched function；
B6. data are transported to share memory module by system DMA, hardware accelerator module complete downlink reception remaining
Data decoding and verifying work.
Beneficial effects of the present invention:
The present invention is reasonable in design, simple in construction, and flow process understands, solves a difficult problem for interconnection on multinuclear interconnection and sheet, compares
The design of this field existing level, chip specific aim is higher, and area is less, and power consumption is lower, have employed based on IP reusable simultaneously
Bus interface module carry out hardware module interconnection, add motility, reduce cost and design risk.
Accompanying drawing explanation
Fig. 1 is the configuration diagram of the present invention.
Fig. 2 is the ASIP kernel micro structure schematic diagram of the present invention.
Fig. 3 is ASIP memory access subsystem structure schematic diagram of the present invention.
Fig. 4 is the present invention up transmitting chain schematic flow sheet.
Fig. 5 is downlink reception link schematic flow sheet of the present invention.
Fig. 6 is bus structures schematic diagram of the present invention.
Fig. 7 is OR interface schematic diagram of the present invention.
Detailed description of the invention
The present invention is further illustrated with embodiment below in conjunction with the accompanying drawings.
As it is shown in figure 1, the system that the present invention provides uses framework based on AXI bus, this framework uses 32 systems total
Line 1 carries out high-speed equipment interconnection, and the equipment of these interconnections includes connecting the radio frequency interface of radio frequency chip, system DMA, interior reception
Sharing storage, MAC interface, sheet external memory interface on ASIP, transmitting ASIP, hardware accelerator, OR processor core, sheet, these are mutual
The data of concurrent full interconnection can be realized between the equipment of connection and control mutual.Meanwhile, this framework is connected by 32 BITBUS network 2
Basic module and low-speed serial peripheral hardware in contact pin, including clock circuit, reset, timing controlled, low power consumption control, intercore communication control
Other Serial Peripheral Interface (SPI)s such as system, interruption control, general-purpose interface and I2C/SPI/UART/I2S, and, the high speed of this framework is mutual
Connection bus and low speed bus are directly interconnected by bus switching bridge, it is achieved the equipment that system bus 1 is interconnected can be right
Basic module and low-speed serial peripheral hardware carry out data and control mutual.
Described ASIP includes two kinds, and a kind of ASIP realizes inner receiver function, mainly include synchronizing, channel is estimated, equilibrium,
Demodulate, descramble, connect rate-matched, RS/Golay decoding, folding coding, CRC check etc..Another kind is to realize transmitter function,
Including controlling chnnel coding and data channel coding.ASIP instruction set needs for satellite communication mobile terminal base band Processing Algorithm
Asking and develop, structure has specific aim, irredundant hardware consumption resource, with the use of coprocessor, makes overall hardware resource excellent
Change.By balanced algorithm complexity and hardware resource consumption, what coprocessor mainly completed in downlink reception link more complicated translates
Code algorithm part.
Described ASIP is divided into kernel and subsystem two parts, and wherein the micro structure of kernel is as in figure 2 it is shown, be divided into:
Program storage (Program Memory): be used for storing ASIP performs instruction；
Instruction obtain (Instruction Fetch): be used for according to instruction address obtain ASIP perform instruction；
Instruction decoding (Instruction Decode): after obtaining instruction, instruction is decoded, it is thus achieved that concrete instruction
Form etc.；
Instruction performs (Instruction Issue): according to concrete instruction, perform corresponding operating；
Data path 0 ~ 7(data path0 ~ 7): data channel parallel in execution process instruction；
Data storage (Data Memory): be used for storing the storage of the result that instruction performs；
The structure of subsystem is as it is shown on figure 3, include:
Bus (AXI BUS): be used for outside ASIP carrying out the module of data interaction, support AMBA AXI agreement；
Bit wide coupling (Width Match): complete mating of the data bit width between bus module with inside；
Program storage (pm_ram, I Cache): complete the storage of the programmed instruction of kernel, uses the shape of RAM and CACHE
Formula；
Kernel bag (Core Wrapper, State Control, MT core, JTAG_TAP): provide kernel encapsulation and
Interface, it is provided that state control, kernel example, JTAG TAP function；
Data storage (dm_ram, D Cache): complete the storage of the data of kernel, use the form of RAM and CACHE；
Register file (Register File): provide the outside software interactive interface to ASIP, by the shape of depositor
Formula；
Semaphore (semiphore): provide and outside hardware interactive interface, by the way of semaphore；
Directly access control (DMA control): provide the DMA control mode to outside data access；
The present invention coordinates the differences such as external memory interface, intercore communication interface unit, Universal peripheral interface, radio frequency interface to connect
The use of mouth die block, supports to communicate with between application processor, other external modules such as functional chip, radio frequency chip outside.Coordinate
Bus connects, and completes whole terminal communication process, solves interconnection problems between sheet.For general-purpose interface, use IP reusing design.
Independent development radio frequency interface, completes the functions such as filtering and upper down-sampling, and provides multiple interfaces agreement.
For the modules in such scheme, develop bus cross bar switch, dissimilar connection-bridge, formation specially
Communication system between reason layer subsystem hardware module, solves interconnection problems on SoC sheet.Meanwhile, apply and open for free
OpenRisc(OR) processor realizes system control, and has carried out reseting meter for interface: change OR processor original
Wishbone EBI, uses more general interface standard, to realize with bus couple processor, memorizer, other are all
As DSP and peripheral module realize interconnecting on more preferable sheet.Share memorizer by intermodule, to reduce memory space, reduce eventually
The area of end group provided with processor and power consumption.Coordinate top layer DMA and the use of inside modules read-write DMA, flexible design.
Described bus structures take standardization IP module to realize, and as shown in Figure 6, bus IP has multiple main frame and from setting
Multiple hardware modules can be linked together, it is achieved chip-on communication by standby interface.Different bus protocol interface standard is different, carries
The data-handling capacity of confession the most difference, therefore according to the different demands of actual data throughput, selects different bus type
Type, reduces hardware consumption.For the intermodule communication that bus interface standards is inconsistent, bus switching bridge is used to be attached.Always
The data interaction that line connection-bridge will complete between dissimilar bus interface module.As a example by OR module, such as the mark of Fig. 7, OR module
Quasi-interface is wishbone interface, and this class interface is the most rare in design, and other modules are almost without using.Use inhomogeneity
OR module interface is converted into and other module accordant interface 2 types by the bridge module of type, between convenience and other hardware modules
Data interaction, reduce design cost, increase design flexibility.
Present invention also offers single clock control module, the module few firstly, for amount of calculation uses low-frequency clock,
Finally reach that to have the deadline between the different IPs of data interaction essentially the same.By the clock frequency of reduction part of module
Reduce the power consumption of whole design.Secondly, it is designed with a mode of operation switch to whole, enters sleep when chip does not works
State, all module from service, and after sleep a period of time, recover normal operating conditions by reconfiguring switch, it is achieved
The functions such as the regulation of dynamic clock frequency, idle pulley, reduce baseband processor power consumption.
Present invention also offers the application process of this processing system a kind of, including up transmitting and downlink reception.According to defending
Star communication standard, during up transmitting, the data after application processor data or audio coding decoding, by protocol stack processor
Process, baseband processor the interface provided, be transferred to physical layer subsystem, encoded after, passed by radio frequency chip interface
To radio frequency chip, then launch.Inside baseband processor, mainly complete the chnnel coding of data.Fig. 4 indicates base band
The handling process of processor up transmitting data:
Step 1:MAC layer provides physical layer configurations information, starts physical layer transmitter, starts timing control module simultaneously.
Step 2: chnnel coding by a special ASIP.
After step 3:ASIP completes coding, radio frequency interface module read the data after ASIP processes.
Step 4: radio frequency interface is shaped the operations such as filtering, up-sampling to launching data.
Step 5: judge whether timing controlled arrives the benchmark transmission time of communication standard, opens radio frequency interface after arrival,
Data are sent, otherwise continues waiting for.
Such scheme is according to satellite communication protocols, acknowledgement channel coding maximum amount of data, and according to algorithm structure, customizes
ASIP structure and instruction set.By the process periodicity of assessment algorithm, according to protocol timeslot structure, confirm ASIP work clock frequency
Rate, develops special ASIP on this basis.Compared with general dsp, the ASIP of this application specific architecture has with strong points, area
Little, hardware resource utilization advantages of higher.
According to satellite communications standards, during downlink reception, the data that radio frequency chip receives, enter thing by radio frequency chip interface
Reason layer subsystem, after decoding, enters protocol stack processor, and after the process of protocol stack processor, voice data passes through
After decoding, passing to audio output apparatus by audio interface and export, remainder data transfers to USB interface to pass to application processor.?
Inside baseband processor, mainly complete the frame synchronization process of downlink data, data are decoded, connects the operations such as rate-matched.
Fig. 5 indicates the handling process of satellite communication terminal baseband processor downlink reception data:
Step 1: upper layer information starts physical layer and receives process, starts timing control module simultaneously.
Step 2: judge whether timing controlled arrives communication benchmark and receive the time, if arriving, then opening radio frequency interface, receiving
Downlink data.Otherwise, proceed synchronization control, until arriving fiducial time.
Step 3: radio frequency interface module carries out interpolation, time-domain filtering etc. and processes data.
Step 4: the data that radio frequency interface has been processed by system DMA move ASIP internal storage to.
Step 5: use special downlink reception ASIP to carry out data process, completes synchronization, channel estimation, equilibrium, data
Demodulation, solution rate-matched function.
Step 6: data are transported to share memory module by system DMA, hardware accelerator module complete downlink reception
Remaining data decoding and verifying work.
In such scheme, by assessing the algorithm complex of downlink reception link, have employed ASIP and add hardware accelerator work
Mode for coprocessor completes downlink receiver.
Part that the present invention does not relate to is the most same as the prior art maybe can use prior art to be realized.
Claims (3)
1. a satellite communication mobile terminal base band processing system, including framework based on AXI bus, is characterized in that this framework is adopted
High-speed equipment interconnection is carried out, to realize concurrent full internet data and to control mutual with 32 system bus 1；And it is total by 32
Line 2 connects basic module and low-speed serial peripheral hardware, and is carried out system bus 1 and system bus 2 mutually by bus switching bridge
Connection, it is achieved the equipment that high-speed bus is interconnected can carry out data and control mutual basic module and low-speed serial peripheral hardware；Institute
State high-speed equipment to include radio frequency interface, system DMA, interior reception ASIP, launch ASIP, hardware accelerator, OpenRisc processor
Storage, MAC interface and sheet external memory interface is shared on core, sheet；Described basic module and low-speed serial peripheral hardware include clock circuit,
Reset, timing controlled, low power consumption control, intercore communication control, interrupt control, general-purpose interface and I2C/SPI/UART/I2S；Institute
State bus 1 and bus 2 is bus IP and has multiple main frame and from equipment interface, it is possible to multiple hardware modules are connected to one
Rise, it is achieved chip-on communication.
Satellite communication mobile terminal base band processing system the most according to claim 1, it is characterized in that described interior reception ASIP and
Launch ASIP and all include that kernel and subsystem, described kernel include program storage, instruction acquisition, instruction decoding, data path 0-7
Storing with data, the storage of its Program performs instruction for store ASIP；Instruction obtains for obtaining according to instruction address
ASIP performs instruction；Instruction decoding is after obtaining instruction, is decoded instruction, obtains concrete instruction format；Instruction
Execution is to perform to operate accordingly according to concrete instruction；The data that data path 0-7 is parallel during instruction performs are led to
Road；Data storage is to use RAM and CACHE form, the result that storage instruction performs；Described subsystem includes bus, bit wide
Join, the storage of kernel bag, data, register file, semaphore and directly access control, wherein bus is for carrying out outside ASIP
Data exchange, and support AMBA AXI protocol；Program storage has been the storage of the programmed instruction of kernel；Kernel bag is to provide kernel
Encapsulation and interface, state control, kernel example and JTAG TAP function；Data storage is to use RAM and CACHE form, complete
Become the data storage of kernel；Register file is to provide the form of depositor, it is provided that the outside software interactive interface to ASIP；Directly
The control controlling to be to provide the DMA to data access is asked in receiving.
3. an application process for satellite communication terminal band processing system described in claim 1, including up transmitting and descending
Receive, it is characterized in that the method for described up transmitting comprises the following steps:
A1. upper layer information starts physical layer emission process, starts timing control module simultaneously；
A2. chnnel coding by a special ASIP；
A3. after ASIP completes coding, radio frequency interface module the data after ASIP processes are read；
A4. radio frequency interface is shaped filtering and up-sampling operation to launching data；
A5. judge whether timing controlled arrives the benchmark transmission time of communication standard, open radio frequency interface after arrival, by data
Send, otherwise continue waiting for；
The method of described downlink reception comprises the following steps:
B1. upper layer information starts physical layer reception process, starts timing control module simultaneously；
B2. judge whether timing controlled arrives communication benchmark and receive the time, if arriving, then opens radio frequency interface, receives lower line number
According to, otherwise, proceed synchronization control, until arriving fiducial time；
B3. radio frequency interface module carries out interpolation to data and time-domain filtering processes；
B4. the data that radio frequency interface has been processed by system DMA move ASIP internal storage to；
B5. use special downlink reception ASIP to carry out data process, complete synchronization, channel estimation, equilibrium, data demodulation, solve
Rate-matched function；
B6. data are transported to share memory module by system DMA, hardware accelerator module complete the remaining number of downlink reception
According to decoding and verifying work.
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Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105871894A (en) * | 2016-05-17 | 2016-08-17 | 华南理工大学 | IEC61850 communication protocol conversion SOC chip with encryption and decryption functions and implementing method |
| CN109286597A (en) * | 2017-07-20 | 2019-01-29 | 北京中科晶上科技股份有限公司 | A kind of baseband chip |
| CN109408425A (en) * | 2018-12-27 | 2019-03-01 | 中科院计算技术研究所南京移动通信与计算创新研究院 | A kind of high speed magnanimity Flash memory module based on VPX |
| CN109932963B (en) * | 2019-01-29 | 2022-03-08 | 中国航空无线电电子研究所 | ADS-B system-level chip architecture based on DSP core |
| CN110071755A (en) * | 2019-04-26 | 2019-07-30 | 中国电子科技集团公司第五十四研究所 | A kind of satellite mobile communication radio frequency interface controller and radio frequency signal processing equipment |
| CN110738015B (en) * | 2019-09-10 | 2020-07-07 | 广东高云半导体科技股份有限公司 | System on chip and FPGA kernel information processing method thereof |
| CN110995750B (en) * | 2019-12-18 | 2021-09-28 | 展讯通信（上海）有限公司 | Terminal device |
| CN112134590B (en) * | 2020-09-22 | 2022-05-31 | 北京强云创新科技有限公司 | Satellite communication baseband chip structure |
| CN112148651B (en) * | 2020-10-10 | 2022-05-03 | 中国人民解放军国防科技大学 | Enhanced rapidio interconnection device and equipment |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102063337A (en) * | 2009-11-17 | 2011-05-18 | 中兴通讯股份有限公司 | Method and system for information interaction and resource distribution of multi-processor core |
| CN202189147U (en) * | 2011-04-19 | 2012-04-11 | 中国电子科技集团公司第五十四研究所 | Multimode navigation information terminal SoC (system on chip) chip integrating multiple IP cores |
-
2013
- 2013-10-25 CN CN201310508570.7A patent/CN103581070B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102063337A (en) * | 2009-11-17 | 2011-05-18 | 中兴通讯股份有限公司 | Method and system for information interaction and resource distribution of multi-processor core |
| CN202189147U (en) * | 2011-04-19 | 2012-04-11 | 中国电子科技集团公司第五十四研究所 | Multimode navigation information terminal SoC (system on chip) chip integrating multiple IP cores |
Non-Patent Citations (5)
| Title |
|---|
| "SoC片上系统总线分析与研究_";时伟等;《电子世界》;20120330;第20-21页 * |
| "一种支持高效互连网络的ASIP设计方法";赵学秘等;《第十四届计算机辅助设计与图形学学术会议论文集》;20070723;第167-175页 * |
| "基于AMBA3_0的AXI转接桥的设计与实现_ （2011-08-12";曾思等;《第十五届计算机工程与工艺年会暨第一届微处理器技术论坛论文集（A辑）》;20110812;第327-331页 * |
| "基于AMBA总线的UARTIP设计与实现";徐云云;《中国优秀硕士学位论文全文数据库信息科技辑》;20120515;第I135-192页 * |
| "基于AXI总线的DMA控制器的研究与设计";季顺南;《中国优秀硕士学位论文全文数据库信息科技辑》;20110315;第I135-179页 * |
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