CN103581070A - Satellite communication mobile terminal base band processing system and application method thereof - Google Patents
Satellite communication mobile terminal base band processing system and application method thereof Download PDFInfo
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Abstract
The invention relates to a satellite communication mobile terminal base band processing system. The satellite communication mobile terminal base band processing system comprises a framework based on an AXI bus, wherein the framework adopts a 32-digit system bus I for interconnection of high-speed devices in order to achieve concurrent fully-meshed data and control interaction, a basic module and a low-speed serial peripheral are connected through a 32-digit bus II, the system bus I and the system II are connected through a bus through-connection bridge, and the devices connected with a high-speed bus can carry out data and control interaction on the basic module and the low-speed serial peripheral. The satellite communication mobile terminal base band processing system is reasonable in design, is simple in structure, is clear in process, and solves the problems of multi-core interconnection and vane interconnection. Compared with a design of the field in the prior art, a chip is stronger in pertinence, smaller in size, and lower in power consumption. Meanwhile, a bus interface module based on a reusable IP is adopted to carry out interconnection of hardware modules, flexibility is increased, cost is lowered, and design risks are lowered.
Description
Technical field
The present invention relates to wireless communication technology field, especially a kind of band processing system, specifically a kind of satellite communication terminal band processing system.
The invention still further relates to a kind of method of applied satellite communication terminal band processing system.
Background technology
At present, in a satellite communication system, user terminal provides the function of obtaining service from the interface of satellite system.Baseband processor is the most crucial part of user terminal, is mainly used to transmit and receive baseband signal.During transmitting, audio signal or application processor data compilation are become to be used for the base band code of transmitting; During reception, the base band code of receiving is interpreted as to audio signal or application processor data.Need to complete upstream transmitter and comprise the operations such as chnnel coding, modulation, molding filtration, timed sending, need downlink receiver function to comprise the operations such as processing before frame synchronization, demodulation, rate de-matching, decoding simultaneously.Due to complex disposal process, baseband chip is being had relatively high expectations aspect speed, disposal ability, power consumption.
Traditional terminal baseband chip adopts a general dsp to complete physical layer base band signal process, processes in addition in conjunction with a CPU as arm processor completes protocol stack, adopts the mode of the more additional bus bridges of static memory to complete structure connection between the two.Along with scientific and technological progress and application demand growing, satellite communication system requires higher data-handling capacity and lower power consumption.Adopt the framework of a general dsp and a CPU can not meet application needs.So multicore architecture is born, adopting a plurality of general dsp core is the main flow design architecture of current baseband chip in conjunction with an above arm processor mode.But this framework can be introduced new problem, due to the continuous increase of core, the connection communication problem between different IPs is day by day remarkable.Meanwhile, bring larger pressure also can to bus and storage system, power consumption also can increase thereupon.In addition, general dsp compatibility the functional module of current mainstream technology scheme, be applied in specific standard agreement mobile terminal and certainly exist a large amount of redundancy logics, thereby increase system area and power consumption, also can increase cost simultaneously.
Summary of the invention
The object of this invention is to provide a kind of the deficiencies in the prior art that overcome, can eliminate redundancy logic, reduce satellite communication terminal band processing system and the application process thereof of chip area and power consumption.
Technical scheme of the present invention is:
A mobile terminal baseband treatment system, comprises the framework based on AXI bus, and it is interconnected that 32 system buss 1 of this framework employing carry out high-speed equipment, to realize concurrent full internet data and to control mutual; And connect basic module and low-speed serial peripheral hardware by 32 buses 2, and by bus switching bridge, system bus 1 and system bus 2 are carried out interconnectedly, realize the interconnected equipment of high-speed bus and can carry out data and control mutual basic module and low-speed serial peripheral hardware; Described high-speed equipment comprises on radio frequency interface, system DMA, interior reception ASIP, transmitting ASIP, hardware accelerator, OR processor core, sheet shares storage, MAC interface and sheet external memory interface; Described basic module and low-speed serial peripheral hardware comprise clock circuit, reset, timing controlled, low power consumption control, internuclear Control on Communication, interrupt control, general-purpose interface and I2C/SPI/UART/I2S.
Described interior reception ASIP and transmitting ASIP include kernel and subsystem, and described kernel comprises that program storage, instruction are obtained, instruction decoding, data path 0-7 and data storage, its Program storage execution instruction for storing ASIP; Instruction is obtained for obtain the execution instruction of ASIP according to instruction address; Instruction decoding is after obtaining instruction, and instruction is decoded, and obtains concrete command format; It is to carry out corresponding operation according to concrete instruction that instruction is carried out; Data path 0-7 is data channel parallel in execution process instruction; Data storage is to adopt RAM and CACHE form, the result that storage instruction is carried out; Described subsystem comprises bus, bit wide coupling, kernel bag, data storage, register file, semaphore and directly access control, and wherein bus, for carrying out exchanges data with ASIP outside, is supported AMBA AXI agreement; Program storage has been the storage of the program command of kernel; Kernel bag is to provide encapsulation and interface, state control, kernel exampleization and the JTAG TAP function of kernel; Data storage is to adopt RAM and CACHE form, completes the data storage of kernel; Register file is to provide the form of register, and the outside software interactive interface to ASIP is provided; Directly access control is to provide the control to the DMA of data access.
Described bus structures are that a bus IP has a plurality of main frames and from equipment interface, a plurality of hardware modules can be linked together, and realize chip-on communication.
Described OR processor has special purpose interface, better to realize the on-chip interconnect that is connected processor, memory and peripheral module with bus.
Native system is provided with independent clock control module, realizes dynamic clock frequency adjustment and idle mode functionality.
A method for above-mentioned satellite communication terminal band processing system application, comprises up transmitting and descending reception, it is characterized in that the method for described up transmitting comprises the following steps:
A1. upper layer information starts physical layer emission process, starts timing control module simultaneously; ;
A2. by a special-purpose ASIP, start chnnel coding;
A3. ASIP completes after coding, by radio frequency interface module, reads the data after ASIP processes;
A4. radio frequency interface carries out the operations such as molding filtration, up-sampling to transmitting data;
A5. judge whether timing controlled arrives the benchmark transmitting time of communication standard, opens radio frequency interface after arrival, and data are sent, otherwise continue to wait for;
Described descending receiving method comprises the following steps:
B1. upper layer information starts physical layer receiving course, starts timing control module simultaneously;
B2. judge whether timing controlled arrives communication benchmark time of reception, if arrive, opens radio frequency interface, downlink data receiving, otherwise, proceed synchronous adjustment, until arrive fiducial time;
B3. radio frequency interface module is carried out the processing such as interpolation, time-domain filtering to data;
B4. the data that system DMA is handled radio frequency interface are moved ASIP internal storage to;
B5. adopt special-purpose descending receptions ASIP to carry out data processing, complete synchronously, channel estimating, equilibrium, data demodulates, rate de-matching function;
B6. system DMA, by data conveyance to shared storage module, completes the remaining data decoding of descending reception and verifying work by hardware accelerator module.
Beneficial effect of the present invention:
The present invention is reasonable in design, simple in structure, flow process is clear, has solved a difficult problem for multinuclear interconnection and on-chip interconnect, compares the design of this field existing level, chip specific aim is stronger, area is less, and power consumption is lower, has adopted based on the reusable bus interface module of IP simultaneously and has carried out hardware module interconnection, increase flexibility, reduced costs and designed risk.
Accompanying drawing explanation
Fig. 1 is configuration diagram of the present invention.
Fig. 2 is ASIP kernel micro-structural schematic diagram of the present invention.
Fig. 3 is ASIP memory access subsystem structure schematic diagram of the present invention.
Fig. 4 is the up transmitting chain schematic flow sheet of the present invention.
Fig. 5 is the descending receiver schematic flow sheet of the present invention.
Fig. 6 is bus structures schematic diagram of the present invention.
Fig. 7 is OR interface switching schematic diagram of the present invention.
Embodiment
Below in conjunction with drawings and Examples, the present invention is further illustrated.
As shown in Figure 1, system provided by the invention adopts the framework based on AXI bus, it is interconnected that 32 system buss 1 of this framework employing carry out high-speed equipment, these interconnected equipment comprise on radio frequency interface, system DMA, interior reception ASIP, transmitting ASIP, hardware accelerator, OR processor core, the sheet that connects radio frequency chip shares storage, MAC interface, sheet external memory interface, can realize concurrent complete interconnected data and control alternately between these interconnected equipment.Simultaneously, this framework comes basic module and low-speed serial peripheral hardware on brace by 32 buses 2, comprise clock circuit, reset, timing controlled, low power consumption control, internuclear Control on Communication, interrupt other Serial Peripheral Interface (SPI)s such as control, general-purpose interface and I2C/SPI/UART/I2S, and, the high speed interconnection of this framework and low speed bus are directly undertaken interconnected by bus switching bridge, realize the interconnected equipment of system bus 1 and can carry out data and control mutual basic module and low-speed serial peripheral hardware.
Described ASIP comprises two kinds, and a kind of ASIP realizes inner receiver function, mainly comprises synchronous, channel estimating, equilibrium, demodulation, descrambling, connects rate-matched, RS/Golay decoding, folding coding, CRC check etc.Another kind is to realize transmitter function, comprises control channel coding and data channel coding.ASIP instruction set is developed for satellite communication mobile terminal baseband Processing Algorithm demand, and structure is pointed, and irredundant hardware consumption resource is used in conjunction with coprocessor, makes whole hardware resource optimization.By balanced algorithm complexity and hardware resource consumption, coprocessor mainly completes the more complicated decoding algorithm part in descending receiver.
Described ASIP is divided into kernel and subsystem two parts, and wherein the micro-structural of kernel as shown in Figure 2, is divided into:
Program storage (Program Memory): the execution instruction that is used for storing ASIP;
(Instruction Fetch) obtained in instruction: be used for obtaining according to instruction address the execution instruction of ASIP;
Instruction decoding (Instruction Decode): obtain after instruction, instruction is decoded, obtain concrete command format etc.;
(Instruction Issue) carried out in instruction: according to concrete instruction, carry out corresponding operating;
Data path 0 ~ 7(data path0 ~ 7): parallel data channel in execution process instruction;
Data storage (Data Memory): be used for storing the storage of the result that instruction carries out;
The structure of subsystem as shown in Figure 3, comprising:
Bus (AXI BUS): be used for carrying out with ASIP outside the module of data interaction, support AMBA AXI agreement;
Bit wide coupling (Width Match): complete mating of data bit width between bus module and inside;
Program storage (pm_ram, I Cache): complete the storage of the program command of kernel, adopt the form of RAM and CACHE;
Kernel bag (Core Wrapper, State Control, MT core, JTAG_TAP): encapsulation and the interface of kernel are provided, state control, kernel exampleization, JTAG TAP function are provided;
Data storages (dm_ram, D Cache): complete the storage of the data of kernel, adopt the form of RAM and CACHE;
Register file (Register File): provide the outside software interactive interface to ASIP, by the form of register;
Semaphore (semiphore): provide and outside hardware interactive interface, by the mode of semaphore;
Directly access control (DMA control): the DMA control mode to outside data access is provided;
The present invention coordinates the use of the distinct interface modules such as external memory interface, internuclear communications interface unit, general Peripheral Interface, radio frequency interface, between the external modules such as support and application processor, outside other functional chips, radio frequency chip, communicates by letter.Coordinate bus to connect, complete whole terminal communication process, solve chip interconnect problem.For general-purpose interface, adopt the reusable design of IP.Independent development radio frequency interface, complete the functions such as filtering and upper down-sampling, and multiple interfaces agreement be provided.
For the modules in such scheme, developed specially bus cross bar switch, dissimilar connection-bridge, form physics straton system hardware intermodule communication system, solve SoC on-chip interconnect problem.Simultaneously, applied the OpenRisc(OR opening for free) processor realizes system and controls, and carried out reseting meter for interface: change the original wishbone bus interface of OR processor, adopt more general interface standard, to realize, be connected processor, memory with bus, other realize better on-chip interconnect such as DSP and peripheral module.By intermodule shared storage, to reduce memory space, reduce area and the power consumption of terminal baseband processor.Coordinate the use of top layer DMA and inside modules read-write DMA, flexible design.
Described bus structures take standardization IP module to realize, and as shown in Figure 6, a bus IP has a plurality of main frames and from equipment interface, a plurality of hardware modules can be linked together, and realizes chip-on communication.Different bus protocol interface standard is different, and the data-handling capacity providing is difference to some extent also, therefore according to the different demands of actual data throughput, selects different bus types, reduces hardware consumption.For the inconsistent intermodule communication of bus interface standards, adopt bus switching bridge to connect.Bus switching bridge is by the data interaction completing between dissimilar bus interface module.Take OR module as example, and as Fig. 7, the standard interface of OR module is wishbone interface, and this class interface is more rare in design, and other modules are not almost used.Adopt dissimilar bridge module that OR module interface is converted to and other module accordant interface 2 types, the data interaction conveniently and between other hardware modules, reduces to design cost, increases design flexibility.
The present invention also provides independent clock control module, first, for the few module of amount of calculation, adopts low-frequency clock, finally reaches between the different IPs with data interaction the deadline substantially the same.By reducing the clock frequency of part of module, reduce the power consumption of whole design.Secondly, whole design is adopted to a mode of operation switch, when not working, chip enters sleep state, all modules quit work, and after sleep a period of time, by reshuffling switch, recover normal operating conditions, realize the functions such as dynamic clock frequency adjustment, idle pulley, reduce baseband processor power consumption.
The present invention also provides a kind of application process of this treatment system, comprises up transmitting and descending reception.According to satellite communications standards, during up transmitting, data after application processor data or audio coding decoding, by the processing of protocol stack processor, the interface being provided by baseband processor, is transferred to physical layer subsystem, after coding, by radio frequency chip interface, pass to radio frequency chip, then launch.In baseband processor inside, mainly complete the chnnel coding of data.Fig. 4 has shown the handling process of the up transmitting data of baseband processor:
Step 1:MAC layer provides physical layer configurations information, starts physical layer transmitter, starts timing control module simultaneously.
Step 2: start chnnel coding by a special-purpose ASIP.
Step 3:ASIP completes after coding, by radio frequency interface module, reads the data after ASIP processes.
Step 4: radio frequency interface carries out the operations such as molding filtration, up-sampling to transmitting data.
Step 5: judge whether timing controlled arrives the benchmark transmitting time of communication standard, opens radio frequency interface after arrival, and data are sent, otherwise continue to wait for.
Such scheme is according to satellite communication agreement, acknowledgement channel coding maximum amount of data, and according to algorithm structure, customization ASIP structure and instruction set.By the treatment cycle number of assessment algorithm, according to agreement structure of time slot, confirm ASIP working clock frequency, develop on this basis special-purpose ASIP.Compare with general dsp, the ASIP of this application specific architecture pointed strong, area is little, hardware resource utilization advantages of higher.
According to satellite communications standards, during descending reception, the data that radio frequency chip receives, by radio frequency chip interface, enter physical layer subsystem, after decoding, enter protocol stack processor, after the processing of protocol stack processor, voice data, after decoding, is passed to audio output apparatus by audio interface and is exported, and remainder data transfers to USB interface to pass to application processor.In baseband processor inside, mainly complete the frame synchronization process of downlink data, data are carried out decoding, connect the operations such as rate-matched.Fig. 5 has shown the handling process of the descending reception data of satellite communication terminal baseband processor:
Step 1: upper layer information starts physical layer receiving course, starts timing control module simultaneously.
Step 2: judge that whether timing controlled arrives communication benchmark time of reception, if arrive, opens radio frequency interface, downlink data receiving.Otherwise, proceed synchronous adjustment, until arrive fiducial time.
Step 3: radio frequency interface module is carried out the processing such as interpolation, time-domain filtering to data.
Step 4: the data that system DMA is handled radio frequency interface are moved ASIP internal storage to.
Step 5: adopt special-purpose descending receptions ASIP to carry out data processing, complete synchronously, channel estimating, equilibrium, data demodulates, rate de-matching function.
Step 6: system DMA to shared storage module, completes descending reception remaining data decoding and verifying work by hardware accelerator module by data conveyance.
In such scheme, by assessing the algorithm complex of descending receiver, adopted ASIP to add hardware accelerator and completed downlink receiver as the mode of coprocessor.
The part that the present invention does not relate to all prior art that maybe can adopt same as the prior art is realized.
Claims (6)
1. a satellite communication mobile terminal baseband treatment system, comprises the framework based on AXI bus, it is characterized in that this framework adopts 32 system buss 1 to carry out high-speed equipment interconnected, to realize concurrent full internet data and to control mutual; And connect basic module and low-speed serial peripheral hardware by 32 buses 2, and by bus switching bridge, system bus 1 and system bus 2 are carried out interconnectedly, realize the interconnected equipment of high-speed bus and can carry out data and control mutual basic module and low-speed serial peripheral hardware; Described high-speed equipment comprises on radio frequency interface, system DMA, interior reception ASIP, transmitting ASIP, hardware accelerator, OR processor core, sheet shares storage, MAC interface and sheet external memory interface; Described basic module and low-speed serial peripheral hardware comprise clock circuit, reset, timing controlled, low power consumption control, internuclear Control on Communication, interrupt control, general-purpose interface and I2C/SPI/UART/I2S.
2. satellite communication mobile terminal baseband treatment system according to claim 1, it is characterized in that described interior reception ASIP and transmitting ASIP include kernel and subsystem, described kernel comprises that program storage, instruction are obtained, instruction decoding, data path 0-7 and data storage, its Program storage execution instruction for storing ASIP; Instruction is obtained for obtain the execution instruction of ASIP according to instruction address; Instruction decoding is after obtaining instruction, and instruction is decoded, and obtains concrete command format; It is to carry out corresponding operation according to concrete instruction that instruction is carried out; Data path 0-7 is data channel parallel in execution process instruction; Data storage is to adopt RAM and CACHE form, the result that storage instruction is carried out; Described subsystem comprises bus, bit wide coupling, kernel bag, data storage, register file, semaphore and directly access control, and wherein bus, for carrying out exchanges data with ASIP outside, is supported AMBA AXI agreement; Program storage has been the storage of the program command of kernel; Kernel bag is to provide encapsulation and interface, state control, kernel exampleization and the JTAG TAP function of kernel; Data storage is to adopt RAM and CACHE form, completes the data storage of kernel; Register file is to provide the form of register, and the outside software interactive interface to ASIP is provided; Directly access control is to provide the control to the DMA of data access.
3. satellite communication mobile terminal baseband treatment system according to claim 1, is characterized in that described bus structures are that a bus IP has a plurality of main frames and from equipment interface, a plurality of hardware modules can be linked together, and realize chip-on communication.
4. satellite communication mobile terminal baseband treatment system according to claim 1, is characterized in that described OR processor has special purpose interface, better to realize the on-chip interconnect that is connected processor, memory and peripheral module with bus.
5. satellite communication mobile terminal baseband treatment system according to claim 1, is characterized in that native system is provided with independent clock control module, realizes dynamic clock frequency adjustment and idle mode functionality.
6. an application process for satellite communication terminal band processing system described in claim 1, comprises up transmitting and descending reception, it is characterized in that the method for described up transmitting comprises the following steps:
A1. upper layer information starts physical layer emission process, starts timing control module simultaneously; ;
A2. by a special-purpose ASIP, start chnnel coding;
A3. ASIP completes after coding, by radio frequency interface module, reads the data after ASIP processes;
A4. radio frequency interface carries out the operations such as molding filtration, up-sampling to transmitting data;
A5. judge whether timing controlled arrives the benchmark transmitting time of communication standard, opens radio frequency interface after arrival, and data are sent, otherwise continue to wait for;
Described descending receiving method comprises the following steps:
B1. upper layer information starts physical layer receiving course, starts timing control module simultaneously;
B2. judge whether timing controlled arrives communication benchmark time of reception, if arrive, opens radio frequency interface, downlink data receiving, otherwise, proceed synchronous adjustment, until arrive fiducial time;
B3. radio frequency interface module is carried out the processing such as interpolation, time-domain filtering to data;
B4. the data that system DMA is handled radio frequency interface are moved ASIP internal storage to;
B5. adopt special-purpose descending receptions ASIP to carry out data processing, complete synchronously, channel estimating, equilibrium, data demodulates, rate de-matching function;
B6. system DMA, by data conveyance to shared storage module, completes the remaining data decoding of descending reception and verifying work by hardware accelerator module.
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| CN105871894A (en) * | 2016-05-17 | 2016-08-17 | 华南理工大学 | IEC61850 communication protocol conversion SOC chip with encryption and decryption functions and implementing method |
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| CN109408425A (en) * | 2018-12-27 | 2019-03-01 | 中科院计算技术研究所南京移动通信与计算创新研究院 | A kind of high speed magnanimity Flash memory module based on VPX |
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| CN110738015A (en) * | 2019-09-10 | 2020-01-31 | 广东高云半导体科技股份有限公司 | System on chip and FPGA kernel information processing method thereof |
| CN110995750A (en) * | 2019-12-18 | 2020-04-10 | 展讯通信（上海）有限公司 | Terminal device |
| CN112134590A (en) * | 2020-09-22 | 2020-12-25 | 北京德科信科技有限公司 | Novel satellite communication baseband chip structure |
| CN112148651A (en) * | 2020-10-10 | 2020-12-29 | 中国人民解放军国防科技大学 | Enhanced rapidio interconnection device and equipment |
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