CN110738015B - System on chip and FPGA kernel information processing method thereof - Google Patents
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Abstract
The invention discloses a system on a chip and an FPGA kernel information processing method thereof, wherein the method comprises the following steps: decoding bus information sent by the MCU kernel; decoding an addressing parameter in the address bus information; acquiring bus clock frequency and bus bit width information in the decoded bus information, and outputting the acquired bus clock frequency, bus bit width information and addressing parameters to a layout and wiring design module; and informing the optimal time sequence wiring path output by the layout and wiring design module to the MCU kernel through a bus. According to the invention, the optimal time sequence wiring path of the FPGA kernel matched with the MCU kernel is output by automatically identifying the MCU kernel bus information, and wiring is carried out according to the optimal time sequence wiring path, so that the wiring efficiency is improved, the interconnection time sequence of the MCU kernel and the FPGA kernel is improved, the chip power consumption is reduced, and the performance requirement of the interconnection communication between the MCU kernel and the FPGA kernel is met.
Description
Technical Field
The invention relates to the technical field of semiconductor chips, in particular to a system on chip and an FPGA kernel information processing method thereof.
Background
At present, as the semiconductor industry enters the era of ultra-deep submicron and nano processing, it is a necessary development trend to realize a complex electronic System on a single integrated circuit kernel, SoC (System on Chip) is more and more widely used, in the prior art, the System on Chip is an FPGA (Field Programmable Gate Array) kernel connecting an MCU (micro controller Unit) kernel, a memory, an external device and the like, and further leading out a bus (a common communication trunk for transmitting information between different devices), and bus wiring is performed inside the FPGA kernel, and due to the limitations of Gate Array arrangement, software model layout, Chip area and the like of the FPGA kernel, the problems of different wiring lengths and unbalanced wiring resources in the kernel and the like are caused, and further, timing and power consumption cannot completely satisfy the interconnection communication between the MCU kernel and the FPGA kernel, and moreover, bus information is manually identified and input into wiring software according to the requirements of MCU kernels with different architectures, so that the wiring efficiency is reduced due to input errors easily.
Disclosure of Invention
The invention provides a system on a chip and an FPGA kernel information processing method thereof, which output an optimal time sequence wiring path of an FPGA kernel matched with the MCU kernel by automatically identifying MCU kernel bus information and perform wiring according to the optimal time sequence wiring path, thereby improving wiring efficiency, improving the interconnection time sequence of the MCU kernel and the FPGA kernel, reducing chip power consumption and meeting the performance requirement of the interconnection communication of the MCU kernel and the FPGA kernel.
The system on a chip comprises an MCU (microprogrammed control Unit) core and an FPGA (field programmable gate array) core, wherein the FPGA core is in communication connection with the MCU core through a bus; the FPGA kernel comprises an FPGA bus software module and at least one FPGA soft core;
the FPGA bus software module receives bus information sent by the MCU kernel, decodes the bus information, acquires address bus information in the decoded bus information, decodes addressing parameters in the address bus information, outputs bus clock frequency and bus bit width information in the decoded bus information and the addressing parameters to the layout and wiring design module, receives an optimal time sequence wiring path output by the layout and wiring design module, and informs the MCU kernel of the optimal time sequence wiring path.
An FPGA kernel information processing method of a system on a chip comprises the following steps:
the method comprises the steps of receiving bus information sent by an MCU kernel, decoding the bus information, obtaining address bus information in the decoded bus information, decoding addressing parameters in the address bus information, outputting bus clock frequency and bus bit width information in the decoded bus information and the addressing parameters to a layout and wiring design module, receiving an optimal time sequence wiring path output by the layout and wiring design module, and informing the MCU kernel.
The invention discloses a system on chip and an FPGA kernel information processing method thereof.A bus message sent by an MCU kernel is received, the bus message is decoded to obtain an address bus message in the decoded bus message, an addressing parameter in the address bus message is decoded, a bus clock frequency, the bus bit width message and the addressing parameter in the decoded bus message are output to a layout and wiring design module, and an optimal time sequence wiring path output by the layout and wiring design module is received and notified to the MCU kernel. According to the invention, the optimal time sequence wiring path of the FPGA kernel matched with the MCU kernel is output by automatically identifying the MCU kernel bus information, and wiring is carried out according to the optimal time sequence wiring path, so that the wiring efficiency is improved, the interconnection time sequence of the MCU kernel and the FPGA kernel is improved, the chip power consumption is reduced, and the performance requirement of the interconnection communication between the MCU kernel and the FPGA kernel is met.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments of the present invention will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art that other drawings can be obtained according to these drawings without inventive labor.
FIG. 1 is a flow chart of a method for processing FPGA kernel information of a system-on-chip according to an embodiment of the present invention;
FIG. 2 is a flowchart of step S10 of the FPGA kernel information processing method of the system on a chip according to an embodiment of the present invention;
FIG. 3 is a flowchart of step S20 of the FPGA kernel information processing method of the system on a chip according to an embodiment of the present invention;
FIG. 4 is a functional block diagram of a system-on-chip in an embodiment of the invention;
FIG. 5 is a functional block diagram of a decoder in an FPGA core of a system-on-chip in an embodiment of the present invention;
FIG. 6 is a functional block diagram of a decoder in an FPGA core of a system-on-chip according to an embodiment of the present invention;
FIG. 7 is a diagram illustrating a system on a chip interfacing with an external computer device, in accordance with an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The invention provides a system on chip (1), which outputs an optimal time sequence wiring path of an FPGA (field programmable gate array) kernel (3) matched with an MCU kernel (2) by automatically identifying bus information of the MCU kernel (2) kernel, and performs wiring according to the optimal time sequence wiring path, thereby improving wiring efficiency, improving the interconnection time sequence of the MCU kernel (2) kernel and the FPGA kernel (3), reducing chip power consumption and meeting the performance requirement of interconnection communication of the MCU kernel (2) kernel and the FPGA kernel (3).
The FPGA kernel 3 information processing method of the system on chip 1 can be applied to the system on chip 1, as shown in FIG. 4, the system on chip comprises an MCU kernel and an FPGA kernel, and the FPGA kernel is in communication connection with the MCU kernel through a bus; the FPGA kernel 3 information processing method of the system on chip 1 comprises the steps that the FPGA bus software module receives bus information sent by an MCU kernel, decodes the bus information, acquires address bus information in the decoded bus information, decodes addressing parameters in the address bus information, outputs bus clock frequency, bus bit width information and the addressing parameters in the decoded bus information to a layout and wiring design module, receives an optimal time sequence wiring path output by the layout and wiring design module and informs the MCU kernel.
In an embodiment, as shown in fig. 1 and 4, the FPGA bus software module receives bus information sent by an MCU core, decodes the bus information, obtains address bus information in the decoded bus information, decodes addressing parameters in the address bus information, outputs bus clock frequency and bus bit width information in the decoded bus information and the addressing parameters to a placement and routing design module, receives an optimal timing routing path output by the placement and routing design module, and notifies the MCU core, including the following steps S10-S40:
and S10, the decoder 31 receives the bus information sent by the MCU kernel 2 and decodes the bus information.
Understandably, the bus information sent by the MCU core 2 to the FPGA core 3 is received by the decoder 31 shown in fig. 7, and includes address bus information, data bus information, and control bus information. Correspondingly, the system on chip 1 includes an MCU core 2 and an FPGA core 3 connected by a bus, and the bus includes three bus types of an address bus 6, a data bus 7 and a control bus 8, where the address bus 6 is used to transmit address information for storing data information to a designated unit, and may also be understood as forming a group of wire harnesses by all address signal transmission lines in the MCU core 2, the data bus 7 is used to transmit data information, and may also be understood as forming a group of wire harnesses by all data signal transmission lines in the MCU core 2, and the control bus 8 is used to transmit control information such as control signals and timing signals of the MCU core 2, and may also be understood as forming a group of wire harnesses by all control signal transmission lines in the MCU core 2, such as: interrupt response signals, chip select signals, reset signals, etc.
The bus information sent by the MCU core 2 to the FPGA core 3 further includes a clock frequency, where the clock frequency refers to a fundamental frequency of a clock in the circuit, such as: 5MHz, 12MHz, 35MHz, etc.
Understandably, the decoder 31 decodes the bus information, that is, analyzes information such as address bus information, data bus information, control bus information, clock frequency, and the like from the bus information, and further determines bus clock frequency and bus bit width information according to the information, where the bus bit width information includes bus types (for example, an address bus 6 type, a data bus 7 type, and a control bus 8 type) included in the bus information and bus bit width parameters (including an address bus bit width parameter, a data bus bit width parameter, and a control bus bit width parameter) corresponding to each of the bus types.
Specifically, the interface of the FPGA core 3 is scanned in real time, where the interface of the FPGA core 3 includes an address interface, a data interface, a control interface, and a clock line of the MCU core 2 is connected to the clock interface of the FPGA core 3 (specifically, bus information received from the clock interface is analyzed and a clock frequency is obtained, and then the obtained clock frequency is marked as a bus clock frequency).
All address signal transmission lines of the MCU kernel 2 are connected to an address interface of the FPGA kernel 3, all data signal transmission lines of the MCU kernel 2 are connected to a data interface of the FPGA kernel 3, all control signal transmission lines of the MCU kernel 2 are connected to a control interface of the FPGA kernel 3, each bus type corresponding to bus information output by the MCU kernel 2 is determined by identifying the interface of the FPGA kernel 3, and then bus information (including address bus information, data bus information and control bus information) received from the interface corresponding to each bus type is analyzed and corresponding bus bit width parameters are determined. The bus bit width parameter includes an address bus bit width parameter, a data bus bit width parameter, and a control bus bit width parameter, where the bus bit width parameter refers to the number of bits of binary data that can be simultaneously transmitted by a bus, that is, how many same bus type wire harnesses are in a bus transmission primary instruction, such as: the method comprises the steps that 32-bit binary data are simultaneously transmitted on an address bus 6 in bus information, namely 32 address lines are connected to transmit address signals, the bit width parameter of the address bus is analyzed and determined to be 32 bits, 16-bit binary data are simultaneously transmitted on a data bus 7 in the bus information, it is determined that 16 data lines are connected to transmit data signals, the bit width parameter of the data bus is determined to be 16 bits, 5-bit binary data are simultaneously transmitted on a control bus 8 in the bus information, namely 5 control lines are connected to transmit control signals, and the bit width parameter of the control bus is determined to be 5 bits through analysis.
S20, the decoder 32 obtains address bus information in the decoded bus information, and decodes the addressing parameter in the address bus information.
Understandably, the decoder 32 shown in fig. 7 is used to obtain address bus information in the bus information decoded by the decoder 31, and decode addressing parameters in the address bus information, where the addressing parameters include all source addresses in the address bus information and destination addresses of all FPGA soft cores 33 associated with the address bus information, the source addresses are address bus information in the bus information sent by the MCU core 2, the bit number is determined according to the address bus bit width parameter, and the bit number is composed of binary "0" (low level) or "1" (high level), and includes a start address and an end address, where the start address is a start address of all source addresses, i.e. a first source address, and the end address is a last source address of all source addresses, for example: the address bus bit width parameter is 4 bits, the start address is 0000, and the end address is 1111, so all source addresses are 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111.
As shown in fig. 7, the FPGA core 3 includes at least one FPGA soft core 33, one FPGA soft core 33 includes one register 331, the register 331 has a register 331 address composed of binary bits of preset number of bits, the register 331 includes an address depth and a data width, the address depth is the number of addresses stored in the register 331, the data width is the bit width of data stored in the register 331, according to the address depth and the data width of each FPGA soft core 33 and the data bus bit width parameter (obtained from the data bus information in the bus information after decoding), preferably, the data width is consistent with the data bus parameter, at this time, all source addresses are segmented, and each segment in the source addresses is connected and mapped to a destination address of one FPGA soft core 33, that is, the source address in a continuous range is connected and mapped to the register 331 address of one FPGA soft core 33 In conjunction with this, the address of the register 331 of the FPGA soft core 33 associated with the source address is further marked as the destination address of the FPGA soft core 33, and understandably, a segment of source address is associated with the destination address of one FPGA soft core 33, for example: in the above example, if the address of the register 331 of the first FPGA soft core 33 is 00000001, the address depth of the register 331 is 3, the data width of the register 331 is 16 bits, and the data bus bit width parameter is 16 bits, 00000001 is marked as the destination address of the FPGA soft core 33 and is associated with one of the source addresses 0000, 0001, and 0010 (the first three of all the source addresses).
The decoder 32 sends all source addresses in the address bus information and the destination addresses of all the FPGA soft cores 33 associated with the address bus information to the timing analyzer 34 shown in fig. 7, and sends a control signal containing the destination addresses of the FPGA soft cores 33 to the multiplexer 36 shown in fig. 7, so as to control and select the corresponding FPGA soft cores 33.
S30, the timing analyzer 34 obtains the bus clock frequency and the bus bit width information in the decoded bus information, and outputs the bus clock frequency, the bus bit width information, and the addressing parameter to a layout and routing design module.
Preferably, the bus bit width information includes bus types included in the bus information and bus bit width parameters corresponding to the bus types, and the bus types include an address bus 6, a data bus 7 and a control bus 8; the bus bit width parameters include address bus bit width parameters, data bus bit width parameters, and control bus bit width parameters, the placement and routing design module is a model preset in an external computer device 4 connected to the timing analyzer 34 shown in fig. 7, the placement and routing design module includes a routing algorithm and a timing algorithm, that is, a computer program capable of implementing functions of the placement and routing design module according to the routing algorithm and the timing algorithm (that is, the routing algorithm can determine all possible routing paths from the MCU core 2 to the FPGA soft core 33 according to each parameter in the input placement and routing design module, and the timing algorithm can determine an optimal timing routing path from the path with the least timing delay in all paths according to each parameter in the input placement and routing design module) is preset in the external computer device 4, wherein the timing analyzer 34 acquires bus clock frequency parameters in the bus information decoded by the decoder 31 The bus clock frequency, the bus type, the bus bit width parameter, all source addresses in the address bus information, and destination addresses of all FPGA soft cores 33 associated with the address bus information are output to the placement and routing design module, and are processed by a routing algorithm and a timing algorithm of the placement and routing design module to calculate and output the following optimal timing routing path under the condition of the bus clock frequency, the bus type, the bus bit width parameter, all source addresses in the address bus information, and the destination addresses of all FPGA soft cores 33 associated with the address bus information.
S40, the receiving module 35 receives the optimal timing wiring path output by the layout and wiring design module, and notifies the MCU core 2 of the optimal timing wiring path through the bus 5.
Understandably, after receiving the optimal timing wiring path output by the place and route design module through the receiving module 35 shown in fig. 7 (where the format of the optimal timing wiring path output by the place and route design module is a file format supporting the FPGA core 3 to execute wiring), the receiving module 35 notifies the MCU core 2 through the bus 5 that the optimal timing wiring path has been received, and then the FPGA core 3 may perform a wiring operation according to the wiring instruction fed back by the MCU core 2 and the optimal timing wiring path.
According to the invention, the bus information of the MCU kernel 2 is automatically identified to output the optimal time sequence wiring path of the FPGA kernel 3 matched with the MCU kernel 2, and wiring is carried out according to the optimal time sequence wiring path, so that the wiring efficiency is improved, the interconnection time sequence of the MCU kernel 2 and the FPGA kernel 3 is improved, the chip power consumption is reduced, and the performance requirement of the interconnection communication between the MCU kernel 2 and the FPGA kernel 3 is met. Understandably, the method for processing the information of the FPGA kernel 3 of the system on chip 1 is suitable for the MCU kernels 2 with different architectures, such as the MCU kernels 2 with 1 bit of MCU kernel 2, the MCU kernel with 4 bits of MCU kernel 28 bits of MCU kernel 2, the MCU kernel with 16 bits of MCU kernel 2, the MCU kernel with 32 bits of MCU kernel 2, the MCU kernel with 64 bits of MCU kernel 2 and the like.
In an embodiment, as shown in fig. 2, the decoding the bus information in step S10 includes:
s101, the address unit 311 analyzes the address bus information in the bus information, and determines an address bus bit width parameter according to the bit width of the address bus information.
Understandably, the FPGA core 3 scans the address interface of the FPGA core 3 in real time, since all address signal transmission lines of the MCU core 2 are connected to the address interface of the FPGA core 3, the bus information is transmitted once, the address bus information of the bus information transmits address signals through all address signal transmission lines, that is, binary ("0" low level or "1" high level) data is transmitted, the level state of the address interface of the FPGA core 3 is scanned in real time, i.e. when the bus information transmits an instruction, the number of the address interfaces of the FPGA core 3 connected to the address signal transmission line can be obtained if the address interfaces of the FPGA core 3 have a level state (high level or low level), namely the binary bit number of the address bus information transmission representing the bus information, and the binary bit number of the address bus information transmission of the bus information is determined as the address bus bit width parameter. Such as: the address bus 6 in the bus information has 32-bit binary data to be transmitted simultaneously, that is, 32 address lines are connected to transmit address signals, the address interfaces of the FPGA kernels 3 are scanned in real time, the level states of the address interfaces of the 32 FPGA kernels 3 are obtained, and the address bus bit width parameter is determined to be 32 bits.
S102, the data unit 312 parses the data bus information in the bus information, and determines a data bus bit width parameter according to the bit width of the data bus information.
Understandably, the FPGA core 3 scans the data interface of the FPGA core 3 in real time, since all the data signal transmission lines of the MCU core 2 are connected to the data interface of the FPGA core 3, the bus information transmits a command once, the data bus information of the bus information can transmit data signals through all the data signal transmission lines, i.e., transmit binary ("0" low level or "1" high level) data, and usually, the number of all the data signal transmission lines is the same as the bit number of the MCU cores 2 of different architectures, i.e., 1 data signal transmission line exists for 1-bit MCU core 2, 4 data signal transmission lines exist for 4-bit MCU core 2, 8 data signal transmission lines exist for 8 bits, 16 data signal transmission lines exist for 16 bits, 32 data signal transmission lines exist for 32 bits, and 64 data signal transmission lines exist for 64 bits. Therefore, by scanning the level state of the data interface of the FPGA core 3 in real time, that is, when the bus information transmits a command once, the data interface of the FPGA core 3 has a level state (high level or low level), the number of the data interfaces of the FPGA core 3 connected to the data signal transmission line, that is, the number of binary bits representing the data bus information transmission of the bus information, can be obtained, and the number of the binary bits of the data bus information transmission of the bus information is determined as the data bus bit width parameter. Such as: and (3) simultaneously transmitting 16-bit binary data in the data bus 7 in the bus information, namely, connecting 16 data lines to transmit data signals, scanning the data interfaces of the FPGA kernels 3 in real time, acquiring the level states of the 16 data interfaces of the FPGA kernels 3, and determining that the bit width parameter of the data bus is 16 bits.
S103, the control unit 313 analyzes the control bus information in the bus information and determines a control bus bit width parameter according to the bit width of the control bus information.
Understandably, the FPGA core 3 scans the control interface of the FPGA core 3 in real time, since all control signal transmission lines of the MCU core 2 are connected to the control interface of the FPGA core 3, the bus information transmits a command once, the control bus information of the bus information transmits a control signal through all the control signal transmission lines, i.e., transmits binary ("0" low level or "1" high level) data, the level state of the control interface of the FPGA core 3 is scanned in real time, i.e. when the bus information transmits an instruction, the control interface of the FPGA core 3 has a level state (high level or low level), the number of the control interfaces of the FPGA core 3 connected with the control signal transmission line can be obtained, namely the binary digit number of the control bus information transmission representing the bus information, and the binary digit number of the control bus information transmission representing the bus information is determined as the control bus bit width parameter. Such as: and 5-bit binary data are simultaneously transmitted in a control bus 8 in the bus information, namely 5 control lines are connected to transmit control signals, the control interfaces of the FPGA kernels 3 are scanned in real time, the level states of the control interfaces of the 5 FPGA kernels 3 are obtained, and the bit width parameter of the control bus is determined to be 5 bits.
S104, the clock unit 314 parses the clock frequency in the bus information, and marks the parsed clock frequency as a bus clock frequency.
Understandably, the FPGA core 3 scans the clock interface of the FPGA core 3 in real time, and since the clock line of the MCU core 2 is connected to the clock interface of the FPGA core 3, the clock interface of the FPGA core 3 is scanned in real time and the clock frequency of the MCU core 2 is read, and the clock frequency is marked as the bus clock frequency. Such as: the clock frequency of the MCU kernel 2 is 12MHz, the clock frequency is transmitted to the clock interface of the FPGA kernel 3, the FPGA kernel 3 reads out 12MHz, and the bus clock frequency is marked as 12 MHz.
The execution sequence of steps S101, S102, S103, and S104 may be performed synchronously or asynchronously, and the execution sequence of the four steps may also be changed, which is not limited herein, and is preferably performed synchronously, so that the running time of the FPGA core 3 can be saved. Thus, the bit width parameter of the address bus, the bit width parameter of the data bus, the bit width parameter of the control bus and the bus clock frequency are automatically identified by scanning the interface of the FPGA kernel 3 in real time.
In one embodiment, the addressing parameters include all source addresses in the address bus information and the destination addresses of all FPGA soft cores associated with the address bus information. As shown in fig. 3, in the step S20, the decoding the addressing parameter in the address bus information includes:
s201, the decoding unit 321 decodes the start address and the end address of the address bus information, and determines all source addresses of the address bus information according to the start address and the end address.
Understandably, the source address is address bus information in the bus information sent by the MCU core 2, the bit number is determined according to the address bus bit width parameter, and is composed of binary "0" (low level) or "1" (high level), and includes a start address and an end address, preferably, all the bit numbers are "0" (low level) and are determined as the start address, and all the bit numbers are "1" (high level) and are determined as the end address, so that all the source addresses in the range of the start address and the end address are decoded, for example: the address bus bit width parameter is 4 bits, the start address is 0000, and the end address is 1111, so all source addresses are 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111. Understandably, if the address bus bit width parameter is n bits, then there are 2 to the power of n source addresses.
S202, the obtaining unit 322 obtains the address depth and the data width of the register 331 of all the FPGA soft cores 33, and obtains the data bus bit width parameter in the decoded bus information at the same time; one of the FPGA soft cores 33 includes a register 331.
Understandably, the FPGA core 3 includes at least one FPGA soft core 33, the register 331 of each FPGA soft core 33 has the inherent address depth and the data width, the address depth and the data width of the register 331 of each FPGA soft core 33 are obtained, and the two are multiplied to obtain the buffer capacity of the register 331, for example: the address depth of the register 331 of the first soft core is 3, and the data width of the register 331 of the first soft core is 8 bits, that is, the cache capacity of the register 331 of the first soft core is 24 bits. In this embodiment, after the bus information is decoded in step S10, the data bus bit width parameter included in the decoded bus information may be acquired. Understandably, the data width of the register 331 of the FPGA soft core 33 is generally consistent with the data bus bit width parameter, but the data bus bit width parameter may be a multiple of the data width of the register 331 of the FPGA soft core 33, or the data width of the register 331 of the FPGA soft core 33 may be a multiple of the data bus bit width parameter.
S203, the association unit 323 segments all source addresses according to the address depth, the data width, and the data bus bit width parameter, and maps the source address of each segment after segmentation to a destination address of the FPGA soft core 33.
Understandably, the decoder 32 calculates the cache capacity of the register 331 of each FPGA soft core 33 through the acquired address depth and data width of the register 331 of all FPGA soft cores 33, then divides the cache capacity of the register 331 of each FPGA soft core 33 by the data bus bit width parameter, and rounds up the divided value, so as to obtain the number of occupation of each FPGA soft core 33, where the occupation number refers to the number of consecutive source addresses that each FPGA soft core 33 needs to occupy in all source addresses. Segmenting all the source addresses according to the occupation numbers of all the FPGA soft cores 33, and dividing the source addresses into sections of continuous source addresses corresponding to the occupation numbers of the FPGA soft cores 33 (each occupation is sequentially and continuously arranged according to the sequence of the corresponding FPGA soft core 33) (a section of one continuous source address corresponds to one section of the source addresses, and the source address number of each section of the continuous source addresses is equal to the occupation number of one FPGA soft core 33). Since the register 331 of the FPGA soft core 33 has a register 331 address composed of a preset number of bits (the register 331 address is labeled as the destination address of the FPGA soft core 33), the segment connection of each consecutive source address can be mapped to the destination address of one FPGA soft core 33, and therefore, the segment of the consecutive source address can be associated with the destination address of the FPGA soft core 33. Therefore, the incidence relation between all source addresses and all destination addresses of the FPGA soft core 33 can be obtained, and further, the starting address of wiring and the ending address of wiring are provided for the wiring process, the time for manually searching addresses is saved, and the wiring efficiency is improved.
In another embodiment, as shown in fig. 7, in the step S20, the obtaining address bus information in the decoded bus information and decoding an addressing parameter in the address bus information includes:
and receiving a control signal containing a destination address of the FPGA soft core 33, and connecting the MCU core 2 to the FPGA soft core 33 corresponding to the destination address of the FPGA soft core 33.
Understandably, the multiplexer 36 shown in fig. 7 receives the control signal containing the destination address of the FPGA soft core 33 sent by the decoder 32, because each segment of the source addresses is connected and mapped with the destination address of one FPGA soft core 33, when the address bus information in the bus information matches one source address in one segment of the source addresses, the control signal of the destination address of the FPGA soft core 33 associated with the segment of the source address to which the source address belongs is generated, and the MCU core 2 is connected to the FPGA soft core 33 corresponding to the destination address of the FPGA soft core 33 according to the control signal, at this time, the FPGA soft core 33 solely shares the data bus information in the bus information sent by the MCU core 2, so as to implement the data read-write operation between the MCU core 2 and the FPGA soft core 33.
It should be understood that, the sequence numbers of the steps in the foregoing embodiments do not imply an execution sequence, and the execution sequence of each process should be determined by its function and inherent logic, and should not constitute any limitation to the implementation process of the embodiments of the present invention.
The invention provides a system on chip 1, and the system on chip 1 corresponds to the FPGA kernel information processing method of the system on chip in the embodiment one by one. As shown in fig. 4, the FPGA core 3 includes:
the FPGA bus software module 30 is configured to receive bus information sent by an MCU core, decode the bus information, obtain address bus information in the decoded bus information, decode addressing parameters in the address bus information, output bus clock frequency and bus bit width information in the decoded bus information and the addressing parameters to a layout and wiring design module, receive an optimal timing wiring path output by the layout and wiring design module, and notify the optimal timing wiring path to the MCU core through a bus 5.
In one embodiment, as shown in fig. 7, the FPGA bus software module 30 includes:
the decoder 31 is used for receiving the bus information sent by the MCU kernel 2 and decoding the bus information;
the decoder 32 is configured to obtain address bus information in the decoded bus information, and decode an addressing parameter in the address bus information;
the timing analyzer 34 is configured to obtain bus clock frequency and bus bit width information in the decoded bus information, and output the bus clock frequency, the bus bit width information, and the addressing parameter to a layout and wiring design module;
and the receiving module 35 is configured to receive the optimal timing wiring path output by the layout and wiring design module, and notify the optimal timing wiring path to the MCU core 2 through the bus 5.
In the system on chip 1 of the above embodiment, the FPGA core 3 of the system on chip 1 receives the bus information sent by the MCU core 2, the decoder 31 decodes the bus information, the decoder 31 is connected to the decoder 32 through the address bus 6, and is connected to the timing analyzer 34 through the address bus 6, the data bus 7 and the control bus 8, the decoder 32 obtains the address bus information in the bus information decoded by the decoder 31, the decoder 32 decodes the addressing parameter in the address bus information, the timing analyzer 34 obtains the bus clock frequency and the bus bit width information in the bus information decoded by the decoder 31, and the timing analyzer 34 outputs the bus clock frequency, the bus bit width information and the addressing parameter to the layout and wiring design module, the receiving module 35 receives the optimal time sequence wiring path output by the layout wiring design module, and informs the optimal time sequence wiring path to the MCU kernel 2 through the bus 5, so that the optimal time sequence wiring path of the FPGA kernel 3 matched with the MCU kernel 2 is output by automatically identifying the bus information of the MCU kernel 2, and wiring is performed according to the optimal time sequence wiring path, thereby improving the wiring efficiency, improving the interconnection time sequence of the MCU kernel 2 and the FPGA kernel 3, reducing the chip power consumption, and meeting the performance requirements of interconnection communication between the MCU kernel 2 and the FPGA kernel 3.
Specifically, in fig. 7, the system on chip 1 includes an MCU core 2 and an FPGA core 3; the FPGA core 3 comprises a decoder 31, a decoder 32, a timing analyzer 34, a multiplexer 36, a receiving module 35 and at least one FPGA soft core 33 (one FPGA soft core 33 comprises a register 331); the MCU kernel 2 is connected with a decoder 31 in the FPGA kernel 3 through a bus 5; the decoder 31 is connected with the decoder 32 through an address bus 6, and the decoder 31 is connected with the multiplexer 36 through a data bus 7; the decoder 32 and the multiplexer 36 are connected to all the FPGA soft cores 33, the decoder 31 is connected to the timing analyzer through an address bus 6, a data bus 7 and a control bus 8, the timing analyzer 34 is connected to an external computer device 4, the external computer device 4 is connected to the receiving module 35, and the receiving module 35 is connected to the MCU core 2 through a bus 5.
In an embodiment, the bus bit width information includes bus types included in the bus information and bus bit width parameters corresponding to the bus types; the bus types include an address bus 6, a data bus and a control bus; the bus bit width parameters comprise address bus bit width parameters, data bus bit width parameters and control bus bit width parameters.
In one embodiment, as shown in fig. 5, the decoder 31 includes:
the address unit 311 is configured to analyze address bus information in the bus information, and determine an address bus bit width parameter according to a bit width of the address bus information;
the data unit 312 is configured to analyze data bus information in the bus information, and determine a data bus bit width parameter according to a bit width of the data bus information;
the control unit 313 is configured to analyze control bus information in the bus information, and determine a control bus bit width parameter according to a bit width of the control bus information;
the clock unit 314 is configured to parse the clock frequency in the bus information, and mark the parsed clock frequency as a bus clock frequency.
In one embodiment, as shown in fig. 6, the addressing parameters include all source addresses in the address bus information and the destination addresses of all FPGA soft cores 33 associated with the address bus information; one of the FPGA soft cores 33 includes one register 331;
the decoder 32 includes:
a decoding unit 321, configured to decode a start address and an end address of the address bus information, and determine all source addresses of the address bus information according to the start address and the end address;
an obtaining unit 322, configured to obtain address depths and data widths of registers of all the FPGA soft cores 33, and obtain a data bus bit width parameter in the decoded bus information at the same time;
and the association unit 323 is configured to segment all source addresses according to the address depth, the data width, and the data bus bit width parameter, and map a destination address of one FPGA soft core 33 to each segmented source address.
In one embodiment, as shown in fig. 7, the FPGA core 3 further includes:
and the multiplexer 36 is configured to receive a control signal including a destination address of the FPGA soft core 33, and connect the MCU core 2 to the FPGA soft core 33 corresponding to the destination address of the FPGA soft core 33.
For the specific definition of the system on chip 1 and the FPGA core 3 therein, reference may be made to the above definition of the FPGA core 3 information processing method of the system on chip 1, and details are not described here. It will be apparent to those skilled in the art that, for convenience and brevity of description, only the above-mentioned division of the functional units and modules is illustrated, and in practical applications, the above-mentioned function distribution may be performed by different functional units and modules according to needs, that is, the internal structure of the apparatus is divided into different functional units or modules to perform all or part of the above-mentioned functions.
The above description is only for the specific embodiments of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art can easily conceive of the changes or substitutions within the technical scope of the present invention, and all the changes or substitutions should be covered within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. The system on a chip is characterized by comprising an MCU core and an FPGA core, wherein the FPGA core is in communication connection with the MCU core through a bus; the FPGA kernel comprises an FPGA bus software module and at least one FPGA soft core;
the FPGA bus software module is used for receiving bus information sent by an MCU kernel, decoding the bus information, acquiring address bus information in the decoded bus information, decoding addressing parameters in the address bus information, outputting bus clock frequency and bus bit width information in the decoded bus information and the addressing parameters to a layout and wiring design module, receiving an optimal time sequence wiring path output by the layout and wiring design module, and informing the MCU kernel through a bus.
2. The system on a chip of claim 1, wherein the bus bit width information includes a bus type and a bus bit width parameter corresponding to each of the bus types included in the bus information;
the bus type comprises an address bus, a data bus and a control bus; the bus bit width parameters comprise address bus bit width parameters, data bus bit width parameters and control bus bit width parameters;
the FPGA bus software module comprises:
the decoder is used for receiving the bus information sent by the MCU kernel and decoding the bus information;
the decoder is used for acquiring address bus information in the decoded bus information and decoding addressing parameters in the address bus information;
the time sequence analyzer is used for acquiring the bus clock frequency and the bus bit width information in the decoded bus information and outputting the bus clock frequency, the bus bit width information and the addressing parameters to the layout and wiring design module;
and the receiving module is used for receiving the optimal time sequence wiring path output by the layout and wiring design module and informing the MCU kernel of the optimal time sequence wiring path through a bus.
3. The system on a chip of claim 2, wherein the decoder comprises:
the address unit is used for analyzing the address bus information in the bus information and determining an address bus bit width parameter according to the bit width of the address bus information;
the data unit is used for analyzing the data bus information in the bus information and determining a data bus bit width parameter according to the bit width of the data bus information;
the control unit is used for analyzing control bus information in the bus information and determining a control bus bit width parameter according to the bit width of the control bus information;
and the clock unit is used for analyzing the clock frequency in the bus information and marking the analyzed clock frequency as the bus clock frequency.
4. The system on a chip of claim 2, wherein the addressing parameters include all source addresses in address bus information and destination addresses of all FPGA soft cores associated with the address bus information; one FPGA soft core comprises one register;
the decoder includes:
the decoding unit is used for decoding the initial address and the end address of the address bus information and determining all source addresses of the address bus information according to the initial address and the end address;
the acquisition unit is used for acquiring the address depth and the data width of all registers of the FPGA soft core and acquiring the data bus bit width parameter in the decoded bus information;
and the association unit is used for segmenting all source addresses according to the address depth, the data width and the data bus bit width parameters, and mapping the source address of each segment after segmentation to a destination address of one FPGA soft core in a connecting manner.
5. The system on a chip of claim 1, wherein the FPGA bus software module further comprises:
and the multiplexer is used for receiving a control signal containing a destination address of the FPGA soft core and connecting the MCU core to the FPGA soft core corresponding to the destination address of the FPGA soft core.
6. The FPGA kernel information processing method of the system on chip is characterized in that the system on chip comprises an MCU kernel and an FPGA kernel, and the FPGA kernel is in communication connection with the MCU kernel through a bus; the FPGA kernel comprises an FPGA bus software module and at least one FPGA soft core; the method comprises the following steps:
the FPGA bus software module receives bus information sent by an MCU kernel, decodes the bus information, acquires address bus information in the decoded bus information, decodes addressing parameters in the address bus information, outputs bus clock frequency and bus bit width information in the decoded bus information and the addressing parameters to a layout and wiring design module, receives an optimal time sequence wiring path output by the layout and wiring design module, and informs the MCU kernel through a bus.
7. The FPGA core information processing method of the system on a chip as recited in claim 6, wherein said bus bit width information includes a bus type included in said bus information and a bus bit width parameter corresponding to each of said bus types;
the bus type comprises an address bus, a data bus and a control bus; the bus bit width parameters comprise address bus bit width parameters, data bus bit width parameters and control bus bit width parameters;
the FPGA bus software module comprises a decoder, a time sequence analyzer and a receiving module;
the method comprises the steps of receiving bus information sent by an MCU kernel, decoding the bus information, obtaining address bus information in the decoded bus information, decoding addressing parameters in the address bus information, outputting bus clock frequency, bus bit width information and the addressing parameters in the decoded bus information to a layout and wiring design module, receiving an optimal time sequence wiring path output by the layout and wiring design module, and informing the MCU kernel, and comprises the following steps:
the decoder receives bus information sent by the MCU kernel and decodes the bus information;
the decoder acquires address bus information in the decoded bus information and decodes addressing parameters in the address bus information;
the time sequence analyzer acquires the bus clock frequency and the bus bit width information in the decoded bus information and outputs the bus clock frequency, the bus bit width information and the addressing parameters to a layout and wiring design module;
and the receiving module receives the optimal time sequence wiring path output by the layout and wiring design module and informs the MCU kernel of the optimal time sequence wiring path through a bus.
8. The FPGA core information processing method of the system on a chip of claim 7 wherein said decoder comprises an address unit, a data unit, a control unit and a clock unit;
the decoding the bus information includes:
the address unit analyzes address bus information in the bus information and determines an address bus bit width parameter according to the bit width of the address bus information;
the data unit analyzes data bus information in the bus information and determines a data bus bit width parameter according to the bit width of the data bus information;
the control unit analyzes control bus information in the bus information and determines a control bus bit width parameter according to the bit width of the control bus information;
the clock unit analyzes the clock frequency in the bus information and marks the analyzed clock frequency as the bus clock frequency.
9. The FPGA core information processing method of the system on a chip of claim 7, wherein said decoder comprises a decoding unit, an obtaining unit, and an associating unit; the addressing parameters comprise all source addresses in address bus information and destination addresses of all FPGA soft cores associated with the address bus information; the decoding of the addressing parameters in the address bus information includes:
the decoding unit decodes the initial address and the end address of the address bus information and determines all source addresses of the address bus information according to the initial address and the end address;
the acquisition unit acquires the address depth and the data width of registers of all the FPGA soft cores and simultaneously acquires the data bus bit width parameters in the decoded bus information; one FPGA soft core comprises a register;
and the association unit segments all source addresses according to the address depth, the data width and the data bus bit width parameters, and maps the source address of each segment after segmentation to a destination address of an FPGA soft core in a connecting manner.
10. The FPGA core information processing method of a system on a chip of claim 7 wherein the FPGA bus software module further comprises a multiplexer; the obtaining address bus information in the decoded bus information and decoding addressing parameters in the address bus information includes:
and the multiplexer receives a control signal containing the destination address of the FPGA soft core and connects the MCU core to the FPGA soft core corresponding to the destination address of the FPGA soft core.
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| CN113672551B (en) * | 2020-05-14 | 2024-05-14 | 广东高云半导体科技股份有限公司 | General processing system and general processing method |
| CN111923606B (en) * | 2020-06-30 | 2022-03-29 | 厦门汉印电子技术有限公司 | Printer and printing method |
| CN112181865B (en) * | 2020-09-09 | 2024-05-31 | 北京爱芯科技有限公司 | Address coding method, address coding device, address decoding method, address decoding device, and computer storage medium |
| CN112347014B (en) * | 2020-11-30 | 2022-04-26 | 安徽信息工程学院 | Optimal time sequence control method and system for centralized data communication |
| CN113434460B (en) * | 2021-08-26 | 2022-01-11 | 长沙海格北斗信息技术有限公司 | Multi-bus topology system in SoC (System on chip) architecture and bus interconnection method |
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| CN115658560B (en) * | 2022-12-28 | 2023-03-14 | 北京紫光芯能科技有限公司 | Data sharing management method, device and system, electronic equipment and storage medium |
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