CN115130413B - Topological structure design method of field programmable gate array and electronic equipment - Google Patents

Topological structure design method of field programmable gate array and electronic equipment Download PDF

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CN115130413B
CN115130413B CN202211060342.3A CN202211060342A CN115130413B CN 115130413 B CN115130413 B CN 115130413B CN 202211060342 A CN202211060342 A CN 202211060342A CN 115130413 B CN115130413 B CN 115130413B
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connection
metal interconnection
connection relation
pins
programmable logic
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CN115130413A (en
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王祥
周芝梅
武延年
张少波
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China Gridcom Co Ltd
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China Gridcom Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/343—Logical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/347—Physical level, e.g. placement or routing

Abstract

The invention discloses a topological structure design method of a field programmable gate array, electronic equipment and a computer readable storage medium. The topological structure design method comprises the following steps: determining the input number of a multiplexer in a programmable gate array, the number of metal interconnection lines and the number of pins of a programmable logic module; generating a connection relation according to the input number of the multi-path selector, the number of the metal interconnection lines and the number of the pins of the programmable logic module according to a preset rule; and generating a circuit schematic diagram according to the connection relation under the condition that the connection relation meets the design requirement. And flexibly setting the jump relation of the interconnection channels among different numbers under the condition that the metal interconnection line segments cross the number of the logic modules and the number of the metal interconnection line segments, designing balanced connection, covering comprehensive connection relation, carrying out structure evaluation, further automatically generating a circuit schematic diagram, and realizing customized channel structure design.

Description

Topological structure design method of field programmable gate array and electronic equipment
Technical Field
The invention relates to the technical field of chip design, in particular to a topological structure design method of a field programmable gate array, electronic equipment and a computer readable storage medium.
Background
A Field-Programmable Gate Array (FPGA) chip is a general signal processing device, and its main constituent modules include a Programmable logic module, an embedded memory, programmable interconnection resources, a Programmable input/output module, and the like. The interconnection resource topology structure provides programmable interconnection resources for the FPGA chip. The interconnection resource arrangement mode is of great importance to the communication distribution rate of the FPGA chip.
Disclosure of Invention
The present invention is directed to solving at least one of the problems of the prior art. Therefore, the present invention is to provide a topology design method of a field programmable gate array, an electronic device and a computer readable storage medium.
The topological structure design method of the field programmable gate array provided by the embodiment of the invention comprises the following steps: determining the input number of a multiplexer in the programmable gate array, the number of metal interconnection lines and the number of pins of a programmable logic module; generating a connection relation according to the input number of the multi-path selector, the number of the metal interconnection lines and the number of the pins of the programmable logic module according to a preset rule; and generating a circuit schematic diagram according to the connection relation under the condition that the connection relation meets the design requirement.
According to the topological structure design method, under the condition that the metal interconnection line segments span the number of logic modules and the number of the metal interconnection line segments, the jump relation of interconnection channels among different numbers is flexibly set, balanced connection is designed, the comprehensive connection relation is covered, structure evaluation is carried out, a circuit schematic diagram is further automatically generated, and the customized channel structure design is realized.
In some embodiments, the generating a connection relationship according to the input number of the multiplexer, the number of the metal interconnection lines, and the number of the pins of the programmable logic module according to a preset rule includes: setting a connection step length according to the input number of the multiplexer under the condition that the input number of the multiplexer is smaller than the number of the metal interconnection lines; sequentially and circularly determining interconnection channels based on the initial connection and the connection step length; and determining the connection relation according to the using times of the interconnection channel.
In some embodiments, before the step of sequentially determining the interconnection channels based on the initial connection and the connection step size in a loop, the generating a connection relationship according to the input number of the multiplexers, the number of the metal interconnection lines, and the number of the pins of the programmable logic module according to a preset rule includes: and determining the cycle number according to the input number of the multi-path selector, the number of the metal interconnection lines and the number of the pins of the programmable logic module.
In some embodiments, said determining a number of cycles based on a number of inputs to said multiplexer, a number of said metal interconnect lines, and a number of pins of said programmable logic module comprises: and calculating the product of the input number of the multiplexer and the number of the pins of the programmable logic module and dividing the product by the number of the metal interconnection lines to obtain the cycle number.
In some embodiments, the determining the connection relation according to the number of times of using the interconnection channel includes: determining the total number of interconnection channels according to the input number of the multiplexer and the number of pins of the programmable logic module; calculating the difference between the total number of the interconnection channels and the number of the use times of the interconnection channels to obtain the residual interconnection channels; and selecting the residual interconnection channels for connection to determine the connection relation.
In some embodiments, the generating a connection relationship according to the input number of the multiplexer, the number of the metal interconnection lines, and the number of the pins of the programmable logic module according to a preset rule includes: and respectively connecting the metal interconnection lines to the input ends of the multiplexers to generate the connection relation under the condition that the input number of the multiplexers is equal to the number of the metal interconnection lines.
In some embodiments, the generating a connection relationship according to the input number of the multiplexer, the number of the metal interconnection lines, and the number of the pins of the programmable logic module according to a preset rule includes: and under the condition that the input number of the multi-path selector is larger than the number of the metal interconnection lines, feeding back error information and setting the input number of the multi-path selector to be equal to the number of the metal interconnection lines.
In some embodiments, the generating a schematic circuit diagram according to the connection relation when the connection relation meets the design requirement includes: wiring the connection relation by using preset software; and generating a circuit schematic diagram according to the connection relation when the wiring is successful.
The electronic device according to an embodiment of the present invention includes a processor and a memory, where the memory stores a computer program, and the computer program, when executed by the processor, implements the topology design method according to any of the above embodiments.
The electronic equipment of the embodiment of the invention executes the computer program by the processor, flexibly sets the jump relation of the interconnection channels among different numbers under the condition that the metal interconnection line segments cross the number of the logic modules and the number of the metal interconnection line segments, designs the balanced connection, covers the comprehensive connection relation, carries out structure evaluation, further automatically generates a circuit schematic diagram, and realizes the structure design of the customized channel.
The computer-readable storage medium of the embodiments of the present invention stores a computer program, and when the computer program is executed by one or more processors, the computer program implements the topology design method described in any of the above embodiments.
In the computer readable storage medium of the embodiment of the invention, when a computer program is executed by a processor, under the condition that metal interconnection line segments cross over the number of logic modules and the number of the metal interconnection line segments, the jump relation of interconnection channels among different numbers is flexibly set, balanced connection is designed, comprehensive connection relation is covered, structure evaluation is carried out, a circuit schematic diagram is further automatically generated, and the structure design of a customized channel is realized.
Additional aspects and advantages of the invention will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the invention.
Drawings
The above and/or additional aspects and advantages of the present invention will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings of which:
fig. 1 is a schematic diagram of a prior art row-based interconnect topology for a field programmable gate array.
Fig. 2 is a schematic diagram of a hierarchical row-based interconnection topology of a field programmable gate array of the prior art.
FIG. 3 is a schematic diagram of a prior art island-based interconnection topology of a field programmable gate array.
Fig. 4 is a schematic diagram of a prior art field programmable gate array interconnect channel design scheme.
Fig. 5 is a flowchart illustrating a topology design method of a field programmable gate array according to an embodiment of the present application.
Fig. 6 is a schematic flowchart of a topology design method of a field programmable gate array according to an embodiment of the present application.
Fig. 7 is a schematic flowchart of a topology design method of a field programmable gate array according to an embodiment of the present application.
Fig. 8 is a flowchart illustrating a topology design method of a field programmable gate array according to an embodiment of the present application.
Fig. 9 is a flowchart illustrating a topology design method of a field programmable gate array according to an embodiment of the present application.
Fig. 10 is a block diagram of a computer device according to an embodiment of the present application.
Detailed Description
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
In the description of the present invention, it is to be understood that, in the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. In the description of the present invention, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly and may, for example, be fixedly connected, detachably connected, or integrally connected; may be mechanically connected, may be electrically connected or may be in communication with each other; they may be directly connected or indirectly connected through intervening media, or may be connected through the use of two elements or the interaction of two elements. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
Reference will now be made in detail to embodiments of the present invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the accompanying drawings are illustrative only for the purpose of explaining the present invention, and are not to be construed as limiting the present invention.
Referring to fig. 1 to 4, in the related art, the interconnection topology mainly has three forms, the first is a row-based interconnection topology, as shown in fig. 1, the interconnection channels in the row-based interconnection topology are arranged in rows in the chip, and the logic module is connected to the row interconnection channels through the antifuse crossbar. The second is a hierarchical interconnection topology structure, as shown in fig. 2, interconnection channels in the hierarchical interconnection topology structure may be divided into a top layer data channel, a local data channel, and a bottom layer data channel, logic resources are distributed in different logic domains, logic inside the logic domains may be connected through the bottom layer data channel, and connections between the logic domains are connected through the local data channel or the top layer data channel according to the domain positions where the logic domains are located. This configuration has the advantage of having a certain delay between the logic, but is not conducive to optimizing circuit performance. The third is an island interconnection topology structure, as shown in fig. 3, where island interconnection resources are distributed among various heterogeneous modules of the FPGA and are composed of metal line segments spanning a certain number of modules and a crossbar switch, LB represents a logic module, a connection line segment represents a metal line segment, a ladder diagram represents a multiplexer for connecting the metal line and the LB, a shaded portion at the intersection of the line segments represents the crossbar switch, and the crossbar switch is used for realizing jump between metal lines and connection between the LB and the metal line.
An important task in the design of interconnection resources is to select the appropriate metal line segment numbers to connect to the multiplexers and crossbars, thereby achieving smaller area and higher flexibility. As shown in fig. 4, the conventional interconnect channel design generally adopts a fixed design mode, including a discrete type, a univeral type, and a wilton type, and the connection form is single. When the channels jump, a certain numbered channel can only be connected to the channel with the same number, and the flexibility is not enough; while the uninversal and Wilton type crossbar switches increase the jumping between channels with different numbers, the jumping can be performed only according to certain rules, for example, the Universal type crossbar switch can only jump to the channels with the same number or the complementary number, and Wilton is similar. The above channel structures all have the disadvantage of insufficient flexibility.
Aiming at the problem in the design of a connecting line connecting module (consisting of metal connecting lines and a multiplexer), the invention provides a topological structure design method of a customized channel structure.
Specifically, referring to fig. 5, a method for designing a topology of a field programmable gate array according to an embodiment of the present invention includes:
01, determining the input number of a multiplexer in a programmable gate array, the number of metal interconnection lines and the number of pins of a programmable logic module;
02, generating a connection relation according to the input number of the multi-path selector, the number of the metal interconnection lines and the number of the pins of the programmable logic module according to a preset rule;
and 03, generating a schematic circuit diagram according to the connection relation under the condition that the connection relation meets the design requirement.
According to the topological structure design method, under the condition that the metal interconnection line segments span the number of logic modules and the number of the metal interconnection line segments, the jump relation of interconnection channels among different numbers is flexibly set, balanced connection is designed, the comprehensive connection relation is covered, structure evaluation is carried out, a circuit schematic diagram is further automatically generated, and the customized channel structure design is realized.
In step 01, the designer may define the input number i of the multiplexers in the programmable gate array to be designed, the number j of the metal interconnection lines, and the number k of PINs (PINs) of the programmable logic modules (LB). The possible total number of interconnect channels p can be calculated from the product of the number of multiplexer inputs i and the number of pins k of the programmable logic module.
And then selecting a corresponding interconnection channel according to a preset rule for connection to automatically generate a connection relation, so that a circuit schematic diagram can be automatically generated under the condition that the connection relation meets a preset condition, and the structural design of the customized channel is realized. It should be noted that, the connection relation meeting the preset condition may be that the multiplexer, the metal interconnection line and the programmable logic module can achieve successful wiring and meet the requirement of the line length or the time sequence.
Referring to fig. 6, in some embodiments, step 02 includes:
022, setting a connection step according to the input number of the multiplexer when the input number of the multiplexer is less than the number of the metal interconnection lines;
024, determining the interconnection channel based on the initial connection and the connection step length;
026, the connection relation is determined according to the number of usage of the interconnection path.
It can be understood that, in the case that the input number of the multiplexers is less than the number of the metal interconnection lines, the metal interconnection lines connected to each multiplexer may have multiple combinations, and at this time, corresponding connection step lengths may be set according to the input number of the multiplexers, and the initial connection may be set by a designer, the corresponding interconnection channels may be determined based on the initial connection and the connection step lengths, and the number of times of use of each interconnection channel may be counted, so that the connection relationship may be determined.
In one example, the connection step size may be the same as the input number i of the multiplexer, i.e. the connection step size step = i.
Further, in one example, the interconnect channel number may be 1,2,3,4 \8230; \823080; 80, and if the input number of multiplexers i =16, the initial connection of the first multiplexer may be 1,2,3,4, \823016. The initial connection of the second multiplexer may be 1+ step, 2+ step, 3+ step,4+ step \8230, 16+ step.
Referring to fig. 7, in some embodiments, before step 024, step 02 further includes:
023, determining the number of cycles according to the number of inputs to the multiplexer, the number of metal interconnect lines and the number of pins of the programmable logic module.
Specifically, the number relationship among the input number of the multiplexer, the number of the metal interconnection lines, and the number of the pins of the programmable logic module may determine how many times of cycles are performed in sequence to realize the connection of the corresponding interconnection channels, that is, determine the number of cycles for generating the connection relationship.
In certain embodiments, step 023 comprises: and calculating the product of the input number of the multiplexer and the number of the pins of the programmable logic module and dividing the product by the number of the metal interconnection lines to obtain the cycle number.
The product of the input number of the multiplexer and the number of the pins of the programmable logic module can be calculated to obtain the possible total number of the interconnecting channels, and then the quotient of the total number of the interconnecting channels and the number of the metal interconnecting lines can be calculated to obtain the cycle number, that is, the cycle number is: p/j.
Referring to fig. 8, in some embodiments, step 026 includes:
0262 determining total number of interconnection channels based on the input number of the multiplexer and the number of pins of the programmable logic module;
0264, calculating the difference between the total number of interconnecting channels and the number of times of using interconnecting channels to obtain the remaining interconnecting channels;
0266, the remaining interconnection paths are selected for connection to determine the connection relationship.
Thus, after the interconnection channels are determined circularly, the number of times of use of each interconnection channel is counted, and the total number of times of use is subtracted by the total number p of interconnection channels to obtain the number of remaining channels which can be connected. And can be manually adjusted by designers so as to select the rest channels for connection, thereby obtaining a connection relation file.
In certain embodiments, step 02 comprises: and respectively connecting the metal interconnection lines to the input ends of the multiplexers to generate connection relations under the condition that the input number of the multiplexers is equal to the number of the metal interconnection lines.
It can be understood that, under the condition that the input number of the multiplexers is equal to the number of the metal interconnection lines, the inputs of all the multiplexers include the numbers of all the metal interconnection lines, and the one-to-one correspondence between the inputs of all the multiplexers and the metal interconnection lines can be realized, at this time, the metal interconnection lines can be directly connected to the input ends of the multiplexers respectively, so that the connection relationship can be generated.
In certain embodiments, step 02 comprises: and under the condition that the input number of the multiplexers is larger than the number of the metal interconnection lines, feeding back error information and setting the input number of the multiplexers equal to the number of the metal interconnection lines.
It can be understood that the input number of the multiplexers is greater than the number of the metal interconnection lines, which is not beneficial to the field programmable gate array design, so that when the defined input number i of the multiplexers is greater than the number j of the metal interconnection lines, error information can be fed back to prompt the designer that the number of the defined parameters is wrong, so that the designer can modify the parameters conveniently. The input number of the multiplexers can also be automatically designed to be equal to the number of the metal interconnection lines, i.e. i = j, without receiving the modification instruction of the designer.
Referring to fig. 9, in some embodiments, step 03 includes:
032, wiring the connection relationship by using preset software;
034, when the wiring is successful, a schematic circuit diagram is generated based on the connection relationship.
The preset software can be FPGA layout wiring software, wiring is carried out on the generated connection relation through the preset software, and when wiring is successful and wire length or time sequence requirements are met, a circuit schematic diagram can be generated according to the connection relation.
In some embodiments, after step 032, the topology design method comprises: in the event of unsuccessful routing or inadequate wire length or timing requirements, the initial connection is adjusted to re-establish the interconnect channel.
Referring to fig. 10, an electronic device 10 according to an embodiment of the present invention includes a processor 12 and a memory 14, the memory 14 stores a computer program 142, and when the computer program 142 is executed by the processor 12, the topology design method according to any of the embodiments is implemented.
In one embodiment, the computer program 142, when executed by the processor 12, implements the following method steps:
01, determining the input number of a multiplexer in a programmable gate array, the number of metal interconnection lines and the number of pins of a programmable logic module;
02, generating a connection relation according to the input number of the multi-path selector, the number of the metal interconnection lines and the number of the pins of the programmable logic module according to a preset rule;
03, generating a circuit schematic diagram according to the connection relation under the condition that the connection relation meets the design requirement, and realizing the design of the customized channel structure.
In the electronic device 10 according to the embodiment of the present invention, the processor 12 executes the computer program 142, and when the metal interconnection line segments cross the number of logic modules and the number of the metal interconnection line segments, the jump relationship of the interconnection channels between different numbers is flexibly set, so as to design a balanced connection, cover a comprehensive connection relationship, perform structure evaluation, further automatically generate a circuit schematic diagram, and implement a customized channel structure design.
The computer-readable storage medium of the embodiments of the present invention stores a computer program, and when the computer program is executed by one or more processors, the topology design method of any of the above embodiments is implemented.
In the description herein, references to the description of the terms "one embodiment," "some embodiments," "an illustrative embodiment," "an example," "a specific example," or "some examples" or the like mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, schematic representations of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
Any process or method descriptions in flow charts or otherwise described herein may be understood as representing modules, segments, or portions of code which include one or more executable instructions for implementing specific logical functions or steps of the process, and alternate implementations are included within the scope of the preferred embodiment of the present invention in which functions may be executed out of order from that shown or discussed, including substantially concurrently or in reverse order, depending on the functionality involved, as would be understood by those reasonably skilled in the art of the present invention.
The logic and/or steps represented in the flowcharts or otherwise described herein, e.g., an ordered listing of executable instructions that can be considered to implement logical functions, can be embodied in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, processor-containing system, or other system that can fetch the instructions from the instruction execution system, apparatus, or device and execute the instructions. For the purposes of this description, a "computer-readable medium" can be any means that can contain, store, communicate, propagate, or transport the program for use by or in connection with the instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium would include the following: an electrical connection (electronic device) having one or more wires, a portable computer diskette (magnetic device), a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium could even be paper or another suitable medium upon which the program is printed, as the program can be electronically captured, via for instance optical scanning of the paper or other medium, then compiled, interpreted or otherwise processed in a suitable manner if necessary, and then stored in a computer memory.
It should be understood that portions of the present invention may be implemented in hardware, software, firmware, or a combination thereof. In the above embodiments, the various steps or methods may be implemented in software or firmware stored in memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or combination of the following technologies, which are well known in the art, may be used: a discrete logic circuit having a logic gate circuit for implementing a logic function on a data signal, an application specific integrated circuit having an appropriate combinational logic gate circuit, a Programmable Gate Array (PGA), a Field Programmable Gate Array (FPGA), or the like.
It will be understood by those skilled in the art that all or part of the steps carried out to implement the above-described implementation method can be implemented by hardware related to instructions of a program, which can be stored in a computer-readable storage medium, and the program, when executed, includes one or a combination of the steps of the method embodiments.
In addition, functional units in the embodiments of the present invention may be integrated into one processing module, or each unit may exist alone physically, or two or more units are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode. The integrated module, if implemented in the form of a software functional module and sold or used as a stand-alone product, may also be stored in a computer readable storage medium.
The computer readable storage medium mentioned above may be a read-only memory, a magnetic or optical disk, etc. Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention, and that variations, modifications, substitutions and alterations can be made to the above embodiments by those of ordinary skill in the art within the scope of the present invention.

Claims (9)

1. A topological structure design method of a field programmable gate array is characterized by comprising the following steps:
determining the input number of a multiplexer in the programmable gate array, the number of metal interconnection lines and the number of pins of a programmable logic module;
generating a connection relation according to the input number of the multiplexers, the number of the metal interconnection lines and the number of the pins of the programmable logic module according to a preset rule;
generating a circuit schematic diagram according to the connection relation under the condition that the connection relation meets the design requirement;
generating a connection relation according to the input number of the multiplexers, the number of the metal interconnection lines and the number of the pins of the programmable logic module according to a preset rule, wherein the generating of the connection relation comprises the following steps:
setting a connection step length according to the input number of the multi-path selector under the condition that the input number of the multi-path selector is smaller than the number of the metal interconnection lines;
determining the interconnection channels in turn circularly based on the initial connection and the connection step length;
and determining the connection relation according to the using times of the interconnection channel.
2. The method according to claim 1, wherein before the step of determining the interconnect channels sequentially and cyclically based on the initial connection and the connection step size, the step of generating the connection relationships according to the number of inputs of the multiplexer, the number of the metal interconnect lines, and the number of pins of the programmable logic module according to a preset rule comprises:
and determining the cycle number according to the input number of the multiplexer, the number of the metal interconnection lines and the number of the pins of the programmable logic module.
3. The method of claim 2, wherein determining the number of cycles based on the number of inputs to the multiplexer, the number of metal interconnect lines, and the number of pins of the programmable logic module comprises:
and calculating the product of the input number of the multiplexer and the number of the pins of the programmable logic module and dividing the product by the number of the metal interconnection lines to obtain the cycle number.
4. The method according to claim 2, wherein said determining the connection relation according to the number of times of using the interconnection path comprises:
determining the total number of interconnection channels according to the input number of the multiplexer and the number of pins of the programmable logic module;
calculating the difference between the total number of the interconnection channels and the number of times of using the interconnection channels to obtain the remaining interconnection channels;
and selecting the residual interconnection channels for connection to determine the connection relation.
5. The method of claim 1, wherein the generating a connection relationship according to the input number of the multiplexers, the number of the metal interconnection lines, and the number of the pins of the programmable logic modules according to a preset rule further comprises:
and respectively connecting the metal interconnection lines to the input ends of the multiplexers to generate the connection relation under the condition that the input number of the multiplexers is equal to the number of the metal interconnection lines.
6. The method of claim 5, wherein the generating a connection relationship according to the number of inputs of the multiplexer, the number of the metal interconnection lines, and the number of pins of the programmable logic module according to a preset rule further comprises:
and under the condition that the input number of the multi-path selector is larger than the number of the metal interconnection lines, feeding back error information and setting the input number of the multi-path selector to be equal to the number of the metal interconnection lines.
7. The method according to claim 1, wherein generating a schematic circuit diagram according to the connection relation when the connection relation satisfies a design requirement includes:
wiring the connection relation by using preset software;
and generating a schematic circuit diagram according to the connection relation when the wiring is successful.
8. An electronic device comprising a processor and a memory, the memory storing a computer program that, when executed by the processor, implements the topology design method of any of claims 1-7.
9. A computer-readable storage medium, characterized in that the computer-readable storage medium stores a computer program which, when executed by one or more processors, implements the topology design method of any of claims 1-7.
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Publication number Priority date Publication date Assignee Title
US20080074142A1 (en) * 2006-09-25 2008-03-27 Alex Henderson Routing for Microprocessor Busses
CN100576746C (en) * 2007-03-15 2009-12-30 复旦大学 A kind of field programmable logic array interconnection resource structure and modeling method thereof
US20110289469A1 (en) * 2010-05-21 2011-11-24 Huang Thomas B Virtual interconnection method and apparatus
CN103366028B (en) * 2012-03-31 2016-03-16 中国科学院微电子研究所 A kind of field programmable gate array chip layout method
US9495492B1 (en) * 2015-01-05 2016-11-15 Cadence Design Systems, Inc. Implementing synchronous triggers for waveform capture in an FPGA prototyping system
CN106841894B (en) * 2016-12-23 2020-02-11 深圳市国微电子有限公司 FPGA interconnection line testing method and device
US10608638B2 (en) * 2018-05-24 2020-03-31 iCometrue Company Ltd. Logic drive using standard commodity programmable logic IC chips
CN110738015B (en) * 2019-09-10 2020-07-07 广东高云半导体科技股份有限公司 System on chip and FPGA kernel information processing method thereof
CN114065694A (en) * 2020-08-03 2022-02-18 上海复旦微电子集团股份有限公司 FPGA wiring resource map compression method and global wiring module

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