KR100423594B1 - Concurrent logical and physical construction of voltage islands for mixed supply voltage designs - Google Patents

Abstract

The present invention discloses a method for logically and physically configuring voltage islands. The semiconductor chip design is divided into "bins" which are design areas. In this method, a semiconductor chip is "sliced" into several regions and then these regions are assigned to several voltage levels. Each bin can be thought of as a voltage island. In design, circuits may be added to or removed from multiple bins, increasing or decreasing the speed and power of the circuit. That is, placing a circuit in a bin assigned to a high voltage increases speed and power, while placing a circuit in a bin having a low voltage decreases speed and power. In addition, the size and position of the bins can also vary. By repeating the above steps, power consumption can be optimized while meeting speed limits and other criteria. The invention can be applied to any placement environment, such as an annealing placement tool, in which the placement process can be interrupted to continuously refine circuit location in the design and to make changes in the logic layout.

Description

CONSUMER LOGICAL AND PHYSICAL CONSTRUCTION OF VOLTAGE ISLANDS FOR MIXED SUPPLY VOLTAGE DESIGNS

FIELD OF THE INVENTION The present invention relates generally to computer circuitry on semiconductor chips, and more particularly to a method for logically and physically configuring voltage islands for mixed supply voltage designs simultaneously.

The switching power of the digital circuit increases with the square of the supply voltage increase. Therefore, it is desirable to reduce the power supply voltage in order to reduce the power consumption of the circuit. However, reducing the power supply voltage also degrades circuit performance. Therefore, it is preferable to combine a circuit driven with a high power voltage and a circuit driven with a low power supply voltage (hereinafter, referred to as a high voltage circuit and a low voltage circuit, respectively) on the same chip. Use high voltage circuits where the desired circuit performance is required and low voltage circuits elsewhere.

When high voltage and low voltage circuits are coupled in this manner on a semiconductor chip, it is desirable to combine the low voltage circuits physically into a low voltage "island" and to group the high voltage circuits separately into a high voltage "island". This is desirable because the high and low voltage power supplies are distributed on separate distribution networks and only one of the two power supplies needs to be distributed within each island by grouping the circuits into islands. This reduces the amount of extra wiring resources needed to distribute the two power supplies, making more wiring resources available for signal wiring. In turn, this makes the semiconductor chip smaller and / or requires fewer wiring planes.

When combining high and low voltage circuits on a chip, care must also be taken with respect to the net that drives the signal from one type of circuit to another. Typically, a high voltage circuit can drive a low voltage circuit directly without a specific insertion circuit, but a low voltage circuit with a high voltage circuit must drive a high voltage circuit through a specific "level shifter" circuit. The circuitry increases the area, power and delay of the network. Therefore, it is desirable to minimize the use of the circuit. In many families of circuits, the high voltage latch circuit can operate as a level shifter at no additional cost. Therefore, if the low voltage circuit is selected so that the low voltage circuit directly supplies the latch circuit, the number of level shifters required can be reduced. By assigning a group of tightly coupled circuits to high or low voltage, the number of level shifters required can typically be reduced.

In summary, by placing a high voltage circuit in a high voltage island and a low voltage circuit in a low voltage island, the number of level shifters used is typically minimized. This also reduces the number of places where high voltage power and low voltage power should be routed, thereby reducing power distribution costs. However, the island may not help in the placement of good logic circuits. For example, a signal may have to travel very long distances by moving up to a high voltage island and then back from the high voltage island to the circuit using the signal. This does not increase performance but actually reduces performance. Therefore, poor placement results occur where good placement should be made.

Another method of creating high voltage and low voltage circuits is logic clustering. In logical clusters, high and low voltage circuits are designed based on connections and not within voltage islands. Devices in the circuit that need to be faster change to higher voltages, while slower non-critical devices change to low voltages. This solves the placement problem caused by high voltage and low voltage island clustering when the data path is not moved. However, different power sources must be distributed at each place and the number of level shifters can be greatly increased by logical clustering.

Therefore, there is a need to limit the amount of power routing and the number of level shifters while allowing the critical data path to meet timing conditions.

The preferred embodiment of the present invention solves this problem by providing a logical and physical configuration of the voltage island. Preferred embodiments of the present invention combine physical and logical synthesis to still meet timing and other requirements while providing less level shifters and less power routing. In addition, by using an iterative process to construct the voltage island, power consumption is minimized while in particular the speed limit is met.

In one aspect of the invention, the semiconductor chip design is divided into "bins" which are design areas. In this method, the semiconductor chip design is "sliced" into several regions, which regions can be assigned to multiple voltage levels. Each bin can be thought of as a voltage island. In design, circuits can be added to or removed from multiple bins, increasing or decreasing the speed and power of the circuit. That is, placing a circuit in a bin assigned to a high voltage increases speed and power, while placing a circuit in a bin having a low voltage decreases speed and power. In addition, the size and position of the bins may vary. By repeating these steps, optimal power consumption is achieved while meeting speed limits and other criteria.

Therefore, instead of just adding a circuit to a voltage island or just determining which circuit requires a high voltage and changing the circuit to a high voltage level, the present invention combines the two concepts. The present invention employs both physical and logical configurations of voltage islands to meet predetermined criteria.

Dividing a semiconductor chip design into multiple bins is just one way of placing circuitry in the design. The present invention can be applied to any placement environment where the placement process can be interrupted to continuously advance the position of the circuit in the design and also change the logic circuit placement.

These and other features and advantages of the present invention will become apparent from the following detailed description of the preferred embodiments of the invention as illustrated in the accompanying drawings.

1 illustrates a preferred method of providing a logical and physical configuration of a voltage island in accordance with a preferred embodiment of the present invention.

2 shows a preferred method of moving circuits between bins to improve speed and reduce power and congestion.

3-7 illustrate logic circuits at various stages of deployment in accordance with the method of FIG. 1.

8 and 9 illustrate exemplary power reduction steps employed by the preferred embodiment of the present invention in the illustrated arrangement.

10 and 11 are flow charts of a second preferred method according to a preferred embodiment of the present invention.

<Explanation of symbols for the main parts of the drawings>

331,332: NAND gate

330,340: Logical Blocks

350 to 355: Inverter

410,420: Island

510, 520: empty

1055: Level Shifter

1122: application program

1128: operating system

1140: Terminal Interface

As mentioned above, the present invention relates to the arrangement of circuitry on a semiconductor chip by a computer. For those who do not know this principle, the following overview introduces concepts related to the batch process. Those skilled in the art of arranging circuits on a semiconductor chip with a computer may directly enter the detailed description.

Outline

When designing semiconductor chips, computer design tools are used. This tool works to create a file called a "netlist." The netlist contains a description of all the gates and the connections between them. Semiconductor chip designers typically work with the logic layout of a simulated chip. In other words, the semiconductor chip performs some function, and the designer ensures that the simulated chip actually performs the function logically. When ready to manufacture the actual chip, the chip designer uses a batch tool that uses the original netlist and generates the output. The batch tool is set with netlist, timing limit, batch limit and switching information. The layout tool is also set with a library that describes the timing of the wiring and gate and includes layout rules, the size and shape of the gate, and the like. The batch tool outputs the modified netlist and the batch information. Thereafter, the modified netlist and placement information is supplied to a wiring tool, which generates masks and other information that are used to actually create the chip on the semiconductor wafer.

There are many different types of deployment systems. One important system is called Placement Driven Synthesis (PDS). References to PDS are given by the names "An Integrated Placement and Synthesis Approach for Timing Closure of the POWER PC Microprocessor" by S. Hojat and D. Villarrubia in pages 206-210 of the International Conference on Computer Design (1997). This document is incorporated herein by reference. PDS systems allow for logical changes in the network during deployment. The PDS consists of a batch program based on cuts and a set of operations performed between the cuts. The cut-based batch program repeatedly divides the chip region and the circuit on the chip. Generally, the division begins by dividing the chip into two (although the quadrisection method of dividing the chip into four parts is also known), and then dividing each half into two and continuing. To divide in that way. Initially, the final position of the circuit on the chip is unknown, and after each set of cuts the circuit position is elaborated.

The regions formed by dividing the chip at any point in the placement process are called "empty". In the PDS, various "logical synthesis" operations (generally, programs that modify the netlist) are performed between batch cut sets, so that variations on the network can be made based on a sophisticated knowledge of the currently available circuit layouts. To be. Typical operations include buffering, cloning (duplicating circuits and distributing their fanouts between the original circuit and the duplicated circuits), factoring, pin swapping, and the like. Circuits are often moved between bins.

Another example of a placement tool and method is a simulated annealing placer. The placement tool works similar to the physical annealing of the crystal, making many experimental changes to the placement. Each test change is maintained or restored according to improvements in the measurement of "temperature" parameters that help control the "goodness" of the batch (e.g., estimated wire control) and the annealing process. Can be. The process starts at high temperatures and proceeds to low temperatures as the batch progresses. Changes that improve the measurement are always maintained, while changes that degrade the measurement are likely to be maintained, with the potential decreasing with decreasing temperature and increasing amount of batch measurement degradation. As the batch process proceeds, the average distance the circuit travels within the allowed batch changes decreases. Therefore, the circuit location on the chip can be better known gradually.

details

The preferred embodiment of the present invention combines both physical and logical synthesis to provide fewer level shifters and less power routing, but meets timing and other conditions. In addition, by using an iterative process for the construction of the voltage island, the power usage is minimized while in particular the speed limit is met.

In one aspect of the invention the semiconductor chip design is divided into design bins, " bins. &Quot; In this method, the semiconductor chip design is "sliced" into several regions, which regions can be assigned to multiple voltage levels. Each bin can be thought of as a voltage island. In design, circuits can be added to or removed from multiple bins, increasing or decreasing the speed and power of the circuit. That is, placing a circuit in a bin assigned to a high voltage increases speed and power, while placing a circuit in a bin having a low voltage decreases speed and power. In addition, the size and position of the bins may vary. By repeating these steps, optimal power consumption is achieved while meeting speed limits and other criteria.

Therefore, instead of just adding a circuit to a voltage island or just determining which circuit requires a higher voltage and changing the circuit to a higher voltage level, the present invention combines the two concepts. The present invention employs both physical and logical configurations of voltage islands to meet predetermined criteria. Dividing a semiconductor chip design into multiple bins is just one method of placing circuitry in the design. The present invention can be applied to any placement environment where the placement process can be interrupted to continuously advance the position of the circuit in the design and also change the logic circuit placement.

It is better to explain the terminology before further describing the preferred embodiment. "Bin" is the design area of a semiconductor chip herein. Each bin does not have to be assigned a specific voltage. Voltage islands are areas of design that are assigned a specific voltage. All circuits in a voltage island are powered by a specific voltage assigned to that voltage island.

Any deployment system can be used to perform the synthesis of both the physical and logical described herein. In general, the placement system assigns a set of circuits on a portion of a chip design to a particular voltage level, selects an area of the chip design, and assigns circuits within that area to another voltage level. Between the high voltage level and the low (or medium) voltage level, circuit shifts occur to optimize the design. In the best embodiment of the present invention the chip design is sliced into bins. Each bin is a voltage island and assigned a specific voltage. Some bins are assigned a high voltage and some bins are assigned a low voltage. Therefore, physical synthesis is performed. Within this physical limitation, circuits are moved from the high voltage region to the low voltage region and vice versa to meet power, speed, and other criteria. Therefore, logical synthesis is also performed. In another embodiment of the present invention an annealing batch system is used. In this embodiment the voltage island is assigned to a specific location and no bin is used. However, physical and logical synthesis still occurs.

12 is a block diagram of a computer system of the present invention. Those skilled in the art will appreciate that the mechanisms and apparatus of the present invention may equally be used for any computer system, whether the computer system is a complex multi-user computing device or a single user workstation. As shown in FIG. 12, the computer system 1100 may include a main or central processing unit (CPU) 1110, a mass storage interface 1130, a terminal interface 1140, and a network interface connected to the main memory 1120. 1150). The system elements are interconnected via a system bus 1160. The mass storage interface 1130 is used to connect the mass storage device (DASD device 1155, etc.) to the computer system 1100. One particular type of DASD device is a floppy disk drive that stores data on and reads data from the floppy diskette 1955.

Main memory 1120 includes one or more application programs 1122, circuit elements 1124, data 1126, and operating system 1128. The computer system 1100 is known to allow programs in the computer system 1100 to act as if they access only a single large storage device instead of accessing multiple small storage devices, such as the main memory 1120 and the DASD device 1155. Use a virtual addressing mechanism. Therefore, although application program 1122, circuit elements 1124, data 1126, and operating system 1128 are shown as being in main memory 1120, they need to be fully included in main memory 1120 all at the same time. Those skilled in the art will appreciate that there is no. (The term "computer system memory" is used herein to mean all virtual memory of computer system 1100.)

Operating system 1128 may be any suitable operating system. The spirit and scope of the present invention is not limited to any one operating system. In addition, there is one or more application programs 1122 executed by the CPU 1110 in the main memory 1120. One of these application programs is the integrated circuit design tool 1134 according to the present invention. The main memory 1120 also includes display data (eg, electrical and timing parameters) of the circuit elements 1124 used by the design tool 1134. Although the integrated circuit design tool 1134 and the circuit elements 1124 are shown as being in the main memory 1120, they may exist anywhere in the virtual memory space of the computer system 1100. In addition, although the circuit device 1124 is shown separately from the design tool 1134, the circuit device 1124 may also be provided integrally with the integrated circuit design tool 1134. As described in greater detail below, the integrated circuit design tool 1134 is preferably a design tool that performs Placement Driven Synthesis (PDS) of the circuitry 1124. As mentioned in the overview, PDS divides the chip design into relatively small areas called bins. In this preferred embodiment, the bin is used as the voltage island and the criteria are used to determine when the design is properly placed.

Although computer system 1100 is shown to include only a single main CPU and a single system bus, those skilled in the art will appreciate that the present invention may be practiced using computer systems having multiple CPUs and / or multiple buses. In addition, each of the interfaces used in the preferred embodiment includes separate fully programmed microprocessors used to off-load compute-intensive processing in the CPU 1110. However, those skilled in the art will appreciate that the present invention applies equally to computer systems that simply use I / O adapters to perform similar functions.

Terminal interface 1140 is used to connect one or more terminals 1165 directly to computer system 1100. The terminal 1165, which may be a non-intelligent or fully programmable workstation, is used to allow system administrators and users to communicate with the computer system 1100.

The network interface 1150 is used to connect other computer systems and / or workstations (eg, 1175 and 1185 of FIG. 1) to the computer system 1100 in a network format. The present invention can be applied regardless of whether or not the network interface 1150 exists. For the preferred embodiment of the present invention, there is a network interface, and the present invention uses the present analog and / or digital technology no matter how the computer system 1100 is connected to other computer systems and / or workstations. The same applies whether or not through a network or via some networking mechanism in the future. It is also important to know that the presence of network interface 1150 in computer system 1100 means that computer system 1100 can be used for processing in cooperation with one or more other computer systems or workstations. Of course, this means that not all programs depicted in main memory 1120 necessarily reside in computer system 1100. For example, one or more programs of application program 1122 may be involved in the operation of co-operating with one or more programs residing on another system and residing on computer system 1100. The cooperative process may be performed using one of known client-server mechanisms, such as remote procedure call (RPC).

In this respect, while the invention has been described (and will be described) in the context of a fully functional computer system, those skilled in the art will appreciate that the invention may be distributed as various forms of program products, and that the distribution of signal storage media to actually perform the It will be appreciated that the same applies regardless of the particular form. Examples of signal storage media include recordable media such as floppy disks (e.g., disk 1195 in FIG. 12) and CD ROM, and transmission media such as digital and analog communication links, including wireless communication links.

1 illustrates a method of placing circuits using logical and physical configurations of voltage islands. This method 100 is preferably performed by the integrated circuit design tool 1134 as illustrated in FIG. The method 100, when performed by the integrated circuit design tool 1134 during the placement of circuit elements, facilitates circuit element placement to create an optimal combination of power and speed and meet other criteria.

The method 100 begins by setting an unplaced design 105 in a placement tool. The unplaced design is described by a netlist that describes all the gates and the connections between them. With the unplaced design, the tool is set with a set of timing limits and / or power and area limits. In addition, as some circuits (input / output circuits, etc.) need to be located at specific locations, some position restrictions are also required. Eventually, the placement tool sets up a library that describes the timing of the wires and gates and includes placement rules, gate size and shape, and the like.

Initially, all circuits are set to a specific voltage (step 110). Preferably all circuits are set to low voltage to reduce the overall power condition. If the circuits are initially set to high voltage, the circuits already have high power and the placed design tends to be high power. If more than one voltage is used, it is recommended to select the lowest voltage at this stage. In the case of using two voltages (low voltage and high voltage), a low voltage should be selected as the starting voltage of the voltage island.

In step 120, the unplaced design is divided into bins. Each bin and voltage island in this method 100 should be equivalent. In other words, each voltage island becomes one bin. During the splitting (or “cutting”) process, general PDS synthesis operations to meet performance objectives, to reduce power by means other than voltage island generation, and to meet other design objects. This is used. In particular, the PDS system may consider the overall routing constraint in this case. If the voltage island is too small, the amount of power routing increases. It can adversely affect system space.

In step 125 a determination is made whether all design criteria are met. In general, design criteria basically combine performance and power. For example, the design criterion may be to minimize power subject to performance limitations. Performance limits must be met for these criteria, and different power consumption may occur with various deployment designs that meet the performance criteria. One way of judging performance is by "slacks". The amount of time between when the signal should be absolutely in one position and when the signal is actually there is a slack. If it's a positive slack, the signal arrives ahead of schedule. This makes it possible to bring more power to one or more circuits in the path. Conversely, with negative slack, the signal does not arrive in time. In general, this means that changing one or more circuits to higher power in the path increases performance. Meeting the design criteria in terms of minimizing power subject to performance limitations means that all performance objects are met (i.e. all slack is positive) and that the deployed design has the lowest power of the design deployment possible. .

If the design criterion is to maximize performance under the power limitation, then meeting that criterion means that the power limit is exceeded by assigning a high voltage to many bins.

Note that criteria except power and performance can be tested in step 125. For example, its location is important in circuits such as input / output circuits. Meeting the criterion in step 125 may ensure that the circuit is in the proper position. Also, area, noise, reliability, and wire-ability are other criteria that can be tested in step 125.

If the design criteria are met (YES in step 125), the deployment is complete in step 150. At that stage, the PDS system is set a limit that cannot transition the circuit from a low voltage bin to a high voltage bin or vice versa. During this step, the modified netlist and placement information is output. Prior to outputting the placement information, the PDS system determines the exact location of each circuit in each bin to generate the placement information. Preferably, in the previous step the circuits are simply placed in a particular bin. During step 150, the exact X, Y position of each circuit in the bin is determined. Once the modified netlist and placement information is output, the design is deployed and optimized (step 160). The design can be transferred to a wiring tool to create a mask or the like needed to actually manufacture the chip.

If one or more criteria are not met (NO in step 125), then in step 130 the PDS system assigns a bin to the second voltage. The selected bin becomes the voltage island of the second voltage. Preferably, the second voltage is higher than the first voltage. If two voltages, low and high, are used, it is best to assign the bin to a high voltage. If more than one voltage is used, the second highest voltage should be assigned to the bin. For example, if there are three voltages (low voltage, medium voltage and high voltage), the bin will preferably be initially assigned to the medium voltage. In a second pass through step 125, if the slack of the circuit in the bin is still a negative, for example, the same bin may be assigned a high voltage at this time. By assigning the bin to a voltage that increases from low voltage to high voltage, it is possible to obtain a deployed design with lower power than could be achieved by assigning the bin to a decreasing voltage (from high voltage to low voltage).

In step 130 a particular bin is also selected as the bin to assign to the second voltage. There are several ways to determine which bin to assign to the second voltage. When the second voltage is high voltage, the selected bin generally becomes the bin containing the circuit on the worst slack path in design. In this scenario, as the voltage increases, the speed of the circuit increases, improving slack. The selected bin can also be arbitrarily selected. Another way of selecting a bin (when the second voltage is a high voltage) is to select a low switching bin, where the low switching bin includes a less frequently used net, i.e. a circuit that switches relatively few times. Since the increase in switching results in an increase in power, power is reduced in conventional methods.

Alternatively, the determination of which bin to assign to the second voltage involves finding a point where a number of late paths converge. How to find the point is described in references [K. Usami, et al., "Automated Low-Power Technique Exploiting Multiple Supply Voltages Applied to a Media Processor", Institute of Electrical and Electronics Engineers Journal of Solid-State Circuits, v.33, no. 3, 463-472 (March 1998); And L. Berman, et al., "Efficient Techniques for Timing Correction", Proceeding of the 1990 International Symposium on Circuits and Systems (May 1990), which is incorporated herein by reference.

The selected bin can also be a bin with multiple circuits in the critical path. When making this selection, bins with the maximum number of circuits in the critical path may be selected as bins. Alternatively, the selection can be made by determining which bin causes the maximum delay improvement for the critical path if the circuit that the bin contains is assigned a second (high) voltage. Finally, a bin selection can be made by selecting a bin with multiple inputs that directly power the latches, such as reducing the need for a level shifter.

Multiple bins may be selected in step 130. However, for simplicity, this specification describes the selection of only one bin. Further, in step 130, the selected bin and its circuit are assigned to the second voltage. Assigning the circuit to the second voltage allows the PDS tool to recalculate delays, power consumption, slack and other data. Thereafter, the information is used to determine if the criteria have been met.

In step 135, a level shifter is added where needed. If the second voltage is a high voltage, the selected bin is converted to a high voltage island. Low voltage circuits that output a signal to a circuit of a high voltage island (selected bin) have a level shifter added to the low voltage signal. If the second voltage is low voltage, no level shifter is required between the circuit of the high voltage island and the circuit of the low voltage island. This is because low voltage circuits generally require level shifters to power high voltage circuits, but high voltage circuits do not necessarily require level shifters to power low voltage circuits.

In step 140, the level shifter is removed from the output of the circuit that no longer needs the level shifter. For example, if the low voltage circuit has an output signal that provides the high voltage circuit, the output signal of the low voltage circuit has a level shifter above it. When the bin containing the low voltage circuit is made of a high or higher voltage island, a level shifter is no longer needed on the output of the low voltage circuit.

In step 145, the circuits move between the bins to improve speed and reduce power and control. Circuits can move to a selected bin to increase speed (if the selected bin is a high voltage bin), increase occupancy, or free up space in adjacent bins. Circuits can move out of the selected bin to reduce power (when the selected bin is a high voltage bin and the circuit moves to a low voltage bin), reduce congestion, reduce occupancy, or increase the occupied bin occupancy. Can be.

In addition to FIG. 1, FIG. 2 describes step 145 in more detail. In step 145 of this example it is described that the selected bin is high voltage and some nested bins are low voltage. The difference between the above situation and vice versa, that is, the situation where the selected bin is low voltage and some of the nested bins are high voltage is discussed after the description of FIG. Although the steps are shown in a particular order in methods 145 and 100, it is to be understood that the steps need not necessarily be performed in that order.

After each step or operation of method 145, the circuits can be checked to see if it violates the timing limit, exceeds the bin capacity, or violates the constraint limit on the cut line between the bins. If so, the operation may be rejected. Timing restrictions can be violated due to increased load on the net caused by changes in wiring length caused by circuit movement. The bin capacity can be violated if too many circuits are placed in the bin so that the circuit and connecting wiring cannot simply fit into the area of the bin. Note that other semiconductor technologies may have different area conditions for the circuit. Constraints restrictions can be violated if there are too many wires because of too many data paths to the bin. If there are too many data paths to the bin, the bin is not wireable. In method 145, circuit movement may include cloning of the circuit to reduce collisions in the net length.

In FIG. 2, method 145 begins when a non-critical circuit is moved from a selected bin to a low power adjacent bin (step 210). Critical paths need to meet certain timing conditions and also tend to be the most difficult to meet timing. The PDS system performs a timing analysis and determines from which analysis which path is the critical path. Non-critical circuits are circuits that are not in the critical path. Conversely, the threshold circuit is a circuit in the critical path. In step 210 power is lowered by moving the non-critical circuit to a low power voltage island. If necessary, the level shifter on the output of the non-critical circuit is moved to its input. In this step it is possible to preferentially select the circuits of the selected bin sourcing the bin outputs supplied to the circuits of the other low voltage bins.

In step 210 it is also possible to preferentially select the circuits of the selected bin which are supplied by the circuits of the other low voltage bins. In order to reduce the number of level shifters required, a procedure of max-flow, min-cut (max-flow, min-cut) may be performed. References describing the procedure of maximum-flow, minimum-cut include "Graph Algorithms", Shimon Even, Computer Science Press, 1979, which is incorporated herein by reference. In the above procedure, the flow graph is constructed from a set of all non-critical bin inputs of a selected high voltage bin supplied by a circuit of another low voltage bin and from a non-critical circuit of fan-out cones of that selected bin. The minimum-cut through the flow network is determined. All circuits that are “residual” of the nets within the minimum-cut through the flow network are determined. Moving the "residual" or "supply" circuit to an adjacent low voltage bin minimizes the number of level shifters required at the bin input. In essence, the procedure produces a minimum number of signals transitioning from low voltage to high voltage and minimizes wiring length. The flow graph is one way of determining which circuit should be moved to the low voltage.

In step 210, the high switching circuit can also move well out of the bin. The high switching circuit is a circuit for switching a relatively high amount of time. The relatively high switching amount consumes more power. Therefore, a method of reducing power is to eliminate the high switching circuit from the high voltage bin to the low voltage bin. If the circuit is in the critical path, it will remain in the high voltage bin even if the circuit is a high switching circuit.

In step 220, if the selected bin falls below the minimum capacity (YES in step 220), a low voltage circuit powered by the output of the circuit of the selected bin is added to the selected bin (step 240). Circuits moving in this way may be along the input where these circuits require a level shifter, and are therefore preferentially selected to minimize the number of level shifters added as needed. In this step, the circuit powered by the critical net is added to the high voltage bin so that the critical net is maintained at the fastest speed. Therefore, when the size of the selected bin is small, the circuit powered by the critical net and in the low power bin is added to the selected bin at high power, and the non-critical circuit is removed from the selected bin. As an alternative, this step may involve adding a low switching circuit from the surrounding area to the selected bin. This reduces the power and increases the capacity of the selected bin.

If the selected bin does not fall below the minimum capacity ('NO' in step 220), a determination is made whether all non-critical circuits have been moved (step 225). If not ('NO' in step 225), the method returns to step 210. If all non-critical circuits have been moved (YES at step 225), then the threshold circuit of the low voltage bin powering the threshold circuits of the selected bin is moved to the selected bin (step 203). Therefore, if the threshold circuits of the selected bin still do not meet the timing constraints, the circuits that power these threshold circuits are moved from low to high power. This speeds up the critical path and improves timing. If there is a level shifter, the level shifter is moved from the output of the newly added circuit to the input of the newly added circuit.

In step 235, if the selected bin falls below the minimum capacity, a low voltage circuit powered by the output of the threshold circuit of the selected bin is added to the selected bin. Step 235 is similar to step 240. Circuits moving in this way are preferentially selected to minimize the number of level shifters added as needed. In step 235, the circuit powered by the critical net is added to the high voltage bin so that the critical net is maintained at the fastest speed. Therefore, when the size of the selected bin is small, the circuits powered by the critical net and in the low power bin are added to the selected bin of high power, and the non-critical circuit is removed from the selected bin.

In addition, at step 235, it may be necessary to reserve space in adjacent bins for circuits that are moved out of the selected bin. To accomplish this, a low voltage circuit powered by the output of the threshold circuit of the selected bin is added to the selected bin. In addition, circuits moving in this manner are preferentially selected to minimize the number of level shifters added as needed.

In step 255 a determination is made as to whether all criteria meet the bin. The criteria will be performance and power criteria based primarily on performance and power criteria set for chip design. In addition, other criteria such as over or under capacity, routing or location specifications, etc. may be examined. If all the criteria are not met ('NO' in step 255), method 145 is performed again; If all the criteria are met (YES at step 255), the method ends at step 250. Although the performance and power criteria may be met before step 255, the method 145 may be performed multiple times to maximize power reduction while still meeting other criteria. Low power configurations that meet other criteria (and especially performance criteria) are the best solution.

Method 145 may include all of the steps shown in FIG. 2 or may include only some of the specific steps shown. For example, only step 210 may be used in method 145. Preferably, using all steps is preferred because it provides the best performance with the least amount of power. In addition, if any step of method 145 increases the control above a predetermined level, the circuit may be moved between bins to reduce the control.

The method 145 shown in FIG. 2 may be applied whenever the selected bin is assigned a higher voltage than the adjacent bin. If the selected bin is low voltage and the adjacent bin is a higher voltage, the method 145 is slightly different. In this embodiment, it is more advantageous to move the non-critical circuit from adjacent bins to the selected bin in step 210 and to move the threshold circuit out of the selected bin. In step 240, the output circuit, which is a non-critical circuit, is preferentially moved to the selected bin. The same is true for steps 230 and 235. That is, the non-critical circuit from the surrounding high power bin is moved to the low power bin.

After step 145 of method 100, step 125 of method 100 is performed again. Method 100 continues until the criteria are met or until the method does not converge. In general, the latter is set to a time limit, i.e., if the method exceeds a certain time, it is assumed that the method does not converge to the solution. For example, if too low a power criterion is chosen for a too high performance criterion, this case occurs.

Referring to FIGS. 3-7 together with FIGS. 1 and 2, FIGS. 3-7 illustrate exemplary sections of a chip design. 3 shows a chip design that is not fully deployed, as the design exists at step 105 of method 100. 4-7 illustrate the same chip design at various stages of the batch process of methods 100 and 145.

3 shows a completely unplaced chip design. The unplaced chip design 300 has various inputs 310, 311, 312, 313, 314, 315. 316 and an output 320. The unplaced chip design 300 also includes a number of circuits, namely a number of NAND gates 331, 332, logic blocks 340, 330, a number of inverters 350, 351, 352, 353, 354, 355 and a NOR gate 360. Undeployed chip design 300 is described by a netlist.

4 shows a partially disposed design 400, with only a portion of the interconnects shown. The partially deployed design 400 appears after steps 110 and 120 of method 100. Each bin is set to a low voltage, producing low voltage bins / islands 410 and 420. The two islands 410 and 420 are separated by the boundary 430. In step 120, a general PDS synthesis operation is used to meet performance objects, reduce power by other means except for voltage island generation, and to meet other design objects. As a result, the partially disposed design 400 shown in FIG. 4 is created. Path 370 is a critical path and nets 440 and 460 cross boundary 430.

In FIG. 5, bin 410 is assigned to high voltage bin / island 510. In step 125, all criteria are not met ('NO' in step 125), so the bin 510 is selected as the high voltage bin in step 130. The bin 520 (420 of FIG. 4) remains unchanged and is a low voltage bin. All circuitry in bin 510 is assigned a high voltage. The bin 510 is selected as the high voltage bin because it has most of the circuitry on the least designed worst slack path (path 370) (step 130 of method 100). Level shifters 470, 480, 490 are added to the nets 370, 370, 440, respectively, to shift the signal to a higher voltage (step 135). The level shifter is not added to the net 460 and the path 370 when the signal leaves the inverter 353 and moves to the inverter 354 because these are high voltage signals. These signals must be able to drive the low voltage circuit. In step 140 the level shifter is not removed.

The partially deployed design 400 may be checked after the step to determine if power, performance and other criteria are met. In the case of an empty or high voltage island 510, the net control is very high; Inputs 310 through 314 only require some wiring on one side of the bin. Further, non-critical circuits (NAND gate 332) and non-critical nets 450, 440, 460 are in high voltage bin 510. Moreover, it can be assumed that threshold path 370 does not meet the timing condition, which means that the slack is negative.

5 and 6 should be cited in the following description of the step sequence of the method 145 of FIG. Because bin 510 is not optimized, input 314, circuit 332 and nets 440, 460, 450 are moved to low voltage bin / island 520 at step 210 of method 145. The level shifter 490 is no longer needed and thus removed. The bin selected in step 220 does not go below the minimum capacity and in step 224 all low voltage circuitry has been moved. In step 230 threshold circuits 354 and 360 are moved to high voltage bin / island 510. Level shifter 470 is no longer needed, but level shifter 610 is added to increase the voltage from net 620.

Power and performance criteria are determined at step 255. In this example, it is assumed that power and performance criteria are met. However, the method 145 may be repeated a certain number of times to ascertain that a good combination of power and performance can be produced in another batch. Referring to FIGS. 6 and 7 in conjunction with FIGS. 1 and 2, the result after repeating method 145 is the deployed design 700 of FIG. 7. It can be seen that the arrangement of FIG. 6 of the critical path 370 causes the slack of that path to be positive. Because it meets the timing condition, path 370 is no longer a critical path in FIG. However, all changes to the path must be checked to determine consistency with timing. In step 210 the threshold circuit 350 is moved from the high voltage bin / island 510 to the low voltage bin / island 520. As a result, the number of level shifters can be minimized and power consumption can be minimized while meeting performance criteria. During the iterative process, critical circuits 351, 352 and the like were also moved from bin 510 to bin 520. However, the performance was not met. Therefore, the deployed design 700 meets performance and power criteria. If the power is below the reference, the circuit 350 and the circuit 340 are added to the high voltage bin 510 (assuming that the capacitance condition has not been violated).

After step 145, the added bins are selected and optimized in steps 125-145 until the overall design is optimized. In the simple example of FIG. 7, bin 520 may be assigned a high voltage. This improves the performance. However, power also increases. Since the deployed design 700 meets performance and power requirements, step 125 will indicate that all criteria are met. In step 150, the batch is completed and the netlist and the batch information are output. The result is a placed and optimized design (step 160).

The methods 100 and 145 also include general synthetic operations such as cloning and buffering to further reduce power. 8 and 9 illustrate a cloning operation performed during method 145 to reduce power (by minimizing wiring length and eliminating level shifters). In FIG. 8, the partially disposed design 1000 includes a high voltage bin 1020 separated by a boundary 1040 from a low voltage bin 1030. There are two level shifters 1055 and 1060 on the boundary 1040. The level shifter 1060 shifts the voltage from the low voltage of the bin 1030 to the high voltage of the bin 1020, while the level shifter 1055 performs the reverse operation. Depending on the technology implemented, the level shifter 1055 may not be required. The particular technique used in FIG. 8 uses a level shifter 1055. Path 1090 is a critical path that has met the timing condition of FIG. 8.

The high voltage bin 1020 includes inputs 1010-1013, inverters 1070, 1075, 1080, and 1085, logic blocks 1050 and outputs 1091. The low voltage bin 1030 includes inputs 1014-1016, a logic block 1045, a NOR gate 1086, and an inverter 1087. When the method 145 operates on a partially disposed design 1000, the wiring length is determined to be high (especially nets 1093 and 1094) and the level shifter 1055 can be removed. To support it, inverters G1 and 1070 and inverters G2 and 1075 are cloned to be inverters G1 clone 1097 and inverters G2 clone 1096 (see FIG. 9). This reduces the line length since the line length is now net 1091. Also, since the level shifter 1055 is no longer needed, the number of level shifters is reduced.

The foregoing method is described using place driven synthesis (PDS). There are other deployment tools and methods. The present invention can be applied to any placement environment where design can continue to improve circuit placement and the placement process can be interrupted to change the logical position. The following description focuses on a batch tool and a methodology that is a simulated annealing placer. As mentioned in the overview, such placement tools behave similarly to the physical annealing of crystals, resulting in many variations in placement.

FIG. 10 illustrates a method 800 for logically and physically configuring a voltage aland simultaneously using a simulated annealing placer. Since method 800 is very similar to method 100, only the differences are described here with reference to method 800. During the description, it would be good to refer to FIG. 1 for comparison.

One difference between the two methods is in step 820 of method 800. As used in Method 100, the PDS system divides the chip design into several areas called bins. The simulated annealing batch system does not use bins. In step 820, instead of dividing the chip design and performing a synthesis operation in the design, a normal annealing placement process is performed until the average distance to move the circuit is less than the minimum recommended voltage island size. This allows a normal annealing batch process to be completed prior to adding logical and physical simultaneous configuration of the voltage island.

In step 830, the circuit is selected as the "seed" circuit. As described above, it is preferable to initially set all the circuits to low voltage. The seed circuit is then assigned a high voltage and a high voltage island is created around the seed circuit. The size of the high voltage island may increase or decrease depending on the number of circuits in the island. It is possible to preferentially select a circuit close to the existing high voltage island as the seed circuit. Therefore, by moving the seed circuit physically adjacent to the existing high voltage island, the size of the existing high voltage island is increased. Therefore, instead of having a bin that selects the entire bin as a voltage island, method 800 selects a circuit and generates a voltage island around the circuit.

In step 845, the circuits are moved between regions (between islands) to improve speed and reduce power and control. Step 845 is described in more detail as method 845 in FIG. 11 and is similar to steps 230-255 of FIG. 2. In step 930, the threshold circuit of the low voltage island that powers the threshold circuit of the selected island is moved to the selected island. If necessary, the size of the island is increased. Therefore, if the threshold circuit and path of the selected island still do not meet the timing constraints, the circuit powering the threshold circuit is moved from low power to high power. This speeds up the critical path and improves timing. If there is a level shifter, the level shifter is moved from the output of the newly added circuit to the input of the newly added circuit.

In step 935, if the island containing the selected seed circuit falls below the minimum capacity, a low voltage circuit powered by the output of the threshold circuit of the selected island is added to the selected island. Circuits moved in this way are preferentially selected to minimize the number of level shifters added as needed. In step 940, the circuit powered by the critical net is added to the high voltage island so that the critical net is maintained at the fastest speed. Therefore, as the selected island size becomes smaller, the circuit powered by the critical net and in the low power island is added to the selected island with high power, and the non-critical circuit is removed from the selected island.

Further, at step 935, it may be necessary to reserve space in adjacent islands for the circuit being moved out of the selected island. To accomplish this, a low voltage circuit powered by the output of the threshold circuit of the selected island is added to the selected island. Again, the circuit moving in this way is preferentially selected to minimize the number of level shifters added as needed.

In step 955 a determination is made as to whether all criteria are met for this island. The criteria may initially be performance and power criteria according to performance and power criteria set for chip design. In addition, other criteria such as over or under capacity, routing or location specifications, etc. may be examined. If all criteria are not met ('NO' in step 955), the method 845 is performed again, and if all criteria are met ('YES' in step 955), the method ends at step 950. Although performance and power criteria may be met before step 955, method 845 may be performed multiple times to maximize power reduction while still meeting other criteria. The lowest power configuration that meets other criteria (and especially performance criteria) is the best solution.

It should also be noted that if the island is less than a good capacity, then adding an additional circuit to the island in step 955 may be involved. If not enough circuits are added to the island in steps 930 and 935 (because there are fewer critical input cones or because the circuit movement necessary to physically adjoin violates other limitations), another near threshold circuit is selected to high voltage. Can be assigned and moved to island. Thereafter, steps 930 and 935 may continue on the input and output of the newly added circuit.

As described with reference to the method 145 of FIG. 2, other actions may be taken to meet the predetermined criteria of step 845. For example, buffering or cloning can be used to improve speed, reduce power, and / or reduce congestion. As an additional example, the following optimization method 145) may also be used in step 845: the high switching circuit may move from the high voltage island to the low voltage island to reduce power; If the voltage island is too low, the circuit of the surrounding low voltage island powered by the critical path or net in the selected high voltage island can be moved to (high speed) the high voltage island; Circuits can be moved to a selected voltage island based on minimization of the level shifter.

In step 850 of FIG. 10, no change is allowed to physically block the already formed high voltage island. The finishing batch process continues, but with the rule that it does not produce any change that would physically block the high voltage islands. The exact X, Y placement of the circuit in the voltage island is also determined at this stage.

Methods 800 and 845 are equally applicable to selecting seeds for low voltage islands. In this case, non-critical nets and circuits are added to the low voltage island and the critical nets and circuits are transferred to the high voltage island.

In summary, the method of providing both logical and physical configurations of voltage islands is applicable to various placement algorithms. Depending on the method, the voltage island is selected and circuits are added to or removed from the island to best analyze the design criteria. The two basic criteria are power and performance criteria. The logical configuration of the island occurs because the logical structure is maintained in and on the surrounding island. Physical configuration occurs because circuits move into and out of the physical voltage island. The best placement occurs when the logical relationship of the circuit and the physical voltage layout combine to increase performance where needed and reduce power where needed. The iterative nature of the method makes it easier to find the combined logical relationship.

The method described above provides both logical and physical configurations of voltage islands. The preferred embodiment of the present invention combines both physical and logical synthesis to reduce the number of level shifters and to reduce power routing but still meet timing and other conditions. In addition, by using an iterative process in the method of constructing the voltage island, power usage can be minimized, in particular to meet the speed limit.

The embodiments and examples described herein are disclosed to illustrate the invention and its practical applications and may enable those skilled in the art to make and use the invention. However, it will be apparent to one skilled in the art that the foregoing description and examples are disclosed for purposes of illustration only. The detailed description is not intended to be exhaustive or to limit the invention to the precise form disclosed. Similarly, unless otherwise specified, the sequence of steps in the method shown in the figures or specification is set as an example of a possible sequence and not intended to be limiting. Many modifications and variations are possible in light of the above teachings without departing from the spirit and scope of the following claims.

Claims (38)

Developing a first integrated circuit floor plan configuration; Assigning the circuit set to a first voltage level of the plurality of voltage levels; Dividing the circuit set into a plurality of bins; Assigning one of the bins to a second one of a plurality of voltage levels; Assigning circuitry within the bin to the second voltage level based on physical and logical evaluation requirements; The next additional step until an integrated circuit plan is achieved that meets predetermined requirements. Assigning a second circuit bin from a plurality of circuit bins to the second voltage level; Assigning a circuit in the second circuit bin to the second voltage level; Transferring one or more circuits between the bin assigned to the second voltage level and the bin assigned to the first voltage level. Step to repeat The method of disposing a circuit on an integrated circuit comprising a. The method of claim 1, wherein assigning one of the bins to the second voltage level comprises: Determining the worst slack path in the circuit set, Assigning a bin having at least one circuit in the worst slack path as the one bin. Assigning the circuit set to a first voltage level of the plurality of voltage levels; Dividing the circuit set into a plurality of bins; Assigning one of the bins to a second one of a plurality of voltage levels; Assigning circuitry in the one bin to the second voltage level based on physical and logical evaluation requirements; Making the second voltage level greater than the first voltage level; Assigning a bin having a predetermined number of low switching circuits as the one bin The method of disposing a circuit on an integrated circuit comprising a. Assigning the circuit set to a first voltage level of the plurality of voltage levels; Dividing the circuit set into a plurality of bins; Assigning one of the bins to a second one of a plurality of voltage levels; Assigning circuitry in the one bin to the second voltage level based on physical and logical evaluation requirements; Making the second voltage level smaller than the first voltage level; Assigning a bin having a predetermined plurality of high switching circuits as the one bin The method of disposing a circuit on an integrated circuit comprising a. Assigning the circuit set to a first voltage level of the plurality of voltage levels; Dividing the circuit set into a plurality of bins; Assigning one of the bins to a second one of a plurality of voltage levels; Assigning circuitry in the one bin to the second voltage level based on physical and logical evaluation requirements; Making the second voltage level smaller than the first voltage level; Assigning any bin as said one bean The method of disposing a circuit on an integrated circuit comprising a. Assigning the circuit set to a first voltage level of the plurality of voltage levels; Dividing the circuit set into a plurality of bins; Assigning one of the bins to a second one of a plurality of voltage levels; Assigning circuitry in the one bin to the second voltage level based on physical and logical evaluation requirements; Making the second voltage level greater than the first voltage level; Determining a location that converges a number of late paths and assigning a bin having the location as the one bin The method of disposing a circuit on an integrated circuit comprising a. The method of claim 1, wherein assigning one of the bins to the second voltage level comprises: Determining a plurality of critical paths, Determining a delay improvement amount for each bin having a circuit in the critical path when assigning a circuit of each bin to the second voltage; Determining a bin having a maximum delay amount for at least one of the threshold paths when assigning a circuit of the bin to the second voltage level; Assigning the bin as the one bin. The method of claim 1, wherein assigning one of the bins to the second voltage level comprises: Determining a bin having a predetermined input amount that directly powers the latch circuit; Assigning the bin as the one bin. Assigning the circuit set to a first voltage level of the plurality of voltage levels; Dividing the circuit set into a plurality of bins; Assigning one of the bins to a second one of a plurality of voltage levels; Assigning circuitry in the one bin to the second voltage level based on physical and logical evaluation requirements; Next step until the predetermined requirements are met Assigning an additional bin to said second voltage level; Assigning a circuit in the additional bin to the second voltage level; Moving at least one circuit between the bin assigned to the second voltage level and the bin assigned to the first voltage level Step to repeat The method of disposing a circuit on an integrated circuit comprising a. 10. The method of claim 9, wherein moving at least one circuit between the bin assigned to the second voltage level and the bin assigned to the first voltage level comprises: moving the first voltage from the bin assigned to the second voltage level. Moving at least one circuit to a bin assigned to the level. Assigning the circuit set to a first voltage level of the plurality of voltage levels; Dividing the circuit set into a plurality of bins; Assigning one of the bins to a second one of a plurality of voltage levels; Assigning circuitry in the one bin to the second voltage level based on physical and logical evaluation requirements; Adding a level shifter to said input of one of the circuits in said one bin, wherein said input crosses a boundary separating said one bin from an adjacent bin assigned to said first voltage level. The method of disposing a circuit on an integrated circuit comprising a. The method of claim 10, wherein the second voltage level is greater than the first voltage level, and wherein moving the at least one circuit from a bin assigned to the second voltage level to a bin assigned to the first voltage level comprises: Moving at least one high switching circuit from the second voltage level to the first voltage level, wherein the at least one high switching circuit is moved only if the circuit is in a non-critical path. . 10. The method of claim 9, wherein moving the at least one circuit between the bin assigned to the second voltage level and the bin assigned to the first voltage level is based on a criterion that minimizes the number of level shifters. Selecting the circuit. 10. The method of claim 9, wherein the step of moving at least one circuit between the bin assigned to the second voltage level and the bin assigned to the first voltage level comprises: a predetermined minimum of the first bin assigned to the second voltage level; To be sized. 15. The method of claim 14, wherein said second voltage level is greater than said first voltage level, and said step of moving at least one circuit between a bin assigned to said second voltage level and a bin assigned to said first voltage level comprises: Moving at least one low switching circuit from the enclosing bin assigned to the first voltage level to the first bin. 15. The method of claim 14, wherein said second voltage level is greater than said first voltage level, and said step of moving at least one circuit between a bin assigned to said second voltage level and a bin assigned to said first voltage level comprises: Moving at least one enclosing circuit to the first bin, wherein the at least one encircling circuit is in an enclosing bin assigned to the first voltage level and by a critical path of the first bin Which is powered. 15. The method of claim 14, wherein moving the at least one circuit between the bin assigned to the second voltage level and the bin assigned to the first voltage level is based on a criterion that minimizes the number of level shifters. Selecting the circuit. 10. The method of claim 9, wherein moving at least one circuit between the bin assigned to the second voltage level and the bin assigned to the first voltage level comprises buffering at least one circuit. . 10. The method of claim 9, wherein moving at least one circuit between the bin assigned to the second voltage level and the bin assigned to the first voltage level comprises cloning at least one circuit. . A method performed in the design of a semiconductor chip for placing a circuit on an integrated circuit, Assigning the circuit set to a first voltage level of the plurality of voltage levels; Selecting a seed circuit from the circuit set; Assigning the seed circuit to a second one of the plurality of voltage levels; Generating a voltage island around the seed circuit; A method performed at design of a semiconductor chip for disposing a circuit on an integrated circuit comprising a. 21. The method of claim 1 or 20, wherein the second voltage level is greater than the first voltage level. 21. The method of claim 1 or 20, wherein the second voltage level is less than the first voltage level. 21. The method of claim 20, further comprising: generating a first voltage island around a portion of a circuit set assigned to the first voltage level; Moving at least one circuit between the first voltage island and a voltage island around the seed circuit, hereinafter referred to as a second voltage island, to meet a predetermined criterion How to include more. 24. The method of claim 23, wherein moving at least one circuit between the first voltage island and the second voltage island to meet a predetermined criterion comprises buffering the at least one circuit. How to be. 24. The method of claim 23, wherein moving at least one circuit between the first voltage island and the second voltage island to meet a predetermined criterion comprises cloning the at least one circuit. Way. 24. The circuit of claim 23, wherein the second voltage is higher than the first voltage and the at least one circuit is a high switching circuit that is non-critical, and wherein the at least one circuit is configured to drive the second voltage from the second voltage island. 1 voltage is moved to the island. 24. The method of claim 9 or 23, wherein the predetermined criterion comprises minimizing power subject to performance limitations. 24. The method of claim 9 or 23, wherein the predetermined criterion comprises maximizing performance subject to power limitations. 24. The method of claim 23, wherein the at least one circuit is moved from the first voltage island to a second voltage island, the second voltage is higher than the first voltage, and the at least one circuit is a threshold circuit. How to be. 24. The method of claim 23, further comprising: selecting a seed circuit from the circuit set; Assigning the seed circuit to a second voltage level of the plurality of voltage levels; Generating a second voltage island around the seed circuit; Moving at least one circuit between the first voltage island and the second voltage island to meet a predetermined criterion, Repeating until the predetermined criterion is met. 31. The method of claim 30, wherein one of the seed circuits is selected after an existing voltage island assigned to the second voltage level, an additional voltage island is generated around the one seed circuit, and the additional voltage. The island and the existing voltage island are merged to produce a larger voltage island. 31. The method of claim 30, wherein the repeating step causes one of the second voltage islands to fall below a minimum capacity. 33. The method of claim 32, wherein the second voltage is higher than the first voltage and the method further comprises moving an adjacent threshold circuit to the one voltage island. 33. The method of claim 32, wherein the second voltage is higher than the first voltage and the method further comprises moving an adjacent low switching circuit to the one voltage island. Developing the first integrated circuit plan configuration; Assigning the circuit set to a first voltage level of the plurality of voltage levels, Dividing the circuit set into a plurality of bins; Assigning one of the bins to a second voltage level of the plurality of voltage levels; Assigning a circuit in the one bin to the second voltage level; Assigning a second circuit bin from the next additional step of multiple circuit bins to the second voltage level until an integrated circuit plan that meets a predetermined requirement is achieved; Repeating assigning to the second voltage level and converting one or more circuits between the bin assigned to the second voltage level and the bin assigned to the first voltage level. A storage medium having stored therein a computer program having an integrated circuit design tool for performing the task. 36. The storage medium of claim 35, wherein the storage medium comprises a recordable medium. 36. The storage medium of claim 35, wherein the storage medium comprises a transferable medium. 36. The integrated circuit design tool of claim 35, wherein the integrated circuit design tool assigns additional bins to the second voltage level, assigns circuitry within the additional bins to the second voltage level, until the predetermined criterion is met. Moving at least one circuit between a bin assigned to a second voltage level and a bin assigned to the first voltage level.