JP2006049638A - Semiconductor device and method for designing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device and a method for designing the semiconductor device capable of realizing acceleration especially in a system LSI. <P>SOLUTION: A plurality of clock signals are supplied from clock pulse generators 11a, 11b to respective function blocks 10a, 10b; hierarchy in a unit of the function blocks 10a, 10b is developed in the net list of a semiconductor chip which is hierarchically constituted in the unit of the function blocks 10a, 10b; and circuits to which the same clock signal is supplied are extracted and hierarchically constituted to construct a net list including circuit blocks 12a, 12b in each clock domain, and to perform arrangement/wiring in the semiconductor chip in a unit of the circuit blocks 12a, 12b. Consequently, clock latency from the clock pulse generators 11a, 11b is reduced and acceleration can be attained. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor device design method and a semiconductor device, and more particularly to a semiconductor device design method and a semiconductor device having a plurality of functional blocks and a plurality of clock signals having different frequencies, such as a system LSI. It is about technology.

  According to a study by the present inventor, the following can be considered regarding the clock signal technology of the semiconductor device.

  For example, Patent Document 1 discloses a semiconductor integrated circuit that can easily and accurately perform phase management between clock domains to which a plurality of different frequencies are input. In this semiconductor integrated circuit, a phase comparison circuit and a variable delay circuit set according to the comparison result of this phase comparison circuit are added in place to multiple clock domains formed by the output of the divided clock of the PLL circuit. It has been configured. As a result, phase management between clock domains can be performed by an actual circuit without performing circuit simulation or the like, and phase management can be easily and highly accurately performed.

  Patent Document 2 discloses an integrated circuit device that is not easily affected by crosstalk noise, power supply noise, and the like and that can suppress clock skew by a short clock distribution wiring length to the interface circuit. That is, in this integrated circuit device, the clock distribution wiring and the clock driver are arranged on the outermost peripheral portion of the chip which is hardly affected by power supply noise and the like, and the clock input buffer and the PLL circuit are arranged in the chip corner portion.

  Patent Document 3 discloses a semiconductor integrated circuit that can alleviate a skew caused by a relay buffer from an input point of a clock signal to a distribution destination. The semiconductor integrated circuit receives a clock signal having a lower frequency than the clock signal supplied to the terminal circuit block from the outside, and receives the output of the second PLL circuit to supply the clock signal to the terminal circuit block. And a first PLL circuit. That is, since a low-frequency clock signal is input to the semiconductor integrated circuit from the outside, the number of relay buffer stages from the clock signal input point to the distribution destination can be reduced, and the skew can be reduced.

Patent Document 4 discloses a semiconductor device capable of suppressing clock skew between a plurality of modules having different clock transmission paths. In this semiconductor device, a PLL circuit is provided for each module to suppress clock skew and increase the speed.
JP 2004-072680 A JP 2004-015032 A JP 11-224137 A JP-A-10-161769

  By the way, as a result of examination by the present inventor on the clock signal technology of the semiconductor device as described above, the following has been clarified.

  For example, semiconductor devices such as system LSIs and SOCs (System On a Chip) include a large number of functional blocks inside as functions become diversified and complicated. When attention is paid to individual functional blocks, there are many cases where the operating frequency is different for each functional block, or when a plurality of operating frequencies are used in one functional block.

  When designing such a system LSI or the like, the design is usually performed in units of functional blocks. That is, arrangement and wiring (layout) such as arrangement of each functional block (floor plan), wiring in each functional block, connection wiring between each functional block, and the like is performed for each functional block. Furthermore, when using a hierarchical layout design method, a functional block is usually defined as a lower hierarchy. Then, after generating detailed timing constraints for each functional block in the lower hierarchy from the timing constraints of the entire semiconductor chip in the upper hierarchy, placement and wiring of each functional block is performed so as to satisfy this detailed timing constraint.

  However, if such a functional block unit design is used, a flip-flop (hereinafter abbreviated as F / F) that connects dense data transfer paths in the same clock domain, depending on the logical scale of the functional block, floor plan, etc. However, there may be a situation in which they are arranged at a long distance. In this case, in order to eliminate the clock skew with respect to the F / F in the same clock domain, the general layout tool eliminates the clock delay of the other clock wiring in the clock domain so as to match the wiring delay of the long-distance clock wiring. Will adjust. That is, the clock latency increases. If so, there is a concern that the influence of process variations, noise, and the like will increase, making high-speed data transfer difficult.

  Under these circumstances, as shown in Patent Documents 1 to 4, there are various techniques for improving the accuracy of the clock signal by devising the circuit and layout. However, since these are essentially based on the functional block unit design, the problem that the clock latency is increased as described above cannot be solved.

  In addition, system LSIs and the like are strongly required to improve design efficiency in accordance with diversifying product specifications. However, when a normal hierarchical design method is used, if a plurality of operating frequencies exist in one functional block, timing constraints in the functional block may be complicated, and the design efficiency may be reduced.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device design method and a semiconductor device capable of realizing high speed, particularly in a system LSI or the like.

  Another object of the present invention is to provide a semiconductor device design method capable of improving design efficiency, particularly in a system LSI, and in particular, facilitating easy timing design. It is in.

  The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

  Of the inventions disclosed in the present application, the outline of typical ones will be briefly described as follows.

  The semiconductor device design method according to the present invention is realized by using a computer.

  The semiconductor device design method according to the present invention searches for circuit description data for circuit description data of a semiconductor chip including a plurality of functional block unit hierarchies, and a sequential circuit connected to the same clock signal and the sequential circuit. Extracting the combinational circuit connected to the layer, layering the extracted sequential circuit and combinational circuit as one circuit block, and constructing circuit description data including the layered circuit block; And arranging and wiring the entire semiconductor chip in units of the circuit blocks.

  As a result, the semiconductor chip can be arranged and wired using circuit blocks grouped in units of clock domains, so that the clock latency in each clock domain is reduced and the speed of the semiconductor chip can be increased. Become. Further, by using a circuit block in units of clock domains, timing constraints at the time of placement and routing are simplified, so that timing design is facilitated.

  In addition, the semiconductor device design method according to the present invention retrieves circuit description data including the hierarchical circuit blocks, extracts a circuit using a gated clock for each of the hierarchical circuit blocks, The method includes a step of adding an attribute to the circuit, and a step of performing placement and routing in the hierarchized circuit block so that the circuit to which the attribute is added is closely arranged.

  As a result, in the circuit block grouped in clock domain units, circuits using gated clocks can be placed closer to each other, reducing gated cells and designing gated clock timing. Can be facilitated.

  In the semiconductor device design method according to the present invention, the circuit description data including the hierarchized circuit blocks is searched, and data transfer is performed between the hierarchized circuit blocks using mutually different clock frequencies. Extracting a data path, adding a bridge circuit having a function of reliably transferring data between different clock frequencies to the extracted data path, and circuit description data to which the bridge circuit is added And a step of constructing.

  As a result, the timing constraints associated with so-called multi-clock data transfer can be relaxed at the stage of circuit design using a netlist or the like, and subsequent layout design can be easily performed.

  The semiconductor device design method according to the present invention automatically customizes circuit description data of a semiconductor chip based on a preset procedure, and performs placement and routing using the customized circuit description data.

  In other words, according to various design requirements, the circuit description data can be customized from various viewpoints, whereby placement and routing can be easily performed.

  Here, the preset procedure is, for example, extracting a sequential circuit operating with the same clock signal and a combinational circuit accompanying it from circuit description data, and layering these extracted circuits as circuit blocks. The circuit description data including the circuit block is generated.

  Further, the preset procedure is such that when the circuit preceding the memory block is extracted from the circuit description data and the extracted circuit is distributed to more memory blocks than desired, the previous stage of each memory block is extracted. The extracted circuit is duplicated, and circuit description data including the duplicated circuit is generated. As a result, the input timing constraint on the memory block can be relaxed at the stage of circuit design using a netlist or the like, and layout design such as subsequent placement and routing can be easily performed.

  Further, the preset procedure is such that a test mode enable signal is extracted from circuit description data, and when the extracted enable signals are distributed more than a desired number, a stage by a pipeline circuit is performed with respect to the enable signal. The division is added and circuit description data including the pipeline circuit is generated. As a result, the timing constraint on the test mode enable signal can be relaxed at the stage of circuit design using a netlist or the like, and subsequent layout design can be easily performed.

  The semiconductor device according to the present invention includes a plurality of circuit blocks composed of circuits arranged together, and a different clock signal is supplied to each of the plurality of circuit blocks, and each of the plurality of circuit blocks operates with the same clock signal. It is comprised by the circuit which performs. Such a configuration is particularly useful in a system LSI.

  Among the inventions disclosed in the present application, effects obtained by typical ones will be briefly described as follows.

  By arranging and wiring the inside of the semiconductor chip using circuit blocks collected in units of clock domains, the clock latency in each clock domain is reduced, and the speed of the semiconductor chip can be increased. In addition, by using a circuit block in units of clock domains, timing constraints are simplified and timing design can be facilitated.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. Note that components having the same function are denoted by the same reference symbols throughout the drawings for describing the embodiment, and the repetitive description thereof will be omitted. Further, in the description of the present embodiment, in order to make the characteristics of the present invention easy to understand, the description will be made mainly by comparing the prior art with the present invention.

  FIG. 1 is a diagram for explaining an example of a logical level configuration concept in a semiconductor device according to an embodiment of the present invention in comparison with the prior art. FIG. 1A is a configuration conceptual diagram according to the prior art. (B) is a conceptual diagram of the configuration according to the present invention.

  First, in the prior art, a semiconductor chip is configured in units of functional blocks. Therefore, as shown in FIG. 1A, the semiconductor chip has, for example, two functional blocks A (10a) and B (10b), and each of the two functional blocks A (10a) and B (10b). The clock signal is supplied from the clock pulse generator A (11a) and the clock pulse generator B (11b). In each functional block, for example, the F / F (13a) supplied with the clock pulse generator A (11a) is directed to the F / F (13b) supplied with the clock pulse generator B (11b). Data transfer is performed.

  On the other hand, in the present invention, a circuit block is formed by circuits that operate with the same clock signal, and a semiconductor chip is configured with this circuit block as a unit. That is, each circuit block is a clock domain unit. Therefore, as shown in FIG. 1B, the semiconductor chip includes a circuit block 12a operated by the clock pulse generator A (11a) and a circuit block 12b operated by the clock pulse generator B (11b). It becomes composition. As a result, the circuits in the functional blocks A (10a) and B (10b) described above are separated based on the operating clock signal. In each of the circuit blocks 12a and 12b, clock trees 14a and 14b are formed starting from the clock pulse generators A (11a) and B (11b), respectively.

  When placement and routing is performed based on such a clock domain unit circuit block, for example, a chip layout as shown in FIG. 2 is obtained. FIG. 2 is a diagram for explaining the outline of the chip layout of the semiconductor device according to the embodiment of the present invention in comparison with the prior art. FIG. 2A is a layout wiring example according to the prior art. ) Is an example of placement and routing according to the present invention.

  First, in the prior art, as shown in FIG. 2A, placement and routing are performed in units of functional blocks, so that a situation where the clock latency increases may occur. That is, it is assumed that the semiconductor chip includes three functional blocks A (20a), B (20b), and C (20c) as shown in FIG. The functional block A (20a) includes a circuit 21a operating with the clock α, a circuit 22a operating with the clock β, and a circuit 23a operating with the clock γ, and the functional block B (20b) operates with the clock α. 21b and a circuit 22b that operates with the clock β and a circuit 23b that operates with the clock γ, and the functional block C (20c) includes a circuit 21c that operates with the clock α and a circuit 22c that operates with the clock β. .

  Then, for example, since the circuits 21a to 21c that operate with the clock α exist across the three functional blocks A (20a), B (20b), and C (20c), the circuit of FIG. The wiring delay corresponding to the radius of the circle shown in FIG. 5) and the delay due to the clock buffer 24 occur, and the clock latency increases.

  On the other hand, in the present invention, as shown in FIG. 2B, the placement and routing is performed in a circuit block in units of clock domains. Then, the circuits 21a to 21c that operate with the clock α, the circuits 22a to 22c that operate with the clock β, and the circuits 23a and 23b that operate with the clock γ included in the functional blocks A (20a) to C (20c) described above, respectively. The circuit blocks 25a, 25b, and 25c in units of three clock domains are arranged together. As a result, for example, the clock latency of the clock α falls within the distance of the circuit block 25a, and the clock latency can be reduced as can be seen from the size of the radius of the circle shown in FIG.

  In particular, when a hierarchical design method is used, the functional blocks are usually hierarchized as shown in FIG. 2A, so that the timing constraints on the functional blocks become complicated with the number of operating clocks. . Therefore, by performing blocking (hierarchization) in units of clock domains as shown in FIG. 2B, it is possible to simplify the timing constraints for each circuit block. Furthermore, since the data transfer between the circuit blocks is often not a relatively dense transfer, it is considered that the timing constraint in this part is not a problem. As a result, the timing design is facilitated, the design efficiency can be improved, and the design period can be shortened.

  By the way, such a layout and wiring in units of clock domains is formed by performing editing, restructuring, etc. (customization) as described below on a net list or the like using, for example, a design apparatus as shown in FIG. Is done. FIG. 15 shows a configuration example of a design apparatus used in the semiconductor device design method according to the embodiment of the present invention. (A) is an example of the entire configuration including a computer, and (b) is an internal configuration of the computer. It is a structural example.

  In this description, the system LSI design is taken as an example, with reference to FIGS. FIG. 3 is a diagram for explaining an example of the procedure in the method for designing a semiconductor device according to one embodiment of the present invention. FIG. 3A is a conceptual diagram of a logic level configuration in a system LSI before customization. (B) is a conceptual diagram of the layout level. FIG. 4 is a conceptual diagram of a logical level configuration after the flattening process is performed on FIG. FIG. 5 is a conceptual diagram of a logic level configuration after performing extraction processing on the circuit of the same clock signal with respect to FIG. FIG. 6 shows a state where customization is completed after performing the hierarchization process and the floor plan for FIG. 5, (a) is a conceptual diagram of the logic level configuration in the system LSI after customization, (b) FIG. 4 is a structural conceptual diagram of the layout level.

  15A includes, for example, a computer 150 including a CPU (Central Processing Unit) 150a, a RAM (Random Access Memory) 150b, an HDD (Hard Disk Drive) 150c, and the like, and a keyboard for inputting instructions to the computer. 152 and a display 153 for displaying a processing result by the computer 150, and these are connected to each other by a communication cable 151.

  For example, as shown in FIG. 15B, the computer 150 includes a storage unit 154 for circuit description data (1), a customization processing unit 155 for customizing the circuit description data (1), and a circuit after customization. The storage unit 156 stores the description data (2), and the placement and routing processing unit 157 that performs the placement and routing using the circuit description data (2). Among these, the storage units 154 and 156 are mainly realized by the HDD 150c, and the customization processing unit 155 and the placement and routing processing unit 157 are realized by processing such as the CPU 150a and the RAM 150b based on a program.

  The customization processing unit 155 receives an extraction condition from the circuit expansion processing unit 155a that expands the circuit with respect to the circuit description data (1) and the keyboard 152, and the circuit corresponding to the extraction condition from the expanded circuit. And a circuit extraction / attribute addition unit 155b for adding an attribute to the extracted circuit, and layering based on the added attribute, and circuit description data (2) including a circuit block accompanying the layering Includes a circuit block generation unit 155c for generating.

  Then, using such a design apparatus, for example, placement and routing in units of clock domains is realized by a design procedure as shown in (1) to (5) below.

  (1) With respect to a semiconductor chip net list stored in the storage unit 154 and hierarchized by a plurality of functional blocks, the circuit development processing unit 155a expands the functional block hierarchy and generates a flat net for the entire semiconductor chip. Generate a list. Here, the net list is a so-called text description of a circuit diagram, and is circuit description data in which circuit elements (cells) and connection states between the cells are described.

  That is, as shown in FIG. 3A, when a semiconductor chip includes a plurality of functional blocks 30a to 30c, a net list describing the semiconductor chip also has a hierarchical structure in units of functional blocks 30a to 30c. Therefore, this hierarchy is expanded to generate a net list having a flat logical configuration without blocks (hierarchies) as shown in FIG.

  In the semiconductor chip shown in FIG. 3A, a plurality of clock signals are supplied from a plurality of clock pulse generators 34a to 34c to each of the functional blocks 30a to 30c. As shown in FIGS. 3A and 3B, the functional block 30a includes circuits 31a, 32a, and 33a corresponding to a plurality of clock signals. Similarly, the functional block 30b includes the circuits 31a, 32a, and 33a. Includes circuits 31b, 32b, and 33b, and the functional block 30c includes circuits 31c and 32c.

  (2) When the same clock domain is designated as the extraction condition for the circuit extraction / attribute addition unit 155b, the circuit extraction / attribute addition unit 155b searches the flat netlist of the entire semiconductor chip and performs F for each clock domain. / F is extracted. At this time, the starting point of the clock domain is given by designation / instruction using the keyboard 152 or the like, or is a convergence point obtained by tracing the F / F clock. Then, tracing is performed from the starting point of the clock domain, F / F is extracted, and an attribute is added to the extracted F / F.

  In other words, F / Fs connected to the same clock signal are extracted from the logical configuration as shown in FIG. 4, and the connection relationship between the clock signal and the F / F is arranged as in the logical configuration shown in FIG. In FIG. 4, for example, the F / Fs in the three circuits 32a to 32c are extracted and attributed as circuits operating on the clock pulse generator 34a, and as shown in FIG. 5, below the clock pulse generator 34a. The F / Fs in the three circuits 32a to 32c are arranged in a logical configuration.

  (3) The circuit extraction / attribute addition unit 155b searches the flat netlist of the entire semiconductor chip and extracts the combination logic between the extracted F / Fs. Then, an attribute is added to the extracted combination logic. That is, in FIG. 5, for example, a combinational circuit (not shown in FIG. 5) connected between the F / Fs in the circuits 32a to 32c is extracted as a circuit that operates in the clock pulse generator 34a. An attribute indicating the operation at 34a is added. In other words, the attributes are different for different clock domains.

  (4) The circuit block generation unit 155c stratifies the netlist for each added attribute to construct a circuit block. Then, the hierarchical netlist is stored in the storage unit 156. That is, as shown in FIG. 6A, the three circuits 32a to 32c, 31a to 31c, and 33a to 33b classified for each of the clock pulse generators 34a, 34b, and 34c are hierarchized, and three circuit blocks 60a. , 60b, 60c. That is, a circuit block for each clock domain is constructed. When combinational logic exists between the blocks, the combinational logic is included in the circuit block on the source side (F / F output side).

  (5) The placement and routing processing unit 157 performs placement and routing (floor plan and layout) based on the net list hierarchized in units of clock domains. As a result, as shown in FIG. 6B, circuit blocks 60a to 60c in units of clock domains are formed in the semiconductor chip, and circuits that operate with the same clock signal are arranged close to each other in each of the circuit blocks 60a to 60c. It becomes a state.

  In this example, the F / F of the same clock domain is extracted based on the net list. However, not only the net list but also the RTL description that is a circuit description at the register transfer level or after logic synthesis similar to the net list. It is also possible to extract from circuit description data such as an intermediate level description.

  Further, the process of developing the functional block unit hierarchy described in FIG. 4 is not necessarily performed first, and may not be performed in some cases. That is, for example, each circuit may be provided with a function block attribute and a clock domain attribute, and in this state, circuits having the same clock domain attribute may be extracted and layered.

  In the semiconductor chip formed as described above, the clock latency can be reduced as described with reference to FIG. 2 and the like, but the effect shown in FIG. 7 can be further obtained by the reduction of the clock latency. it can. FIG. 7 is a diagram for explaining an example of the effect of the semiconductor device according to the embodiment of the present invention in comparison with the prior art. FIG. 7A is an operation according to the prior art, and FIG. The operation according to the present invention is shown. Here, as shown in FIGS. 7A and 7B, the same clock is supplied from the clock pulse generator 70 to the two F / Fs (71a and 71b) via the clock tree. Assume that data is transferred between F / Fs (71a, 71b).

  First, in the prior art, as shown in FIG. 7A, since the latency of the clock tree 72 composed of a plurality of branch wirings and clock buffers is large, the two F / Fs (71a, 71b) between the two due to process variations or the like In view of the clock skew, a relatively large setup margin 74 is required. In this case, it is necessary to secure at least the clock cycle time by adding the setup margin 74 to the data transfer time between the two F / Fs (71a, 71b).

  On the other hand, in the present invention, as shown in FIG. 7B, since the latency of the clock tree 73 is small, the influence of process variation or the like is reduced, and a relatively small setup margin 75 may be ensured. Therefore, as shown in FIG. 7B, it is possible to provide a margin for the data transfer time between the F / Fs (71a, 71b) as compared with the prior art. That is, the timing design can be facilitated. Also, based on the same data transfer time as in the prior art, the clock cycle time can be shortened by the amount that the setup margin is reduced. This makes it possible to increase the speed.

  By the way, in the above, the customization method of extracting F / F etc. for every clock domain from a net list etc., adding an attribute to this, and making it a block was described. As described above, it is possible to improve the efficiency of various designs by using a design method for customizing a netlist or the like. An example of these will be described with reference to FIGS.

  FIG. 8 is a diagram for explaining an example of processing when a gated clock is included in the method for designing a semiconductor device according to one embodiment of the present invention. FIG. FIG. 7B is an explanatory diagram when the gated clock is extracted. FIG.

  Here, for example, as shown in FIG. 8A, four functional blocks A (81a), B (81b), C (81c), and D (81d) supplied with the same clock from the clock pulse generator 80 are used. Suppose that a gated clock is applied to the circuits 82c and 82d of the two functional blocks C (81c) and D (81d). First, when the gated clock is not extracted based on the design of the functional block unit, a layout distance is generated between the functional blocks C (81c) and D (81d), as shown in FIG. Gated cells 83 and 84 are inserted into the circuits 82c and 82d, respectively.

  On the other hand, in addition to blocking (hierarchization) in units of clock domains, if a circuit that uses a gated clock is further extracted and an attribute is added, a circuit that is hierarchized based on this attribute on the netlist It becomes possible to further construct blocks and the like. Then, as shown in FIG. 8B, among the circuit blocks 86 in units of clock domains, the circuit blocks 87a of the circuits 82a and 82b that do not use the gated clock and the circuits 82c and 82d that use the gated clock. The blocks 87b can be classified and arranged.

  That is, the circuits 82c and 82d of the functional blocks C (81c) and D (81d) in FIG. Thus, for example, the above-described circuits 82c and 82d can be driven using one gated cell 85, and gated cell reduction and gated clock timing design can be facilitated. In this example, the circuit using the gated clock is hierarchized by hierarchizing on the netlist, but the placement and routing tool (placement and routing processing unit 157 in FIG. 15B) is arranged. Thus, if a function capable of changing the arrangement based on the attribute is provided, the same can be realized without hierarchization.

  FIG. 9 is a diagram for explaining an example in which extraction processing between clock ratio domains is performed in the method for designing a semiconductor device according to one embodiment of the present invention. FIG. FIG. 4B is a schematic diagram of the configuration between ratio domains, and FIG. FIG. 10 is a diagram for explaining an example in which extraction processing between clock ratio domains is not performed in the conventional semiconductor device design method studied as a premise of the present invention. A schematic diagram of the configuration between clock ratio domains, (b) is an operation explanatory diagram of (a).

  First, when extraction processing between clock ratio domains is not performed, a circuit block A (100a) operating with clock A and a circuit block B (100b) operating with clock B are directly connected as shown in FIG. Is done. Here, the clock B has a frequency half that of the clock A. Then, the data transfer from the circuit block A (100a) to the circuit block B (100b) is ideally “id1” as shown in FIG. 10B, but in practice, variation in clock latency, etc. As a result, a clock skew “Δcw” occurs. As a result, the hold specification “min_hold1” and the setup specification “max_setup1” are generated, and the actual designable width of the data transfer time is “Δdw1”.

  Further, the data transfer from the circuit block B (100b) to the circuit block A (100a) is ideally “id2” as shown in FIG. 10B, but in practice, the clock skew “Δcw” ”Causes a hold definition“ min_hold2 ”and a setup definition“ max_setup2 ”. However, in this case, there is no data transfer time that satisfies both the hold specification “min_hold2” and the setup specification “max_setup2”, and the design becomes impossible.

  On the other hand, when performing extraction processing between clock ratio domains, as shown in FIG. 9A, a circuit block A (90a) that operates on the netlist based on the clock A and a circuit block B (90b) that operates on the clock B. And a net list in which the bridge circuit 91 is inserted is generated. Here, the clock B has a frequency half that of the clock A. The bridge circuit 91 includes, for example, an F / F (92a) connected to the circuit block A (90a) and operating with the clock A, and an F / F (92a) connected to the circuit block B (90b) and operating with the clock B ′ ( 92b) and a frequency dividing circuit that generates a clock B ′ having a ½ cycle based on the clock A, and configured to transfer data between the two F / Fs (92a, 92b). Yes. The bridge circuit 91 is also called a synchronizer.

  With such a configuration, data transfer from the circuit block A (90a) to the circuit block B (90b) is performed via the F / F (92a) and the F / F (92b). At this time, in the data transfer from the F / F (92a) to the F / F (92b), the influence of the clock skew hardly occurs. Therefore, the data transfer time restriction from the circuit block A (90a) to the circuit block B (90b) is substantially caused by the clock skew “Δcw” between the F / F (92b) and the circuit block B (90b). . In other words, the substantial restrictions are the hold definition “min_hold4” and the setup definition “max_setup4” as shown in FIG. 9B, and thereby, the F / F (92b) to the circuit block B (90b). The designable width of the data transfer time is “Δdw3”.

  The data transfer from the circuit block B (90b) to the circuit block A (90a) is performed via the F / F (92b) and the F / F (92a). At this time, in the data transfer from the F / F (92b) to the F / F (92a), there is almost no influence of the clock skew, and the transfer from the F / F (92a) to the circuit block A (90a). However, since the same clock signal is transferred, no particular problem occurs. Therefore, the restriction on the data transfer time from the circuit block B (90b) to the circuit block A (90a) is substantially caused by the clock skew “Δcw” between the circuit block B (90b) and the F / F (92b). Arise. That is, the substantial restrictions are the hold definition “min_hold5” and the set-up definition “max_setup5” as shown in FIG. 9B, and thereby the circuit block B (90b) to the F / F (92b). The designable width of the data transfer time is “Δdw4”. Therefore, in any case, there is a designable width of the data transfer time.

  Therefore, from the net list or the like, a data path that performs data transfer using different clock frequencies between circuit blocks is extracted, an attribute is added to the data path, and a bridge circuit 91 is inserted based on the attribute. A net list including the circuit 91 is generated. The net list of the bridge circuit 91 itself to be inserted is stored in advance in the HDD 150c or the like in a form corresponding to the attribute. As a result, the timing margin of the data transfer can be increased between circuit blocks operating at different clock frequencies, so that it is possible to facilitate timing design by subsequent arrangement and the like.

  FIG. 11 is a diagram for explaining an example of processing in the case where a circuit having clock selection is included in the method for designing a semiconductor device according to the embodiment of the present invention. An explanatory diagram when the provided circuit is not extracted, and (b) is an explanatory diagram when the circuit provided with clock selection is extracted.

  First, as shown in FIG. 11A, the circuit 110 having clock selection is included in the circuit blocks 111a and 111b in two clock domain units. At this time, the circuit 110 having clock selection is provided. If the circuit 110 is not extracted, there is a possibility that the circuit 110 is arranged at an appropriate position in one circuit block, and as a result, the circuit 110 is arranged at a long distance from the other circuit block.

  Therefore, as shown in FIG. 11B, the circuit 110 having this clock selection is included in the circuit block 112a of one main clock domain, and the timing constraint on the circuit block 112a is satisfied. At this time, by extracting and adding attributes to the circuit 110 and differentiating, the length of the clock path from the circuit 110 to the circuit block 112b of the other clock domain and the timing constraint thereof are taken into consideration. This circuit 110 can be arranged as close as possible to the circuit block 112b. As a result, the timing design can be made more efficient.

  FIG. 12 is a diagram for explaining an example of processing in the case where a test mode enable signal is included in the method for designing a semiconductor device according to one embodiment of the present invention. FIG. 6C is an explanatory diagram when the test mode enable signal is not extracted, and FIG. 10C is an explanatory diagram when the test mode enable signal is extracted. FIG. 13 is a diagram for explaining the outline of the test mode of FIG.

  First, the test mode is a mode for testing data transfer between F / Fs by a so-called scan chain method. As shown in FIG. 13, a selector circuit or the like is used for F / F data input or clock input. Added to enable switching of input data and input clock. The outline of the test operation is that, in the scan-in stage, data of each F / F is set by the shift operation by the low-speed clock, and then, in the capture stage by the mode switching signal, two high-speed clock pulses are generated and the F / F is generated. In the scan-out stage by the mode switching signal, the F / F data after the data transfer is read out.

  In this capture stage, since it is necessary to test the data path of the user data in the F / F, the scan data is scanned using the test mode enable signal (test enable) in the time between two high-speed clock pulses. It is necessary to switch between the path and the user data path. Thus, timing accuracy is required for the test mode enable signal.

  In such a case, when the test mode enable signal is not extracted, as shown in FIGS. 12A and 12B, the enable signal is transferred between two high-speed clock pulses due to the timing skew of the test mode enable signal. This makes it difficult to switch. That is, since the test mode enable signal is added to all the F / Fs in the semiconductor chip, the latency becomes very large and variations occur.

  In FIG. 12A, since the enable signal is an external input, the variation width is very large. In FIG. 12B, the enable signal is generated with reference to the input clock of the F / F, but the generated enable signal may be distributed in plural before reaching the F / F to be actually tested. . As a result, a situation in which the timing accuracy cannot be satisfied may occur.

  Therefore, when the test mode enable signal is extracted from the net list and the extracted enable signals are distributed more than the desired number, the stage division by the pipeline circuit 120 as shown in FIG. In addition, a net list including the pipeline circuit 120 is generated. As a result, the timing accuracy of the enable signal in the test mode can be improved at the netlist stage, and the timing adjustment by the subsequent placement and routing becomes easy.

  FIG. 14 is a diagram for explaining an example of processing when a memory block is included in the method for designing a semiconductor device according to one embodiment of the present invention. FIG. FIG. 6B is an explanatory diagram when the F / F in the previous stage of the memory block is extracted.

  First, when the F / F at the previous stage of the memory block is not extracted, the output signal of the F / F (140) is distributed to a plurality of memory blocks (RAM) as shown in FIG. There are cases where the margin of the input timing of the RAM is reduced. Accordingly, when the F / F (140) in the previous stage of the RAM is extracted from the net list, and the extracted F / F (140) is distributed to more RAMs than desired, FIG. As shown in FIG. 4, the F / F is duplicated in the previous stage of each RAM, and a netlist including the duplicated F / F (140a, 140b, 140c) is generated.

  Alternatively, if the F / F (140) in the previous stage of the RAM is extracted from the net list and the extracted F / F (140) is distributed to more RAMs than desired, the F in the previous stage is further extracted. The combinational circuit 141 between the F / F (140) and the preceding F / F is extracted, and as shown in FIG. 14C, the extracted combinational circuit 141 and the F / F are set in the previous stage of each RAM. May be duplicated as As a result, the margin of the input timing to the memory block can be improved at the stage of the net list, and the timing adjustment by the subsequent placement and routing is facilitated.

  If you use a design method that extracts a part that meets a desired condition from a netlist, etc., and adds attributes to it, you can flexibly respond to various design requirements, not limited to those described above It becomes possible to do. For example, if it is desirable to place them in the vicinity from the viewpoint of the same power supply group, before placement and routing, the circuits of the same power supply are extracted from the netlist etc., and attributes are added to them, and blocks based on this attribute are blocked. It is good to make it. This can improve design efficiency.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment, and various modifications can be made without departing from the scope of the invention. Needless to say.

  The method for designing a semiconductor device and the semiconductor device of the present invention are particularly useful when applied to a system LSI having a large number of functional blocks, a design tool thereof, and the like. It is widely applicable including logic products and design tools.

FIG. 2 is a diagram for explaining an example of a configuration concept of a logic level in a semiconductor device according to an embodiment of the present invention in comparison with the prior art, (a) is a configuration conceptual diagram according to the prior art, and (b). These are the conceptual diagrams of a structure by this invention. 1A and 1B are diagrams for explaining an outline of a chip layout of a semiconductor device according to an embodiment of the present invention in comparison with the prior art, in which FIG. It is an example of arrangement wiring according to the invention. 2A and 2B are diagrams for explaining an example of a procedure in a method for designing a semiconductor device according to an embodiment of the present invention, in which FIG. 1A is a conceptual diagram of a logic level configuration in a system LSI before customization, and FIG. FIG. 2 is a conceptual diagram of the layout level. FIG. 4 is a conceptual diagram of a logical level configuration after flattening processing is performed on FIG. 3. FIG. 5 is a configuration conceptual diagram of a logic level after performing extraction processing on a circuit of the same clock signal with respect to FIG. 4. FIG. 5 shows a state in which customization is completed by performing a hierarchization process and a floor plan on FIG. 5, (a) is a conceptual diagram of a logical level configuration in the system LSI after customization, and (b) is its layout It is a structure conceptual diagram of a level. 4A and 4B are diagrams for explaining an example of the effect of a semiconductor device according to an embodiment of the present invention in comparison with the prior art, where FIG. 5A is an operation according to the prior art, and FIG. 5B is an operation according to the present invention. Is shown. FIG. 7 is a diagram for explaining an example of processing when a gated clock is included in the method for designing a semiconductor device according to one embodiment of the present invention, and FIG. FIG. 7B is an explanatory diagram when a gated clock is extracted. It is a figure for demonstrating an example in the case of performing the extraction process between clock ratio domains in the design method of the semiconductor device by one embodiment of this invention, (a) is between clock ratio domains after an extraction process A schematic diagram of the configuration, (b) is a diagram for explaining the operation of (a). FIG. 7 is a diagram for explaining an example in which extraction processing between clock ratio domains is not performed in the semiconductor device design method according to the related art studied as a premise of the present invention, and FIG. Schematic diagram, (b) is a diagram for explaining the operation of (a). FIG. 7 is a diagram for explaining an example of processing when a circuit with clock selection is included in the method for designing a semiconductor device according to one embodiment of the present invention, and (a) shows a circuit with clock selection. An explanatory diagram in the case of not extracting, (b) is an explanatory diagram in the case of extracting a circuit having a clock selection. FIGS. 8A and 8B are diagrams for explaining an example of a process when a test mode enable signal is included in the method for designing a semiconductor device according to the embodiment of the present invention. FIGS. FIG. 6C is an explanatory diagram when no signal is extracted, and FIG. 10C is an explanatory diagram when a test mode enable signal is extracted. It is a figure for demonstrating the outline | summary about the test mode of FIG. FIG. 6 is a diagram for explaining an example of processing when a memory block is included in the method for designing a semiconductor device according to one embodiment of the present invention, and FIG. (B), (c) is an explanatory diagram when the F / F of the previous stage of the memory block is extracted. 1 is a configuration example of a design apparatus used for a semiconductor device design method according to an embodiment of the present invention; (a) is an overall configuration example including a computer; and (b) is an internal configuration example of a computer. .

Explanation of symbols

10a, 10b, 20a-20c, 30a-30c, 81a-81d functional blocks 11a, 11b, 34a-34c, 70, 80 clock pulse generators 12a, 12b, 25a-25c, 60a-60c, 86, 87a, 87b, 90a, 90b, 100a, 100b, 111a, 111b, 112a, 112b Circuit blocks 13a, 13b, 71a, 71b, 92a, 92b, 140, 140a to 140c Flip-flops (F / F)
14a, 14b, 72, 73 Clock trees 21a-21c, 22a-22c, 23a, 23b, 31a-31c, 32a-32c, 33a, 33b, 82a-82d, 110 circuit 24 clock buffer 74, 75 setup margin 83, 84 85 Gated cell 91 Bridge circuit 120 Pipeline circuit 141, 141a-141c Combination circuit 150 Computer 150a CPU
150b RAM
150c HDD
151 Communication Cable 152 Keyboard 153 Display 154,156 Storage Unit 155 Customization Processing Unit 155a Circuit Development Processing Unit 155b Circuit Extraction / Attribute Addition Unit 155c Circuit Block Generation Unit 157 Placement and Routing Processing Unit

Claims (12)

On the computer,
Extracting a sequential circuit connected to the same clock signal and a combinational circuit connected to the sequential circuit for circuit description data of a semiconductor chip including a plurality of functional block unit hierarchies;
Hierarchizing the extracted sequential circuit and the extracted combinational circuit as one circuit block, and constructing circuit description data including the hierarchized circuit block;
A method for designing a semiconductor device, comprising: performing a schematic arrangement in the semiconductor chip and a step of arranging and wiring in units of the hierarchical circuit blocks. On the computer,
Expanding the functional block unit hierarchy for circuit description data of a semiconductor chip including a plurality of functional block unit hierarchies, and generating circuit description data not including the expanded hierarchy;
Retrieving circuit description data not including the expanded hierarchy, and extracting a sequential circuit connected to the same clock signal and a combinational circuit connected to the sequential circuit;
Hierarchizing the extracted sequential circuit and the extracted combinational circuit as one circuit block, and constructing circuit description data including the hierarchized circuit block;
A method for designing a semiconductor device, comprising: performing a schematic arrangement in the semiconductor chip and a step of arranging and wiring in units of the hierarchical circuit blocks. The method of designing a semiconductor device according to claim 1,
To the computer,
Searching circuit description data including the hierarchical circuit blocks, extracting a circuit using a gated clock for each of the hierarchical circuit blocks, and adding an attribute to the extracted circuit;
And a step of performing placement and routing in the hierarchized circuit block so that the circuits to which the attribute is added are arranged close to each other. The method of designing a semiconductor device according to claim 1 or 2,
To the computer,
Retrieving circuit description data including the hierarchized circuit blocks, and extracting data paths performing data transfer between the hierarchized circuit blocks using mutually different clock frequencies;
Adding a bridge circuit having a function of reliably transferring data between different clock frequencies to the extracted data path;
And a step of constructing circuit description data to which the bridge circuit is added. In the design method of the semiconductor device of any one of Claims 1-4,
The circuit description data is a net list. A semiconductor device design method, wherein:   A design method for a semiconductor device, comprising: causing a computer to customize circuit description data of a semiconductor chip based on a preset procedure, and performing placement and routing using the customized circuit description data. The method for designing a semiconductor device according to claim 6,
The circuit description data is a net list. A semiconductor device design method, wherein: The method of designing a semiconductor device according to claim 6 or 7,
The preset procedure is to extract a sequential circuit that operates with the same clock signal from the circuit description data and a combinational circuit connected to the sequential circuit, hierarchize the extracted circuit as a circuit block, and A method for designing a semiconductor device, comprising generating circuit description data including a block. The method of designing a semiconductor device according to claim 6 or 7,
The preset procedure is such that when a circuit preceding the memory block is extracted from the circuit description data, and the extracted circuit is distributed to more memory blocks than desired, the previous stage of each memory block is extracted. A method for designing a semiconductor device, wherein the extracted circuit is duplicated and circuit description data including the duplicated circuit is generated. The method of designing a semiconductor device according to claim 6 or 7,
The preset procedure is to extract a test mode enable signal from the circuit description data, and when the extracted enable signals are distributed more than a desired number, a pipeline circuit is used for the enable signal. A design method of a semiconductor device, characterized by adding stage division and generating circuit description data including the pipeline circuit. A semiconductor device including a plurality of circuit blocks composed of circuits arranged together,
A different clock signal is supplied for each of the plurality of circuit blocks,
Each of the plurality of circuit blocks includes a circuit that operates with the same clock signal. The semiconductor device according to claim 11.
The semiconductor device is a system LSI.

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