JP3178371B2 - Design method of semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for designing a low-power semiconductor integrated circuit, and more particularly to a method for arranging and wiring a gated clock circuit.

[0002]

2. Description of the Related Art A semiconductor integrated circuit is generally designed as a clock synchronous circuit with an increase in scale. In recent years, there has been an increasing demand for low power LSI chips, and clock synchronous circuits (gated clock circuits) that reduce the power consumed by clock signals have been used.
An example of this is “IEE
International Solid-State Circuit Conference Digest of Technical
Papers, pp. 201-203 (1994 IEEE)
International Solid-Stat
e Circuits Conference, DIG
EST OF TECHNICAL PAPERS, p
p. 201-203) ".

FIG. 5 is a conceptual diagram showing the configuration of the prior art. As shown in FIG. 5, clock lines 58a and 58b
Are connected to the multi-input gates 52a and 52b, and the outputs of the multi-input gates 52a and 52b are connected to clock tree circuits 60A and 60B for each function. The clock tree circuits 60A and 60B include buffers 53 and 54 for amplifying a clock signal, and flip-flops 55a and 55b.
Are arranged in a tree shape. A selector circuit 57 is connected to input terminals of the multi-input gate by clock enable lines 56a and 56b. The clock control signal is supplied from the selector circuit 57 to the multi-input gates 52a, 52a.
b, the clock tree 60A, 6
Control the supply of the clock signal to OB.

[0004]

A problem of the conventional gated clock circuit is that a delay time difference (skew) between flip-flops (FF) to which a clock signal is supplied becomes large. This will be described with reference to FIGS.

In FIG. 5, F included in the circuit of function A
When the number of F55a is larger than the number of FF55b included in the function B circuit, the area occupied by the clock tree 60A occupies a larger chip than the area occupied by the clock tree 60B. Therefore, the multi-input gate 52
The wiring length from a to the FF 55a becomes longer, and the wiring delay becomes larger than the wiring delay from the multi-input gate 52b to the FF 55b. Further, the load driven by each buffer of the clock tree 60A is larger than the load driven by each buffer of the clock tree 60B, and the gate delay is also increased.

As described above, the buffer 51 to the FF 55a
And the delay between the buffer 51 and the FF 55b becomes large. Generally, this delay difference is absorbed by the redundant wiring that makes the wiring length of the clock line 58b longer than 58a.

However, the clock waveform input to the multi-input gate 52b becomes dull due to the wiring resistance and wiring capacitance of the redundant wiring, and skew occurs when the logical threshold voltage fluctuates. For example, as shown in FIG.
The clock waveform 70a of the input terminal of the multi-input gate 52b is completely free from the dullness of the clock waveform 70a of the input terminal 2a.
When 0b has a waveform dulling of 3.0 nsec, when the logical threshold voltage Vt changes by 10% from Vt ', the clock waveform 70b is delayed by 0.3 nsec from "L" to "H" as compared with the clock waveform 70a. And the skew increases.

The present invention has been made in view of the above-mentioned conventional problems.
Flip-flop supplied with a clock signal
Semiconductor that can eliminate the delay time difference (skew) between
An object of the present invention is to provide a method for designing a body integrated circuit .

[0009]

The present invention achieves the above object.
The root buffer and the root buffer
Multi-stage buffer that branches in order from the
With a clock tree structure consisting of a combination of
Of a semiconductor integrated circuit having a gated clock circuit
In total process, buffer of the gated clock circuit
Temporary cell after placing cells other than the
Buffer, temporary gate, circuit of each function connected to temporary gate
Clock tree consisting of flip-flops contained in
From the dedicated netlist for the gated clock circuit
Generating a netlist.
From the temporary netlist of the temporary clock tree.
Buffer stages to be input and number, final stage multi-input gate
Determining the number of devices, and
Cluster for each flip-flop included in the circuit
A function clustering step of performing ringing;
Clock circuit buffers and multiple input gates.
After the floor plan, and
In the cluster generated in the previous step,
Clustering between flip-flops, and
A position clock that determines the flip-flop driven by the port
Rastering process and location clustering process
Clusters that have been created can be further clustered between neighboring clusters.
To determine the circuit to be driven by the preceding buffer.
In the same way as in the
Determining the circuit to be driven by the fan.
It is a sign .

[0010]

[0011]

[0012]

[0013]

[0014]

[0015]

[0016]

According to the present invention, there is provided a gated clock circuit having a clock tree structure comprising a combination of a root buffer, a plurality of buffers sequentially branched from the root buffer, and a final-stage multi-input gate (NOR gate). By generating the connection relationship after arranging all the cells, and after clustering the FFs connected to the clock line for each function, the FFs whose arrangement is further close
By performing clustering among them, the load driven by each buffer and the multi-input gate can be made constant, and skew can be eliminated by such a design.

Further, according to the present invention, by inserting a multi-input gate at the last stage, a gated clock circuit having a clock tree structure is obtained, and redundant wiring is not required.
The occurrence of skew due to waveform dulling can be eliminated.

[0019]

[0020]

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram showing a configuration of an embodiment of the present invention.
2nd and 2nd stage buffer 13, multiple input gates 20a and 20 for controlling supply of clock signal to FF which is a leaf cell
b, FF30a, FF30b are connected in a tree shape to form a gated clock circuit.

The multi-input gate 20a is connected to the FF 30a included in the function A circuit, and the multi-input gate 20b is connected to the FF 30b included in the function B circuit. Clock enable lines 22a and 22b are connected to input terminals of the multiple input gates 20a and 20b that are not connected to the clock lines, respectively. The clock enable lines are connected to the selector circuit 21. The selector circuit 21 generates a clock control signal. The multi-input gate 20a controls the supply of the clock to the function A FF, and the multi-input gate 20b controls the supply of the clock to the function B FF.

Next, a method of designing the circuit shown in FIG. 1 will be described with reference to FIGS. 2, 3 and 4.

FIG. 3 shows a circuit diagram of the clock tree before the cell arranging step. Temporary buffer 1 (Before the tree structure, it is called "temporary")
Are connected to the input terminals of the provisional gate 2a and the provisional gate 2b. The output terminal of the temporary buffer 2a is connected to the FF 30a included in the function A circuit.
The output terminal b is connected to the clock input terminal of the FF 30b included in the function B circuit. Input terminals of the temporary gate 2a and the temporary gate 2b that are not connected to the clock line are connected to the selector circuit 21.

A list A, which is a list of all the FFs connected to the clock tree, is created from a net list (list of connection information) including this circuit (step 101). The members of the list A are FF names and input terminal capacitance of each FF.

Next, floor planning of the chip is performed (step 102). Each cell is grouped for each function, and a range in which cells of each function can be arranged is specified. Referring to FIG. 4A, for example, an area 201 </ b> A where a cell of function A is arranged on the LSI chip 200 is specified. Similarly, an area for arranging cells of other functions is specified.

Then, the cells are automatically arranged (by computer software) (step 103). FIG.
Referring to (a), for example, the FF 30a included in the circuit of the function A is arranged in the area 201A specified by the floor plan. Since cells of each function are arranged collectively, wiring between cells in each function is generally short.

From the list A created in step 101,
The number of stages of buffers to be inserted, the number of buffers in each stage, and the number of multi-input gates are determined (for example, each number is sorted by comparing with data in a database and input as information in a computer) (steps 104 and 105). The number of lower-layer buffers or NORs is an integer multiple of the number of upper-layer buffers. For example, there are four first stage buffers, 16 second stage buffers, and 64 final stage multi-input gates. After the number of stages and the number of each stage are determined, the load capacitance driven by the buffer and the multi-input gate of each stage is calculated.

Subsequently, FF clustering (cluster)
ering: grouping) (steps 106 and 1)
07). Referring to FIG. 3, for example, all the FFs 30a included in the function A circuit are connected to the multi-input gate 2a. Similarly, all the FFs 30b included in the function B circuit are connected to the multi-input gate 2b. So list A
Is divided into an FF connected to the multi-input gate 2a and an FF connected to the multi-input gate 2b.
Is created (step 106). The members of the list B are a function name, an FF name in each function, an input terminal capacity of each FF, and arrangement coordinates.

For each FF of each cluster (group) in the list B, clustering is performed between FFs whose arrangement positions are in the vicinity,
A list C is created (step 107). Clustering is performed such that the total of the input terminal capacitances of the FFs of each cluster is equal to the load capacitance driven by the multi-input gate. The members of list C are cluster names, function names, and FFs in each cluster.
The name, the sum of the input terminal capacitances of the FFs in each cluster, and the barycenter coordinates of the cluster.

Referring to FIG. 4B, for example, the function A
The FFs included in the circuit are clustered between FFs whose arrangement positions are close to each other to create a cluster 3a. List C
Is a list of FFs driven by each multi-input gate in the last stage, and each cluster name is the name of each multi-input gate to be inserted.

Further, in the clusters in the list C, clusters whose arrangement positions are close to each other are combined to form a new cluster, and a list D is created (steps 108 and 109). The number of clusters in list D is the same as the number of buffers in the preceding stage, and each cluster performs clustering so that the load capacity becomes uniform. The members of the list D are the cluster name, the cluster name of the list C in each cluster, the sum of the input terminal capacitances of the FFs in each cluster, and the coordinates of the center of gravity of the cluster. The name of the buffer to be inserted is the cluster name in list D.

If there are a plurality of buffers to be inserted, steps 108 to 109 are repeated.

Based on the lists created in steps 101 to 109, a netlist in which buffers and NORs are inserted is created (step 110).

Next, multiple input gates and buffers are arranged (steps 111 to 114, 121 to 123). From the last stage to the previous stage, arrangement is performed for each stage. The arrangement position is the center of gravity of the cell group driven by the buffer or the multi-input gate.

If cells are overlapped due to the insertion of a buffer or a multi-input gate, the overlaps are loosened and rearrangement is performed so as to minimize cell movement (steps 121 to 123).

After the process of arranging all buffers and multiple input gates is completed, wiring of the buffer output terminal and the input terminal of the next buffer or multiple input gate is performed (step 115). Wiring is performed so that the wiring length from the output terminal to each input terminal is uniform.

After the end of step 115, wiring of all cells is performed (step 116).

[0040]

The effect of the present invention is that the skew of the gated clock circuit can be eliminated and the delay from the route buffer to the FF can be reduced. As a result,
This has an effect that a low-power semiconductor integrated circuit with less possibility of malfunction can be obtained.

The reason is that a circuit free from timing violation due to clock skew can be obtained. Further, 70% or more of the power is consumed by the FF due to the clock signal, and the power consumption is reduced only by controlling the supply of the clock to the FF (by not supplying the clock to the FF that does not need to operate). This is because it can be suppressed.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention.

FIG. 2 is a flowchart showing a design method of the present invention.

FIG. 3 is a circuit diagram of an embodiment before a clock tree net generation step of the present invention.

FIG. 4 is a plan view of one embodiment in a clustering step of the present invention.

FIG. 5 is a conceptual diagram showing a configuration of a conventional technique.

FIG. 6 is a waveform chart for explaining the operation of the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Temporary buffer 2a-2b Temporary gate 3a-3b Cluster 11 Root buffer 12 First stage buffer 13 Second stage buffer 20a-20b Multi-input gate 21 Selector circuit 22a-22b Clock enable line 30a-30b Flip-flop 200 LSI chip 201A- 201B Area specified in floor plan

Claims (2)

(57) [Claims] And 1. A root buffer, the design method of the buffer of the plurality of stages are branched in order from the root buffer, a semiconductor integrated circuit having a gated clock circuit having a clock tree consisting of the final-stage multi-input gate In the above, after arranging the buffer of the gated clock circuit and the cell other than the multi-input gate, the provisional buffer, the provisional gate, and the provisional clock tree including the flip-flops included in the circuits of the respective functions connected to the provisional gate, the gated clock is used. the step of generating a dedicated net list of the circuit
In the net list generating step, a step of determining the number and the number of buffers to be inserted and the number of final stage multiple input gates from the temporary net list of the temporary clock tree; and a circuit of each function from the temporary net list. The file included in
A function clustering step of performing clustering for each flip-flop; and arranging cells other than the buffer and the multi-input gate of the gated clock circuit after floorplanning, and the flip-flop having an arrangement position in the vicinity of a cluster generated in the function clustering step. Clustering between clusters and determining the flip-flop driven by the final-stage multi-input gate; and further clustering the clusters created in the position clustering step between clusters whose arrangements are close to each other. A method for designing a semiconductor integrated circuit, comprising: a step of determining a circuit to be driven; and a step of similarly determining a circuit to be driven by each of the buffers up to the root buffer. 2. The arrangement of the buffer and the multi-input gate of the gated clock circuit is determined in accordance with the barycentric coordinates of each of the multi-input gates or the circuits driven by each of the buffers in order from the last stage to the root buffer for each stage. 2. The method for designing a semiconductor integrated circuit according to claim 1, wherein said method is arranged.