JP2000172367A - Clock signal distribution method and clock distribution circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To minimize the clock skew of a semiconductor device by dividing the terminal cells into plural groups and deciding the number and positions of cells which are connected to a relay buffer of every class so as to secure the even delay in a range covering the root buffer through every terminal cell. SOLUTION: The types of cells of relay buffers 101-104 are defined together with the number of cells of an entire chip. Then a clock trunk line 105 of a higher order level and then the buffers 101-104 are laid out together with the terminal cells 108. At the same time, a two-dimensional chip area is vertically and horizontally divided down to areas equal to the number of buffers 101-104. Then the buffers 101-109 are allocated and laid out. The delay of the part of the line 105 is calculated and then the delay is calculated in a range covering the outside of the chip through each of buffers 101-104. This delay is equalized by changing the connection of cells 108 serving as the loads among those buffers.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock signal distribution method and a clock signal distribution circuit in a layout of a semiconductor integrated circuit by processing using a computer.

[Prior art]

In a digital logic integrated circuit, a sequential circuit represented by a flip-flop is almost always used, and the whole circuit operates while synchronizing with a plurality of clock signals having different phases and periods. It has become. The clock signal is generated inside the chip or supplied from the outside. However, the clock signal is usually supplied through several buffers, and between the buffers and between the buffer and the flip-flop, generally, the CAD technology is used. Automatically connected.

The propagation delay time (hereinafter referred to as delay) of a clock signal supplied to a terminal cell such as a flip-flop.
Generally differs for each flip-flop, and the phase difference is called clock skew (hereinafter abbreviated as skew). If the skew is too large, the circuit cannot operate synchronously at the desired clock frequency. Therefore, it is important to determine the buffer position and the wiring path so that the clock signal arrives at the same timing as possible for all flip-flops on the chip.

The delay up to the flip-flop includes an internal delay of a buffer to be relayed, and a delay required for the buffer to charge / discharge the wiring capacitance / wiring resistance of the wiring for connection and the input terminal capacitance of the driven cell. .

On the other hand, the main methods for reducing the skew include a mesh method and a tree method. In the tree system, buffers connected in parallel at each stage are configured in a multistage configuration, and a tree-shaped wiring path is formed for each buffer. For example, JP-A-5-54100
And Japanese Patent Application Laid-Open No. 9-269847 disclose a method of distributing a clock signal composed of wiring paths using a tree method.

In this method, the skew between buffers in the same stage can be reduced. However, in general, in this method, if the number of stages in the buffer tree is too large, the delay increases even if the skew can be reduced, and the delay prediction is difficult without detailed layout processing. is there. In addition to this problem, for example, in Japanese Patent Application Laid-Open No. 5-54100, a multi-stage buffer tree is formed by buffers. In this case, there is an influence due to the variation in the manufacturing stage for each stage of the tree.
In general, the magnitude of the influence of the variation as a whole circuit is proportional to the number of tree stages.
When the number of stages of the buffer tree is large as in the clock distribution circuit disclosed in the above-mentioned publication, there is a problem that it is susceptible to variations in gate and wiring processes during LSI manufacturing.

In Japanese Patent Application Laid-Open No. 9-269847, among the buffers constituting the tree, the characteristics and the numbers of the buffers of the same hierarchy are made equal, so that the variation in the gate and wiring during the LSI manufacturing in the whole circuit is reduced. A tree-based clock signal distribution method that minimizes the effect is disclosed. The variation in the gate and wiring process is caused by the insertion of multi-stage gates up to the flip-flop as the terminal cell and the width of the wiring. In this case, since a redundant element and a wiring connected to the redundant element are required, an increase in power consumption and an increase in the amount of wiring become problems.

On the other hand, with respect to the tree method described above,
In the mesh method, a wiring path is laid around a chip in a lattice, a buffer is connected to the lattice path, and a buffer is connected to a flip-flop as an end cell via the buffer. Advantages of this method include that the configuration is simple, the equivalent resistance of the wiring is small and the delay is small because the wiring path is annular, and the delay can be predicted before the layout processing. However, when the circuit becomes very large-scale, there is a problem that the skew between the flip-flop near the root buffer and the flip-flop far from the root buffer cannot be ignored, and the wiring length increases due to the necessity of making the grid finer.

[0009] Both the mesh method and the tree method have advantages and disadvantages.
It can be said that a mesh system which has a simple configuration, has small manufacturing variations of the buffer, and has a small delay is desirable.

FIGS. 2 and 6 show an example of a conventional mesh-type clock signal distribution circuit. FIG. 2 shows the entire structure of a conventional mesh-type clock signal distribution circuit, which is configured using a wide mesh wiring at an upper level (clock main line). FIG. 6 shows a lower level (a plurality of clusters 301 to 3 including the relay buffers 101 to 104).
04) relay buffer 101 from mesh wiring
To 104 and the structure of a plurality of trees formed with the relay buffers 101 to 104 as roots. FIG.
In the clock signal distribution circuit shown in FIG. 6, the mesh wiring is divided into two levels, an upper level and a lower level, and the mesh wiring is fixedly arranged with a large width as the upper level, and a root buffer 106 is provided. As a result, the clock main lines 105
A clock is supplied to the entire surface of the chip via a, 105b and 105c. At the same time, as the lower level, the relay buffers 101 to 104, 101a to 104a, and 101b are connected to the respective clock trunk lines 105, 105a, 105b, and 105c.
To 104b and 101c to 104c. FIG. 6 is an enlarged view of the portion of the clock main line 105 shown in FIG. As shown in FIG. 6, a plurality of clusters 301 composed of a plurality of terminal cells 108 with the relay buffer 105 as a root.
To 304 are formed. Here, a flip-flop is used for the terminal cell. In this case, the other clock trunk 105
Also in a, 105b, and 105c, a plurality of clusters are formed similarly to the clock trunk 105 shown in FIG.
The plurality of clusters 301 to 304 are formed by connecting a plurality of end cells in a tree shape with the relay buffers 101 to 104 as roots.

Another example of a conventional mesh-type clock signal distribution circuit and clock signal distribution method is disclosed in Japanese Patent Application Laid-Open No. Hei 4-217345. This clock signal distribution circuit adjusts the delay at each stage of the buffer tree by equally dividing the area when the density of the end cells varies.

[0012]

However, the conventional clock signal distribution circuits and distribution methods shown in FIGS. 2 and 6 have the following problems. In the conventional clock signal distribution circuits shown in FIG. 2 and FIG. 6, the occurrence of electromigration is avoided by arranging the mesh-like wiring, which is the upper level, with a thick clock trunk line. However, in recent years, there has been an increasing demand for high-speed LSI. As described above, simply increasing the width of the upper-level mesh wiring sufficiently reduces the difference in wiring delay due to the difference in distance from the root buffer 106. Therefore, it is becoming impossible to reduce the skew of the clock trunk line, which is the upper level.

Further, in the conventional clock signal distribution circuits shown in FIGS. 2 and 6, since the distance from the root buffer 106 to the relay buffers 101 to 104 differs for each relay buffer, the skew from the upper level also differs. . In order to eliminate the skew of each upper level as described above for each relay buffer, the lower level cluster 3
A redundant wiring 207 corresponding to the distance from the root buffer 106 is provided in the relay buffers 101 to 104 of the clusters 01 to 304, and the dummy load elements 20 are provided in the clusters 301 to 304.
8 is additionally provided. However, the provision of the relay buffers 101 to 104 and the dummy load element 208 causes a problem of an increase in chip size due to deterioration of accommodability due to an increase in wiring length and an increase in power consumption due to an increase in load capacity. .

The conventional clock signal distribution circuit and distribution method disclosed in Japanese Patent Application Laid-Open No. 4-217345 also aims at adjusting the delay for each stage of the buffer tree. It is necessary to attach a load, and there is a problem that power consumption increases. Further, when the wirings of the flip-flops are sparse and dense, a method of equally dividing the area where the buffer is arranged is used, so that it is difficult to match the delays of the flip-flops. The problem of increase had arisen.

The present invention has been made in view of the above-mentioned problems in the prior art. An object of the present invention is to provide a clock signal distribution method and a clock distribution circuit capable of minimizing clock skew in a semiconductor device.

[0016]

A first invention of the present application, which is provided to solve the above-mentioned problems, is provided on a semiconductor substrate, from a root buffer connected to a clock trunk composed of a plurality of clock trunks to a relay buffer. When supplying a clock signal to a plurality of terminal cells via the, generating a cluster including at least one or more terminal cells, dividing the terminal cells into a plurality of groups, the plurality of terminal cells in the cluster After arranging the relay buffer at substantially the center position, considering the skew from the outside of the semiconductor substrate to each relay buffer, determining the position of the relay buffer in each cluster and the configuration and position of the terminal cell, Is determined as a root node, and a wiring path of the entire mesh wiring including a tree-shaped wiring path having the terminal cell as a leaf node is determined. It is a method of distributing clock signals, characterized.

Considering the skew from the outside of the semiconductor substrate to each relay buffer in the present application means, first of all, that the relay cell in each cluster depends on the skew from the outside of the semiconductor substrate to each relay buffer. And dynamically changing the arrangement and number of terminal cells. According to the first clock signal distribution method of the present application having the above configuration, the position of the relay buffer in each cluster and the configuration and position of the terminal cell are determined in consideration of the skew from the outside of the semiconductor substrate to each relay buffer. After that, by determining the wiring path of the entire mesh wiring including the tree-shaped wiring path with the relay buffer as the root node and the terminal cell as the leaf node, the skew from the outside of the semiconductor substrate to each relay buffer is determined. By dynamically changing the arrangement of relay cells and the arrangement and number of end cells in each cluster, it is possible to equalize the delay of each cluster, thereby minimizing the skew of the entire circuit. it can. Further, since it is not necessary to install redundant wirings and dummy load elements in the cluster as in the related art, it is possible to improve the accommodability and reduce the power consumption by reducing the wiring length.

Further, the second invention of the present application provides a clock signal from a root buffer connected to a mesh wiring composed of a plurality of clock trunks to a plurality of terminal cells via a relay buffer. When supplying, a cluster including at least one or more terminal cells is generated, the terminal cells are divided into a plurality of groups, and a relay buffer is arranged at a substantially central position of the terminal cells in the cluster. Calculate the delay from the outside of the board to each relay buffer and the delay from the relay driver to each terminal cell, obtain the sum of these delays for each cluster, and calculate the sum of these delays in each cluster so that the delays of each cluster are equalized. After determining the position of the relay buffer and the configuration and position of the terminal cell, the relay buffer is used as a root node and the terminal cell is used as a leaf node. It is a method of distributing clock signals and determines the routing of the whole mesh-shaped wire including a tree-like wiring route to.

According to the second clock signal distribution method of the present application having the above configuration, the position of the relay buffer and the number and position of the terminal cells in each cluster are adjusted so that the sum of the delays of each cluster is equalized. After deciding,
By determining the wiring path of the entire mesh wiring including the tree-shaped wiring path with the relay buffer as the root node and the terminal cell as the leaf node, the skew of the entire circuit can be minimized. further,
Since there is no need to install redundant wirings or dummy load elements in the cluster as in the related art, it is possible to improve the storability by reducing the wiring length and reduce the power consumption.

The clock signal distribution method according to the third invention of the present application is the clock signal distribution method according to the first or second application of the present application, wherein the delay and relay from the outside of the semiconductor substrate to each relay buffer are performed. The delay of each cluster is equalized by switching the terminal cell from the cluster having the largest total delay from the driver to each terminal cell to the cluster having the minimum total delay.

According to the third clock signal distribution method of the present application having the above configuration, the cluster having the largest total sum of the delay from the outside of the semiconductor substrate to each relay buffer and the delay from the relay driver to each terminal cell is determined from the cluster The skew is reduced by connecting the end cells to the cluster having the minimum sum to equalize the delay of each cluster, thereby minimizing the skew in the entire circuit. Furthermore, since there is no need to install redundant wiring and dummy load elements in the cluster as in the past,
It is possible to improve the accommodating property and reduce the power consumption by reducing the wiring length.

The clock signal distribution method according to the fourth invention of the present application is the clock signal distribution method according to any one of the first to third applications of the present application, wherein the position of the relay buffer in each cluster and After determining the configuration and position of the terminal cell,
After the wiring in each cluster is performed, the entire wiring path in the remaining mesh wiring is determined.

According to the fourth clock signal distribution method of the present application having the above configuration, the position of the relay buffer in each cluster and the configuration and position of the terminal cell are determined, and then wiring in each cluster is performed. By determining the entire wiring path in the remaining mesh wiring, redundant shunt wiring is eliminated, so that skew can be reduced.

According to a fifth aspect of the present invention, there is provided a root buffer disposed on a semiconductor substrate, and a mesh-like wiring comprising a plurality of clock trunk lines connected to the root buffer and receiving clocks of the same phase from the root buffer. Wherein the clock trunk has a plurality of clusters each having a plurality of terminal cells connected in a tree via one relay buffer;
According to a higher level skew from the outside of the semiconductor substrate to each relay buffer, the position of the relay buffer in each cluster and the number and position of the terminal cells are determined to form each cluster. It is a clock distribution circuit.

According to the fifth clock signal distribution circuit of the present application having the above configuration, each of the clock trunk lines is
It has a plurality of clusters having a plurality of end cells connected in a tree via one relay buffer, and has a plurality of clusters in each cluster according to a higher level skew from the outside of the semiconductor substrate to each relay buffer. Since the positions of the relay buffer and the number and positions of the terminal cells are determined and each cluster is formed, the delay of each cluster can be equalized, so that the skew of the entire circuit can be minimized. Can be planned. Further, since it is not necessary to install redundant wirings and dummy load elements in the cluster as in the related art, it is possible to improve the accommodability and reduce the power consumption by reducing the wiring length.

According to a sixth aspect of the present invention, there is provided a base buffer arranged on a semiconductor substrate, and a mesh-like wiring comprising a plurality of clock trunks connected to the base buffer and receiving clocks of the same phase from the base buffer. Wherein the clock trunk has a plurality of clusters each having a plurality of terminal cells connected in a tree via one relay buffer;
A clock distribution circuit characterized in that the position of the relay buffer in each cluster and the number and position of the terminal cells are determined and each cluster is formed so that the delay of each cluster is equalized. .

According to the sixth clock signal distribution circuit of the present application having the above configuration, each of the clock trunk lines is
It has a plurality of clusters having a plurality of terminal cells connected in a tree via one relay buffer, and the position of the relay buffer in each cluster is adjusted so that the delay of each cluster is equalized. Since the number and position of the end cells are determined to form each cluster, the delay of each cluster can be equalized, so that the skew of the entire circuit can be minimized.
Further, since it is not necessary to install redundant wirings and dummy load elements in the cluster as in the related art, it is possible to improve the accommodability and reduce the power consumption by reducing the wiring length.

[0028]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. The following embodiments are examples showing a clock signal distribution method and a clock signal distribution circuit according to the present invention. It's just (First Embodiment) FIG. 1 is an enlarged view of a clock trunk 105 in a clock signal distribution circuit according to an embodiment of the present invention. FIG. 2 is a diagram showing a clock signal distribution circuit according to the embodiment of the present invention. FIG. 3 is a flowchart showing a procedure of the clock signal distribution method according to the embodiment of the present invention. FIG. 4 is a diagram illustrating a clock signal distribution method according to the embodiment of the present invention.

In the clock signal distribution circuit according to the present embodiment, as shown in FIGS. 1 and 2, the entire circuit is divided into two levels, an upper level and a lower level, and the upper level is shown in FIG. Wide clock main lines 105 and 10
Each of the relay buffers 101-104, 101a-104a, 101b- shown in FIG.
Plurality of clusters 4 including 104b, 101c to 104c
01 to 404 are provided. As shown in FIG. 2, the mesh-like wiring is replaced with the thick clock trunk 105, 105a, 105b.
By providing the base buffer 106 fixedly at 105c, a clock is supplied from the base buffer 106 to the entire chip via each clock trunk 105, 105a, 105b, 105c, and at the same time, each clock trunk is set as a lower level. 105 ・ 105a ・ 105b ・ 105
c, relay buffers 101-104, 101a-104
a, 101b to 104b and 101c to 104c are provided.

FIG. 1 shows a mesh trunk 10 shown in FIG.
It is an enlarged view of 5 parts, and relay buffers 101-104,
2 shows the structure of tree-like clusters 401 to 404 formed using the relay buffers 101 to 104 as roots. In this case, a plurality of clusters are formed also in the other clock trunks 105a, 105b, and 105c shown in FIG. 2, similarly to the clock trunk 105 shown in FIG. The clusters 401 to 404 are formed by connecting the terminal cells 108 in a tree shape with the relay buffers 101 to 104 as roots. The end cell 108 is an element for inputting a clock signal, and in this embodiment, a flip-flop is used. As shown in FIG. 1, each of the relay buffers 101 to 104 is arranged according to the skew of the clock trunk 105 at the higher level, and at the same time, the terminal cell 108 in each of the clusters 401 to 404 also has the clock trunk at the higher level. 105 and the relay buffers 101 to 104 are arranged and formed according to the skew. For example, the number of terminal cells 108 in the cluster is set to be larger in the cluster 401 having a small delay in the upper level than in the cluster 404 having a large delay in the upper level. Since the wiring delay of the level increases and cancels out the small delay occurring at the upper level of the cluster 401 and the delay of each cluster in the mesh trunk 105 can be equalized, the skew of the entire circuit can be reduced. it can.

Next, a clock signal distribution method according to the present embodiment will be described with reference to the clock distribution circuit shown in FIGS. 1 and 2 and the flowchart shown in FIG. Here, the clusters 401 to 404 connected to the clock trunk 105 shown in FIG. 1 will be described as an example. The clock signal distribution method according to the present embodiment can be executed by using necessary input / output devices on a digital computer.

First, parameters of the entire circuit are defined (step 31). The types of cells of the relay buffers 101 to 104 and the number of the cells in the entire chip are defined. The types and number of cells of the relay buffers 101 to 104 are not limited to the numbers shown here, and may be specified by a designer through input through an input device, or may be specified by a chip size and a flip-flop which is a terminal cell. A function possessed in the form of library information may be used as a function of the number. Next, the clock main line 105 at the upper level is arranged (step 32). The clock main line 105 receives a signal separately laid out for each chip size. The layout method and shape of the clock trunk line are arbitrary. Also,
Since the connection with the terminal cell is made at the lower level, the clock trunk 105 is connected to the relay buffers 101 to 10 which are circuit elements.
4 and independent. Next, the relay buffers 101 to
The arrangement of 104 is performed. Here, a “placement program” used in a normal LSI design can be used.
An end cell 108 which is a device for inputting a clock signal is also arranged at the same time. There is no particular restriction on the position where the relay buffers 101 to 104 and the terminal cell 108 are arranged (step 33). Next, an initial cluster of the terminal cell 108 is created (step 34). Since the delay is optimized in a later step, it is sufficient here to balance the load capacity and to ensure that the end cells located close to each other are in the same cluster. 2
While dividing the dimensional chip area vertically / horizontally, it is finally divided up to the number of relay drivers defined in step 31.

Next, the subsequent steps (steps 36 to 39) for improving the cluster configuration in consideration of the skew are repeated (step 35) until the skew improvement reaches the target value. The “target value” here is set as a desired skew value inputted from outside through an input device. Even if the target value is not reached, if the skew is not improved when the subsequent step is performed once, the process proceeds to step 311 and subsequent steps.

In step 36, the relay drivers 101 to 104 defined in step 31 are allocated and arranged for each cluster. The relay drivers 101 to 104 are respectively arranged at the center positions of the clusters 401 to 404 or on the clock trunk 105 closest thereto. In the present embodiment, the relay driver 10
In the case where 1 to 104 are arranged, the wiring connecting the clock main line 105 and the relay drivers 101 to 104 can be made short, so that the connection portion does not need to be considered much when calculating the delay in the next step 37.

Next, the delay of the clock trunk 105 (upper level) is calculated, and the delay from the outside of the chip to each of the relay drivers 101 to 104 is calculated (step 3).
7). Here, a “circuit simulator” used in normal LSI design can be used based on the RC (resistance / capacitance) net of the clock trunk 105. Note that the input gate capacitance of the relay drivers 101 to 104 is
In step 37, the relay drivers 101 to 104 are (re)
You need to do this every time you place it.

Next, a delay calculation (lower level) from the relay drivers 101 to 104 to each terminal cell 108 is performed (step 38). The actual wiring is performed in a later process (step 3
Since it is performed in 11), wiring is performed here as an estimate. There is a method of estimating the load capacity by a statistical method and calculating a delay based on the estimated capacity, or a method of performing temporary wiring. In response to the results of steps 37 and 38, in step 39, the delay is equalized by changing the end cell 108, which is the load, between the buffers. Maximum delay
The end cell 108 is reconnected from the cluster having (delay at the upper level + delay at the lower level) to the cluster having the minimum delay (step 39). For example,
If the two clusters, the cluster having the largest delay and the cluster having the smallest delay, are adjacent to each other, the terminal cells are reconnected directly. Reconnect the end cell. FIG. 4 shows an example of the reconnection of the terminal cells described above.
As shown in FIG. 4, the cluster 404 with the largest delay
From the end cell to the cluster 401 with the least delay,
03. The reconnection of the terminal cells is not limited to the method described above. After the cluster improvement described above is completed (step 310), wiring of the entire net including the lower level is performed (step 311). Here, "wiring program" used in normal LSI design
Can be used. According to the above steps, in the clock signal distribution method according to the present embodiment, in a cluster having a small delay at an upper level, the number of terminal cells in the cluster is increased at a lower level, and the gate delay of the relay driver and the relay driver are reduced. On the other hand, while increasing the following wiring delay, in a cluster having a large delay at the upper level, by reducing the number of terminal cells in the cluster at the lower level, the gate delay of the relay driver and the wiring delay below the relay driver are reduced. Since the delay of each cluster can be equalized, the skew can be reduced by canceling out the small delay at the higher level. Further, since it is not necessary to install redundant wirings and dummy load elements in the cluster as in the related art, it is possible to improve the accommodability and reduce the power consumption by reducing the wiring length.

(Second Embodiment) Next, a clock signal distribution method according to another embodiment of the present invention will be described with reference to FIG. FIG. 5 is a flowchart showing a procedure of the clock signal distribution method according to the embodiment of the present invention. Steps 41 to 47 and steps 49 and 410 in FIG. 5 correspond to steps 31 to 47 in FIG. 3 showing the clock signal distribution method according to the first embodiment of the present invention.
37 and steps 39 and 310, and a description thereof will be omitted.

The configuration of the clock signal distribution circuit according to the present embodiment is the same as the configuration of the clock signal distribution circuit according to the first embodiment of the present invention shown in FIGS. Therefore, description will be made with reference to FIGS.

In the method of distributing clock signals according to the present embodiment, in step 411, a lower-level clock net is preferentially wired prior to the wiring of another level portion.
As described above, the lower-level clock net is preferentially wired prior to the wiring of the other level parts, so that a redundant bypass wiring is not formed, so that skew can be reduced.

A "zero skew wiring" in which a binary tree-shaped wiring is formed bottom-up simultaneously with the above-described priority wiring.
It is also possible to use techniques. In this case, the delay calculation in step 48 also needs to calculate the delay after estimating the wiring by the same method. Further, the skew remaining as a result of the improvement after step 45 can be absorbed by using redundant wiring.

[0041]

As described above, according to the clock signal distribution method according to the present invention, a signal is transmitted from a root buffer disposed on a semiconductor substrate and connected to a mesh-like wiring composed of a plurality of clock trunk lines via a relay buffer. When supplying a clock signal to a plurality of end cells, a cluster including at least one end cell is generated, the end cells are divided into a plurality of groups, and the center of the plurality of end cells in the cluster is substantially centered. After arranging the relay buffer at the position, considering the skew from the outside of the semiconductor substrate to each relay buffer, determining the position of the relay buffer in each cluster and the configuration and position of the terminal cell, and then routing the relay buffer By determining a wiring path of the entire mesh wiring including a tree-shaped wiring path having a node as a node and the terminal cell as a leaf node. The delay of each cluster can be equalized by dynamically changing the arrangement of relay cells and the arrangement and number of end cells in each cluster according to the skew from the outside of the semiconductor substrate to each relay buffer. The skew of the entire circuit can be minimized. Further, since it is not necessary to install redundant wirings and dummy load elements in the cluster as in the related art, it is possible to improve the accommodability and reduce the power consumption by reducing the wiring length.

According to the clock signal distribution circuit of the present invention, each of the clock trunk lines has a plurality of clusters each having a plurality of terminal cells connected in a tree via one relay buffer. Then, according to the high-level skew from the outside of the semiconductor substrate to each relay buffer,
Since each cluster is formed by determining the position of the relay buffer in each cluster and the number and position of the terminal cells, the delay of each cluster can be equalized. Minimization can be achieved. Further, since it is not necessary to install redundant wirings and dummy load elements in the cluster as in the related art, it is possible to improve the accommodability and reduce the power consumption by reducing the wiring length.

[Brief description of the drawings]

FIG. 1 is an enlarged view of a clock main line portion in a clock signal distribution circuit according to a first embodiment of the present invention.

FIG. 2 is a diagram illustrating a clock signal distribution circuit according to the related art and the first and second embodiments of the present invention.

FIG. 3 is a flowchart showing a procedure of a clock signal distribution method according to the first embodiment of the present invention.

FIG. 4 is a diagram illustrating a clock signal distribution method according to the first embodiment of the present invention.

FIG. 5 is a flowchart illustrating a procedure of a clock signal distribution method according to a second embodiment of the present invention.

FIG. 6 is an enlarged view of a clock main line in a conventional clock signal distribution circuit.

[Explanation of symbols]

101-104 / 101a-104a / 101b-10
4b, 101c to 104c Relay buffer 105, 105a, 105b, 105c Clock trunk line 106 Root buffer 108 End cell 207 Redundant wiring 208 Dummy load element 301 to 304, 401 to 404 Cluster 309 LSI chip

────────────────────────────────────────────────── ───

[Procedure amendment]

[Submission date] October 4, 1999 (1999.10.
4)

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

[Procedure amendment 2]

[Document name to be amended] Statement

[Correction target item name] 0016

[Correction method] Change

[Correction contents]

[0016]

The first invention of the present application, which is provided to solve the above-mentioned problems, is provided on a semiconductor substrate and from a plurality of clock trunk lines connected to a root buffer via a relay buffer. In the clock signal distribution method for supplying a clock signal to a plurality of end cells, a cluster including at least one end cell is generated, the end cells are divided into a plurality of groups, and a delay from a root buffer to each end cell is equal. A clock signal distribution method characterized in that the number and the position of each terminal cell connected to the relay buffer in each cluster are determined in such a manner as to make a clock signal.

[Procedure amendment 3]

[Document name to be amended] Statement

[Correction target item name] 0017

[Correction method] Change

[Correction contents]

[0017] According to the distribution method of the present application first clock signal having the above structure, the terminal cells to generate a cluster including at least one or more dividing the end cell into a plurality of groups, from the root buffer to each end cell By determining the number and position of each terminal cell connected to the relay buffer in each cluster so as to equalize the delay, it is possible to minimize the skew of the entire circuit. Further, since it is not necessary to install redundant wirings and dummy load elements in the cluster as in the related art, it is possible to improve the accommodability and reduce the power consumption by reducing the wiring length.

[Procedure amendment 4]

[Document name to be amended] Statement

[Correction target item name] 0018

[Correction method] Change

[Correction contents]

Further , the second invention of the present application provides a cluster in which the total sum of the delay from the root buffer to each relay buffer and the delay from the relay driver to each terminal cell is maximum.
The terminal cell is switched to a cluster having the minimum sum of delays, thereby equalizing the delay from the root buffer to each terminal cell.

[Procedure amendment 5]

[Document name to be amended] Statement

[Correction target item name] 0019

[Correction method] Change

[Correction contents]

[0019] According to the distribution method of the present application a second clock signal having the above structure, a cluster sum of delay to each end cell is the maximum delay and the relay buffer from the root buffer to each relay buffer, the delayed The skew is reduced by connecting the end cells to the cluster having the smallest sum of the skews by equalizing the delay from the root buffer to each end cell, thereby minimizing the skew in the entire circuit. it can. Further, since it is not necessary to install redundant wirings and dummy load elements in the cluster as in the related art, it is possible to improve the accommodability and reduce the power consumption by reducing the wiring length.

[Procedure amendment 6]

[Document name to be amended] Statement

[Correction target item name] 0020

[Correction method] Change

[Correction contents]

In the clock signal distribution method according to the third invention of the present application, the position of the relay buffer and the number and position of the terminal cells in each cluster are determined, and then the wiring in each cluster is performed. It is characterized in that the remaining wiring paths are determined.

[Procedure amendment 7]

[Document name to be amended] Statement

[Correction target item name] 0021

[Correction method] Change

[Correction contents]

[0021] According to the distribution method of the present application the third clock signal having the above structure, after the determine the number and position of the position and the end cell of the relay buffer in each cluster were wires in each cluster By determining the remaining wiring paths, redundant shunt wiring is eliminated, and skew can be reduced.

[Procedure amendment 8]

[Document name to be amended] Statement

[Correction target item name] 0022

[Correction method] Change

[Correction contents]

Further , the clock signal distribution method according to the fourth invention of the present application is characterized in that the clock main line is wired in a mesh shape.

[Procedure amendment 9]

[Document name to be amended] Statement

[Correction target item name] 0023

[Correction method] Change

[Correction contents]

[0023] According to the distribution method of the present application the fourth clock signal having the above structure, since the said clock trunk line are wired like a mesh, structure is simple, wiring path is small equivalent resistance of the wiring for the ring Low delay. Further, the delay can be predicted before the layout processing. Further, there is an advantage that variation in manufacturing the buffer is small.

[Procedure amendment 10]

[Document name to be amended] Statement

[Correction target item name] 0024

[Correction method] Change

[Correction contents]

Further, this application fifth invention, a root buffer disposed on a semiconductor substrate, a clock distributing circuit comprising a plurality of clock trunk line which is connected to the base buffer receiving a clock supply of the same phase from said root buffer , Each of the clock trunks has a plurality of clusters each having a plurality of terminal cells connected in a tree via one relay buffer so that the delay from the root buffer to each terminal cell is equalized. The number and position of each terminal cell connected to the relay buffer in each cluster are determined.

[Procedure amendment 11]

[Document name to be amended] Statement

[Correction target item name] 0025

[Correction method] Change

[Correction contents]

According to the fifth clock signal distribution circuit of the present invention having the above configuration, the terminal cells connected to the relay buffers in each cluster are equalized so that the delay from the root buffer to each terminal cell is equalized. By determining the number and the position, the delay from the root buffer to each terminal cell can be equalized, so that the skew of the entire circuit can be minimized. Further, since it is not necessary to install redundant wirings and dummy load elements in the cluster as in the related art, it is possible to improve the accommodability and reduce the power consumption by reducing the wiring length.

[Procedure amendment 12]

[Document name to be amended] Statement

[Correction target item name] 0026

[Correction method] Change

[Correction contents]

Further , the sixth invention of the present application is characterized in that the clock main line is wired in a mesh shape.

[Procedure amendment 13]

[Document name to be amended] Statement

[Correction target item name] 0027

[Correction method] Change

[Correction contents]

[0027] According to the distribution circuit of the present application sixth clock signals having the above structure, by the clock trunk line is routed in a mesh shape, structure is simple, wiring path equivalent resistance of the wiring for the ring Small and low delay. Further, the delay can be predicted before the layout processing. Further, there is an advantage that variation in manufacturing the buffer is small.

[Procedure amendment 14]

[Document name to be amended] Statement

[Correction target item name] 0032

[Correction method] Change

[Correction contents]

First, parameters of the entire circuit are defined (step 31). The types of cells of the relay buffers 101 to 104 and the number of the cells in the entire chip are defined. The types and number of cells of the relay buffers 101 to 104 are not limited to the numbers shown here, and may be specified by a designer through input through an input device, or may be specified by a chip size and a flip-flop which is a terminal cell. A function possessed in the form of library information may be used as a function of the number. Next, the clock main line 105 at the upper level is arranged (step 32). The clock main line 105 receives a signal separately laid out for each chip size. The layout method and shape of the clock trunk line are arbitrary. Also,
Since the connection with the terminal cell is made at the lower level, the clock trunk 105 is connected to the relay buffers 101 to 10 which are circuit elements.
4 and independent. Next, the relay buffers 101 to
The arrangement of 104 is performed. Here, a “placement program” used in a normal LSI design can be used.
An end cell 108 which is a device for inputting a clock signal is also arranged at the same time. There is no particular restriction on the position where the relay buffers 101 to 104 and the terminal cell 108 are arranged (step 33). Next, an initial cluster of the terminal cell 108 is created (step 34). Since the delay is optimized in a later step, it is sufficient here to balance the load capacity and to ensure that the end cells located close to each other are in the same cluster. 2
While dividing the dimensional chip area vertically and horizontally, the chip area is finally divided up to the number of relay buffers defined in step 31.

[Procedure amendment 15]

[Document name to be amended] Statement

[Correction target item name] 0033

[Correction method] Change

[Correction contents]

Next, the subsequent steps (steps 36 to 39) for improving the cluster configuration in consideration of the skew are repeated (step 35) until the skew improvement reaches the target value. The “target value” here is set as a desired skew value inputted from outside through an input device. Even if the target value is not reached, if the skew is not improved when the subsequent step is performed once, the process proceeds to step 311 and subsequent steps. Book
The scanning from the outside of the semiconductor substrate to each relay buffer
Considering the view is primarily due to the
Each click corresponds to the skew from the outside of the board to each relay buffer.
Arrangement of relay cells and arrangement and number of terminal cells in the raster
Means to dynamically change.

[Procedure amendment 16]

[Document name to be amended] Statement

[Correction target item name] 0034

[Correction method] Change

[Correction contents]

In step 36, the relay buffers 101 to 104 defined in step 31 are allocated and arranged in cluster units. The relay buffers 101 to 104 are respectively arranged at the center positions of the clusters 401 to 404 or on the clock trunk 105 closest thereto. In the present embodiment, the relay buffer 10
In the case where 1 to 104 are arranged, the wiring connecting the clock main line 105 and the relay buffers 101 to 104 can be made short, so that the connection portion does not need to be taken into account much when calculating the delay in the next step 37.

[Procedure amendment 17]

[Document name to be amended] Statement

[Correction target item name] 0035

[Correction method] Change

[Correction contents]

Next, delay calculation of the clock trunk 105 (upper level) is performed, and each relay buffer is externally provided from the chip.
To calculate the delay of up to file 101 to 104 (step 3
7). Here, a “circuit simulator” used in normal LSI design can be used based on the RC (resistance / capacitance) net of the clock trunk 105. The relay back
The input gate capacity of the fas 101 to 104 is the clock main line 1
In step 37, the relay buffers 101 to 104 are (re-)
You need to do this every time you place it.

[Procedure amendment 18]

[Document name to be amended] Statement

[Correction target item name] 0036

[Correction method] Change

[Correction contents]

Next, a delay calculation (lower level) from the relay buffers 101 to 104 to each terminal cell 108 is performed (step 38). The actual wiring is performed in a later process (step 3
Since it is performed in 11), wiring is performed here as an estimate. There is a method of estimating the load capacity by a statistical method and calculating a delay based on the estimated capacity, or a method of performing temporary wiring. In response to the results of steps 37 and 38, in step 39, the delay is equalized by changing the end cell 108, which is the load, between the buffers. Maximum delay
The end cell 108 is reconnected from the cluster having (delay at the upper level + delay at the lower level) to the cluster having the minimum delay (step 39). For example,
If the two clusters, the cluster having the largest delay and the cluster having the smallest delay, are adjacent to each other, the terminal cells are reconnected directly. Reconnect the end cell. FIG. 4 shows an example of the reconnection of the terminal cells described above.
As shown in FIG. 4, the cluster 404 with the largest delay
From the end cell to the cluster 401 with the least delay,
03. The reconnection of the terminal cells is not limited to the method described above. After the cluster improvement described above is completed (step 310), wiring of the entire net including the lower level is performed (step 311). Here, "wiring program" used in normal LSI design
Can be used. Through the above steps, in the method for distributing a clock signal in accordance with the present embodiment, the small clusters of high-level delay, gate delay and the relay buffer in the relay buffer by increasing the number of terminal cells in the cluster at a lower level While the following wiring delay increases, in a cluster with a large delay at the upper level, relaying by reducing the number of terminal cells in the cluster at the lower level
By less gate delay and relay buffer following wiring delay buffers, it is possible to equalize the delay each cluster has, it is possible to reduce the skew by offsetting a small delay of the higher level. Further, since it is not necessary to install redundant wirings and dummy load elements in the cluster as in the related art, it is possible to improve the accommodability and reduce the power consumption by reducing the wiring length.

[Procedure amendment 19]

[Document name to be amended] Drawing

[Correction target item name] Figure 2

[Correction method] Change

[Correction contents]

FIG. 2

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 5B079 BC03 CC02 CC04 CC08 CC14 DD08 DD12 DD13 5F064 DD04 DD14 EE12 EE47 EE54 HH06 HH10

Claims (6)

[Claims] When a clock signal is supplied from a root buffer connected to a mesh wiring composed of a plurality of clock trunk lines to a plurality of terminal cells via a relay buffer, the terminal cells are arranged on a semiconductor substrate. After generating a cluster including at least one or more cells, dividing the terminal cells into a plurality of groups, arranging a relay buffer at a substantially central position of the plurality of terminal cells in the cluster, After determining the position of the relay buffer and the configuration and position of the terminal cell in each cluster in consideration of the skew, a mesh including a tree-shaped wiring path having the relay buffer as a root node and the terminal cell as a leaf node A method for distributing a clock signal, comprising determining a wiring route of an entire wire. 2. The method according to claim 1, further comprising the steps of: supplying a clock signal from a root buffer connected to a mesh wiring composed of a plurality of clock trunk lines to a plurality of terminal cells via a relay buffer; After generating a cluster including at least one or more cells, dividing the terminal cells into a plurality of groups, arranging a relay buffer at a substantially central position of the plurality of terminal cells in the cluster, The delay and the delay from the relay driver to each terminal cell are calculated, the sum of these delays is obtained for each cluster, and the position of the relay buffer in each cluster and the position of the terminal cell are equalized so that the delay of each cluster is equalized. After determining the configuration and position, a tree-shaped wiring path with the relay buffer as a root node and the terminal cell as a leaf node Clock signal distribution method of which is characterized by determining the routing of the entire mesh-like wiring including. 3. The terminal cell is switched from a cluster having a maximum sum of delays from the outside of the semiconductor substrate to each relay buffer and a delay from the relay driver to each terminal cell to a cluster having the minimum total sum. 3. The clock signal distribution method according to claim 1, wherein a delay of each cluster is equalized. 4. After deciding the position of the relay buffer in each cluster and the configuration and position of the terminal cell, after arranging the wiring in each cluster, deciding the entire wiring route in the remaining mesh wiring. The clock signal distribution method according to any one of claims 1 to 3, wherein: 5. A clock distribution circuit comprising: a root buffer disposed on a semiconductor substrate; and a mesh-like wiring comprising a plurality of clock trunk lines connected to the root buffer and receiving clocks of the same phase from the root buffer. Wherein the clock trunk has a plurality of clusters each having a plurality of end cells connected in a tree via one relay buffer, and has a higher level skew from the outside of the semiconductor substrate to each relay buffer. A clock distribution circuit characterized in that the position of the relay buffer in each cluster and the number and position of the terminal cells are determined according to the above, so that each cluster is formed. 6. A clock distribution circuit, comprising: a root buffer disposed on a semiconductor substrate; and a mesh wiring comprising a plurality of clock trunk lines connected to the root buffer and receiving clocks of the same phase from the root buffer. In the above, the clock trunk has a plurality of clusters each having a plurality of end cells connected in a tree via one relay buffer, and each of the clock trunks has an equal delay so that each cluster has equal delay. A clock distribution circuit, wherein each cluster is formed by determining the position of a relay buffer in a cluster and the number and position of said terminal cells.