JP3617430B2 - Block cell, block cell design method, and block cell design support apparatus - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a block cell that operates based on a clock signal, a block cell design method, and a block cell design support apparatus, and more particularly to a clock signal without increasing the number of circuits in a semiconductor integrated circuit in which block cells are mixed. The present invention relates to a block cell, a block cell design method, and a block cell design support apparatus suitable for reducing the skew of the block cell.
[0002]
[Prior art]
In recent years, not only chips with general elements but also semiconductor integrated circuits in which macro block cells (hereinafter simply referred to as block cells) such as RAM / ROM and CPU are mixed have been used. Here, the block cell refers to a cell that has been subjected to optimization such as placement and wiring in advance and whose function has been verified. In a semiconductor integrated circuit, these block cells are often configured as a synchronous system that operates in synchronization with other cells by a clock signal.
[0003]
In the synchronous system, each block cell is operated at the rising (falling) timing of the clock signal, so that the clock signal can be obtained at exactly the same timing in any block cell in the normal operation of the circuit. Is desirable. However, in reality, a clock signal delay (hereinafter referred to as a delay) is caused by the resistance of the wiring for routing the clock signal, the capacity of the wiring, and the terminal capacity of the connected block cells. For this reason, an arrival time difference (hereinafter referred to as a skew) occurs in the clock signal that can be obtained between the block cell closest to the input location of the clock signal and the block cell farthest from the input. Minimizing skew is indispensable for the normal operation of the circuit. Therefore, as a method for minimizing skew, a method of appropriately distributing clock signals by adjusting a wiring path using a binary tree (tree) wiring is often used.
[0004]
In this method, block cells are connected to obtain a delay balance point, and the balance point is connected to another balance point to construct a tree having a small skew to obtain a clock distribution wiring with a minimum skew. Is. For example, in Japanese Patent Application No. 3-030721, a branching point is set at a point where the skew is minimized to create a path. In this wiring method, multistage buffering can be performed to reduce delay. In order not to increase the delay due to the wiring, it is important to avoid the detour path and shorten the wiring path length as much as possible.
[0005]
[Problems to be solved by the invention]
However, even in the method of performing the multistage buffering, for example, as shown in FIG. , 12 is located on the opposite side, the wiring from the clock buffer 26 must be routed to the opposite side of the block cells 10, 12. When the skew increases due to this routing, the clock buffers 21 and 23 are respectively connected between the clock buffer 26 and the block cell 10 and between the clock buffer 26 and the block cell 12 in order to prevent the skew from increasing. Must be provided. In this case, since the block cells 10 and 12 include cells to be formed on the gate array, the arrangement of the block cells 10 and 12 is reversed unless the design of the block cells 10 and 12 is changed. Can not do it.
[0006]
Therefore, in such a case, in order to prevent an increase in skew, it may be necessary to add extra circuits such as clock buffers 21 and 23, and the increase in circuit causes an increase in cost and a semiconductor integrated circuit. For example, when there is a design requirement to make the periphery of the block cells 10 and 12 non-arranged areas, the clock buffers 21 and 23 cannot be provided, and the increase in skew is reduced. Can not do it.
[0007]
Therefore, the present invention has been made paying attention to such an unsolved problem of the prior art, and in a semiconductor integrated circuit in which block cells are mixed, the skew of the clock signal without increasing the number of circuits. It is an object of the present invention to provide a block cell, a block cell design method, and a block cell design support apparatus suitable for reducing the above.
[0008]
[Means for Solving the Problems]
To achieve the above object, the block cell according to claim 1 of the present invention is a block cell that operates based on a clock signal, and a clock terminal for inputting the clock signal is provided in the periphery of the block cell. A plurality are provided in the vicinity and operate based on clock signals input from the clock terminals.
[0009]
With this configuration, when a block cell is placed, the clock buffer that distributes the clock signal to the block cell is connected and wired to the clock terminal that is closest to the clock buffer among the multiple clock terminals. Then, the wiring length can be reduced.
[0010]
Furthermore, the block cell according to claim 2 according to the present invention is the block cell according to claim 1, wherein any one of the plurality of clock terminals is viewed from the center position of the block cell. Of these, it was provided at a position symmetrical to the other terminals.
[0011]
With such a configuration, since at least two clock terminals are provided symmetrically, when a block cell is arranged, the distance from the clock buffer that distributes the clock signal to the block cell to the clock terminal is short. If the clock buffer and the clock terminal are connected and wired, the wiring length can be further reduced.
[0012]
Here, the symmetric position refers to a position that is point-symmetric with the other terminals as viewed from the center position of the block cell, or a position that is line-symmetric with the other terminals with respect to a line passing through the center position of the block cell. Say.
[0013]
Furthermore, the block cell according to claim 3 according to the present invention is the block cell according to claim 1, wherein any one of the plurality of clock terminals is provided near one side of the periphery of the block cell. The other terminals among the plurality of clock terminals are provided in the vicinity of the side facing the one side in the periphery of the block cell.
[0014]
In such a configuration, since at least two clock terminals are provided in the vicinity of one side of the block cell and in the vicinity of the opposite side, when the block cell is arranged, the clock signal is supplied to the block cell. There is a possibility that the distance from the clock buffer that distributes the clock to the clock terminal may be shortened, and if the clock buffer and the clock terminal are connected and wired, the wiring length can be further reduced.
[0015]
The block cell according to claim 4 of the present invention is the block cell according to claim 1, wherein the clock terminal is provided in the vicinity of a different corner of the block cell.
[0016]
In such a configuration, since at least two clock terminals are provided in the vicinity of different corners of the block cell, when the block cell is arranged, the clock is distributed from the clock buffer that distributes the clock signal to the block cell. The distance to the terminal may be shortened, and the wiring length can be further reduced by connecting and wiring the clock buffer and the clock terminal.
[0017]
Furthermore, in the block cell according to claim 5 according to the present invention, in the block cell operating based on the clock signal, a clock terminal for inputting the clock signal is provided in the vicinity of the center in the block cell. A wiring region for wiring a clock signal line from a plurality of different locations on the periphery of the cell to the clock terminal is provided in the block cell.
[0018]
With such a configuration, when a block cell is arranged, the periphery of the block cell is arranged so that the distance between the clock buffer and the clock terminal is the shortest from the clock buffer that distributes the clock signal to the block cell. The wiring length can be reduced by wiring to a clock terminal provided in the vicinity of the center of the block cell via any of a plurality of locations serving as entrances of the wiring region.
[0019]
Furthermore, the block cell according to claim 6 of the present invention is the block cell according to claim 5, wherein the wiring region is configured to route a clock signal line from any part of the periphery of the block cell to the clock terminal. And a wiring area for wiring a clock signal line from a position that is symmetrical to any one of the peripheral edges of the block cell from the center position of the block cell to the clock terminal Including.
[0020]
With such a configuration, at least two locations that serve as the entrances to the wiring area in the periphery of the block cell are arranged symmetrically, so that when the block cell is arranged, the clock signal is distributed to the block cell. There is a possibility that the distance from the clock buffer to the clock terminal to be shortened, and if the clock buffer and the clock terminal are connected and wired, the wiring length can be further reduced.
[0021]
Here, the symmetric position refers to a position that is point-symmetric with any of the locations when viewed from the center position of the block cell, or is symmetrical with any location with respect to a line that passes through the center position of the block cell. The position which becomes.
[0022]
Furthermore, the block cell according to claim 7 of the present invention is the block cell according to claim 5, wherein the wiring region is configured to route a clock signal line from one side of the periphery of the block cell to the clock terminal. And a wiring region for wiring a clock signal line from the side facing the one side to the clock terminal in the periphery of the block cell.
[0023]
In such a configuration, at least two locations that serve as the entrances to the wiring area in the periphery of the block cell are provided in the vicinity of one side of the block cell and in the vicinity of the opposite side. When placed, the distance from the clock buffer that distributes the clock signal to the block cell to the clock terminal may be shortened. If the clock buffer and the clock terminal are connected and wired, the wiring length will be further reduced. Is possible.
[0024]
On the other hand, in order to achieve the above object, a block cell design method according to claim 8 according to the present invention is a block cell design method which operates based on a clock signal, and a clock terminal for inputting the clock signal. A clock terminal forming step in which a plurality of the block cells are provided in the vicinity of the periphery of the block cell, and a wiring step in which wiring is performed so that the block cell operates based on a clock signal input from each clock terminal.
[0025]
With such a method, a plurality of clock terminals are provided near the periphery of the block cell through the clock terminal formation step, and the block cell operates based on the clock signal input from the clock terminal through the wiring step. Wiring is performed.
[0026]
Here, the clock terminal forming step may be any step as long as it is a step of providing a plurality of clock terminals in the vicinity of the periphery of the block cell. Specifically, for example, the following method may be used. Can be mentioned. That is, in the block cell designing method according to claim 8, in the clock terminal forming step, any one of the plurality of clock terminals is viewed from a center position of the block cell. Provided at a position symmetrical to other terminals.
[0027]
With such a method, one of the clock terminals is provided at a position symmetrical to the other clock terminals as viewed from the center position of the block cell through the clock terminal formation step.
[0028]
Therefore, since at least two clock terminals are provided symmetrically, when a block cell is arranged, the distance from the clock buffer that distributes the clock signal to the block cell to the clock terminal may be shortened. If the clock buffer and the clock terminal are connected and wired, the wiring length can be further reduced, so that the effect of further reducing the clock signal skew can be obtained.
[0029]
The clock terminal forming step may be any step as long as it is a step of providing a plurality of clock terminals in the vicinity of the periphery of the block cell. Specifically, for example, the following method may be mentioned. It is done. That is, in the block cell designing method according to claim 8, in the clock terminal forming step, any one of the plurality of clock terminals is provided in the vicinity of one side of the periphery of the block cell, Of the plurality of clock terminals, the other terminals are provided in the vicinity of the side facing the one side in the periphery of the block cell.
[0030]
In such a method, after the clock terminal forming step, one of the clock terminals is provided in the vicinity of one side of the block cell, and the other clock terminal is the side facing the one side of the block cell. It is provided in the vicinity.
[0031]
Therefore, since at least two clock terminals are provided in the vicinity of one side of the block cell and in the vicinity of the opposite side, when the block cell is arranged, the clock buffer that distributes the clock signal to the block cell is used. There is a possibility that the distance to the clock terminal may be shortened. If the clock buffer and the clock terminal are connected and wired, the wiring length can be further reduced, so that the skew of the clock signal can be further reduced. Is obtained.
[0032]
The clock terminal forming step may be any step as long as it is a step of providing a plurality of clock terminals in the vicinity of the periphery of the block cell. Specifically, for example, the following method may be mentioned. It is done. That is, in the block cell design method according to claim 8, in the clock terminal forming step, the clock terminals are provided in the vicinity of different corners of the block cell.
[0033]
In such a method, the clock terminals are provided in the vicinity of different corners of the block cell through the clock terminal formation step.
[0034]
Therefore, since at least two clock terminals are provided near different corners of the block cell, when the block cell is arranged, the distance from the clock buffer that distributes the clock signal to the block cell to the clock terminal is short. If the clock buffer and the clock terminal are connected and wired, the wiring length can be further reduced, so that the effect of further reducing the clock signal skew can be obtained.
[0035]
Furthermore, the block cell design method according to claim 9 according to the present invention is the block cell design method that operates based on a clock signal, wherein the clock terminal for inputting the clock signal is centered in the block cell. A clock terminal forming step provided in the vicinity; and a wiring region forming step in which a wiring region for wiring a clock signal line from a plurality of different locations on the periphery of the block cell to the clock terminal is provided in the block cell.
[0036]
In such a method, the clock terminal is provided in the vicinity of the center of the block cell through the clock terminal formation process, and the clock signal is transmitted from a plurality of different locations on the periphery of the block cell to the clock terminal through the wiring area formation process. A wiring region for wiring is provided in the block cell.
[0037]
Here, the wiring region forming step is any step as long as a wiring region for wiring a clock signal line from a plurality of different locations on the periphery of the block cell to the clock terminal is provided in the block cell. However, specific examples include the following methods. That is, in the block cell design method according to claim 9, the wiring region forming step includes a wiring region for wiring a clock signal line from any part of the periphery of the block cell to the clock terminal, A wiring region for wiring a clock signal line from a position that is symmetrical to any one of the peripheral positions of the block cell as viewed from the center position of the block cell to the clock terminal. Provide.
[0038]
With such a method, a wiring region for wiring a clock signal line from any part of the periphery of the block cell to the clock terminal through the wiring region forming step, and the block cell as viewed from the center position of the block cell A wiring region for wiring a clock signal line from a position that is symmetric with respect to any one of the peripheral edges to a clock terminal is provided in the block cell.
[0039]
Therefore, since at least two locations serving as the entrances to the wiring area are arranged symmetrically on the periphery of the block cell, when the block cell is arranged, the clock terminal that distributes the clock signal to the block cell from the clock terminal If the clock buffer and the clock terminal are connected and wired, the wiring length can be further reduced, so that the clock signal skew can be further reduced. It is done.
[0040]
The wiring region forming step is any step as long as a wiring region for wiring a clock signal line from a plurality of different locations on the periphery of the block cell to the clock terminal is provided in the block cell. Specifically, for example, the following method is exemplified. That is, in the block cell design method according to claim 9, the wiring region forming step includes a wiring region for wiring a clock signal line from one side of the periphery of the block cell to the clock terminal, and A wiring region for wiring a clock signal line from a side opposite to the one side of the periphery of the block cell to the clock terminal is provided in the block cell.
[0041]
In such a method, a wiring region for wiring the clock signal line from one side of the block cell to the clock terminal through the wiring region forming step, and the clock from the side opposite to the one side of the block cell. A wiring area for wiring the clock signal line to the terminal is provided in the block cell.
[0042]
Therefore, at least two locations that serve as the entrances to the wiring area in the periphery of the block cell are provided in the vicinity of one side of the block cell and in the vicinity of the opposite side. There is a possibility that the distance from the clock buffer that distributes the clock signal to the block cell and the clock terminal may be shortened. If the clock buffer and the clock terminal are connected and wired, the wiring length can be further reduced. The effect of further reducing the skew is obtained.
[0043]
On the other hand, in order to achieve the above object, a block cell design support apparatus according to claim 10 according to the present invention is a block cell design support apparatus that operates based on a clock signal for inputting the clock signal. Clock terminal forming means for providing a plurality of clock terminals in the vicinity of the periphery of the block cell, and wiring means for performing wiring so that the block cell operates based on a clock signal input from each clock terminal.
[0044]
In such a configuration, the clock terminal forming means provides a plurality of clock terminals in the vicinity of the periphery of the block cell, and the wiring means provides wiring so that the block cell operates based on the clock signal input from the clock terminal. Done.
[0045]
Here, the clock terminal forming means may have any configuration as long as a plurality of clock terminals are provided in the vicinity of the periphery in the block cell. A configuration is mentioned. That is, in the block cell design support apparatus according to claim 10, the clock terminal forming unit sets one of the plurality of clock terminals to the plurality of clock terminals when viewed from the center position of the block cell. Of these, it is provided at a position symmetrical to the other terminals.
[0046]
With such a configuration, one of the clock terminals is provided at a position symmetrical to the other clock terminals as viewed from the center position of the block cell by the clock terminal forming means.
[0047]
Therefore, since at least two clock terminals are provided symmetrically, when a block cell is arranged, the distance from the clock buffer that distributes the clock signal to the block cell to the clock terminal may be shortened. If the clock buffer and the clock terminal are connected and wired, the wiring length can be further reduced, so that the effect of further reducing the clock signal skew can be obtained.
[0048]
Further, the clock terminal forming means may have any configuration as long as a plurality of clock terminals are provided in the vicinity of the periphery of the block cell. Specifically, for example, the following configuration is used. Is mentioned. That is, in the block cell design support apparatus according to claim 10, the clock terminal forming unit provides one of the plurality of clock terminals in the vicinity of one side of the periphery of the block cell, Of the plurality of clock terminals, the other terminals are provided in the vicinity of the side facing the one side in the periphery of the block cell.
[0049]
In such a configuration, one of the clock terminals is provided in the vicinity of one side of the block cell by the clock terminal forming means, and the other clock terminal is provided on the side opposite to the one side of the block cell. It is provided in the vicinity.
[0050]
Therefore, since at least two clock terminals are provided in the vicinity of one side of the block cell and in the vicinity of the opposite side, when the block cell is arranged, the clock buffer that distributes the clock signal to the block cell is used. There is a possibility that the distance to the clock terminal may be shortened. If the clock buffer and the clock terminal are connected and wired, the wiring length can be further reduced, so that the skew of the clock signal can be further reduced. Is obtained.
[0051]
Further, the clock terminal forming means may have any configuration as long as a plurality of clock terminals are provided in the vicinity of the periphery of the block cell. Specifically, for example, the following configuration is used. Is mentioned. That is, in the block cell design support apparatus according to claim 10, the clock terminal forming means provides the clock terminals in the vicinity of different corners of the block cell.
[0052]
With such a configuration, the clock terminal is provided in the vicinity of different corners of the block cell by the clock terminal forming means.
[0053]
Therefore, since at least two clock terminals are provided near different corners of the block cell, when the block cell is arranged, the distance from the clock buffer that distributes the clock signal to the block cell to the clock terminal is short. If the clock buffer and the clock terminal are connected and wired, the wiring length can be further reduced, so that the effect of further reducing the clock signal skew can be obtained.
[0054]
Furthermore, the block cell design support apparatus according to claim 11 according to the present invention is a block cell design support apparatus that operates based on a clock signal, wherein a clock terminal for inputting the clock signal is provided in the block cell. Clock terminal forming means provided in the vicinity of the center, and wiring area forming means for providing a wiring area for wiring a clock signal line from a plurality of different locations on the periphery of the block cell to the clock terminal. Prepare.
[0055]
In such a configuration, the clock terminal is provided in the vicinity of the center of the block cell by the clock terminal forming means, and the clock signal line is connected to the clock terminal from a plurality of different locations on the periphery of the block cell by the wiring area forming means. A wiring region for wiring is provided in the block cell.
[0056]
Here, the wiring area forming means may have any configuration as long as a wiring area for wiring a clock signal line from a plurality of different locations on the periphery of the block cell to the clock terminal is provided in the block cell. Although there may be, specifically, the following structures are mentioned, for example. That is, in the block cell design support apparatus according to claim 11, the wiring region forming means includes a wiring region for wiring a clock signal line from any position in the periphery of the block cell to the clock terminal. A wiring area for wiring a clock signal line from a position that is symmetrical to any one of the peripheral positions of the block cell as viewed from the center position of the block cell to the clock terminal. It is designed to be provided.
[0057]
With such a configuration, the wiring region forming means causes the wiring region for wiring the clock signal line from any part of the periphery of the block cell to the clock terminal, and the block cell as viewed from the center position of the block cell. A wiring region for wiring a clock signal line from a position at a position symmetrical to any one of the peripheral edges to a clock terminal is provided in the block cell.
[0058]
Therefore, since at least two locations serving as the entrances to the wiring area are arranged symmetrically on the periphery of the block cell, when the block cell is arranged, the clock terminal that distributes the clock signal to the block cell from the clock terminal If the clock buffer and the clock terminal are connected and wired, the wiring length can be further reduced, so that the clock signal skew can be further reduced. It is done.
[0059]
In addition, the wiring region forming means may have any configuration as long as a wiring region for wiring a clock signal line from a plurality of different locations on the periphery of the block cell to the clock terminal is provided in the block cell. However, specifically, for example, the following configuration may be mentioned. That is, in the block cell design support apparatus according to claim 11, the wiring region forming unit includes a wiring region for wiring a clock signal line from one side of the periphery of the block cell to the clock terminal, A wiring region for wiring a clock signal line from the side facing the one side to the clock terminal in the periphery of the block cell is provided in the block cell.
[0060]
In such a configuration, the wiring region forming means causes the wiring region for wiring the clock signal line from one side of the block cell to the clock terminal, and the clock terminal from the side facing the one side of the block cell. A wiring region for wiring the clock signal line is provided in the block cell.
[0061]
Therefore, since at least two locations of the periphery of the block cell that serve as the entrance to the wiring area are provided in the vicinity of one side of the block cell and in the vicinity of the opposite side, when the block cell is arranged, There is a possibility that the distance from the clock buffer that distributes the clock signal to the block cell to the clock terminal may be shortened. If the clock buffer and the clock terminal are connected and wired, the wiring length can be further reduced, so the clock signal The effect of further reducing the skew is obtained.
[0062]
In the above, a block cell, a block cell design method, and a block cell design support apparatus for achieving the above object have been proposed. However, the present invention is not limited to this, and in order to achieve the above object, It is also possible to propose a storage medium storing a design support program for 7 block cells.
[0063]
A storage medium storing a design support program for a first block cell is a storage medium storing a design support program for a block cell that operates based on a clock signal, and a clock terminal for inputting the clock signal is connected to the storage medium. A program for causing a computer to function as a plurality of clock terminal forming means provided near the periphery of a block cell and a wiring means for performing wiring so that the block cell operates based on a clock signal input from each clock terminal Is a computer-readable storage medium storing
[0064]
With such a configuration, when the program stored in the storage medium is read by the computer and the computer functions in accordance with the read program, the same operation and effect as those of the block cell design support apparatus according to claim 10. Is obtained.
[0065]
The storage medium storing the second block cell design support program is the first block cell design support program, wherein the clock terminal forming means includes any one of the plurality of clock terminals, As viewed from the center position of the block cell, the clock cells are provided at positions symmetrical to the other terminals among the plurality of clock terminals.
[0066]
If it is such a structure, when the program memorize | stored in the storage medium is read by computer and a computer functions according to the read program, either clock terminal is formed by clock terminal formation means by clock terminal formation means Is provided at a position symmetrical to the other clock terminals when viewed from the center position of the block cell.
[0067]
Therefore, since at least two clock terminals are provided symmetrically, when a block cell is arranged, the distance from the clock buffer that distributes the clock signal to the block cell to the clock terminal may be shortened. If the clock buffer and the clock terminal are connected and wired, the wiring length can be further reduced, so that the effect of further reducing the clock signal skew can be obtained.
[0068]
In the storage medium storing the third block cell design support program, in the first block cell design support program, the clock terminal forming means may include any one of the plurality of clock terminals as the terminal. Provided in the vicinity of one side of the periphery of the block cell, and other terminals of the plurality of clock terminals are provided in the vicinity of the side opposite to the one side in the periphery of the block cell. .
[0069]
With such a configuration, when the program stored in the storage medium is read by the computer and the computer functions in accordance with the read program, any one of the clock terminals is one of the block cells by the clock terminal forming means. The other clock terminal is provided in the vicinity of the side opposite to the one side of the block cell.
[0070]
Therefore, since at least two clock terminals are provided in the vicinity of one side of the block cell and in the vicinity of the opposite side, when the block cell is arranged, the clock buffer that distributes the clock signal to the block cell is used. There is a possibility that the distance to the clock terminal may be shortened. If the clock buffer and the clock terminal are connected and wired, the wiring length can be further reduced, so that the skew of the clock signal can be further reduced. Is obtained.
[0071]
In the storage medium storing the fourth block cell design support program, in the first block cell design support program, the clock terminal forming means sets the clock terminal in the vicinity of a different corner of the block cell. Each is provided.
[0072]
With such a configuration, when a program stored in a storage medium is read by a computer and the computer functions in accordance with the read program, the clock terminal forming means causes the clock terminal to be near a different corner of the block cell. Are provided respectively.
[0073]
Therefore, since at least two clock terminals are provided near different corners of the block cell, when the block cell is arranged, the distance from the clock buffer that distributes the clock signal to the block cell to the clock terminal is short. If the clock buffer and the clock terminal are connected and wired, the wiring length can be further reduced, so that the effect of further reducing the clock signal skew can be obtained.
[0074]
A storage medium storing a fifth block cell design support program is a storage medium storing a block cell design support program that operates based on a clock signal, and has a clock terminal for inputting the clock signal. A clock terminal forming means provided near the center in the block cell, and a wiring area in the block cell for wiring a clock signal line from a plurality of different locations on the periphery of the block cell to the clock terminal A computer-readable storage medium storing a program for causing a computer to function as forming means.
[0075]
With such a configuration, when the program stored in the storage medium is read by the computer and the computer functions in accordance with the read program, the same operations and effects as those of the block cell design support device according to claim 11 are achieved. Is obtained.
[0076]
The storage medium storing the sixth block cell design support program is the fifth block cell design support program, wherein the wiring region forming means is configured to start from any of the peripheral edges of the block cell. A wiring region for routing a clock signal line to a clock terminal, and a clock signal from a position that is symmetrical to any one of the peripheral positions of the block cell as viewed from the center position of the block cell to the clock terminal A wiring area for wiring is provided in the block cell.
[0077]
With such a configuration, when the program stored in the storage medium is read by the computer and the computer functions in accordance with the read program, the wiring region forming means causes the program to be detected from any part of the periphery of the block cell. A wiring area for wiring the clock signal line to the clock terminal, and a clock signal line from the position that is symmetrical to one of the peripheral edges of the block cell as viewed from the center position of the block cell to the clock terminal A wiring region for providing the data is provided in the block cell.
[0078]
Therefore, since at least two locations serving as the entrances to the wiring area are arranged symmetrically on the periphery of the block cell, when the block cell is arranged, the clock terminal that distributes the clock signal to the block cell from the clock terminal If the clock buffer and the clock terminal are connected and wired, the wiring length can be further reduced, so that the clock signal skew can be further reduced. It is done.
[0079]
In the fifth block cell design support program, the storage area storing the seventh block cell design support program may be configured such that the wiring region forming means starts the clock from one side of the periphery of the block cell. A wiring region for wiring the clock signal line to the terminal and a wiring region for wiring the clock signal line from the side facing the one side of the periphery of the block cell to the clock terminal. It is designed to be provided.
[0080]
With such a configuration, when the program stored in the storage medium is read by the computer and the computer functions in accordance with the read program, the wiring area forming means causes the clock from one side of the block cell to the clock terminal. A wiring region for wiring the signal line and a wiring region for wiring the clock signal line from the side facing the one side of the block cell to the clock terminal are provided in the block cell.
[0081]
Therefore, at least two locations that serve as the entrances to the wiring area in the periphery of the block cell are provided in the vicinity of one side of the block cell and in the vicinity of the opposite side. There is a possibility that the distance from the clock buffer that distributes the clock signal to the block cell and the clock terminal may be shortened. If the clock buffer and the clock terminal are connected and wired, the wiring length can be further reduced. The effect of further reducing the skew is obtained.
[0082]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. 1 to 4 are diagrams showing a first embodiment of a block cell, a block cell design method, and a block cell design support apparatus according to the present invention.
[0083]
In this embodiment, a block cell, a block cell design method, and a block cell design support apparatus according to the present invention block a clock terminal C in a block cell 10 that operates based on a clock signal as shown in FIG. By providing a plurality in the vicinity of the periphery in the cell 10, when the block cell 10 is arranged, the wiring length between the block cell 10 and the clock buffer 26 is reduced and the skew of the clock signal is reduced. is there.
[0084]
First, the configuration of a computer system to which the present invention is applied will be described with reference to FIG. FIG. 1 is a block diagram showing a configuration of a computer system to which the present invention is applied.
[0085]
As shown in FIG. 1, the computer 100 includes a CPU 30 that controls operations and the entire system based on a control program, a ROM 32 that stores a control program for the CPU 30 in a predetermined area, data read from the ROM 32, and the like. A RAM 34 for storing calculation results required in the calculation process of the CPU 30, a CRTC 36 for converting data stored in a specific area of the RAM 34 into an image signal and outputting the image signal to the display device 34, and data for the external device The I / F 38 mediates input / output, and these are connected to each other via a bus 39 that is a signal line for transferring data so that data can be exchanged.
[0086]
The I / F 38 includes, as external devices, an input device 40 such as a keyboard and a mouse that can input data as a human interface, a storage device 42 that stores data, tables, and the like as files, and a screen based on image signals. Is connected to a display device 44.
[0087]
The RAM 34 has a VRAM 35 that stores display data for display on the display device 44 as a specific area, and the VRAM 35 can be accessed independently by the CPU 30 and the CRTC 36.
[0088]
The CRTC 36 sequentially reads display data stored in the VRAM 35 from the top address in a predetermined cycle, converts the read display data into an image signal, and outputs the image signal to the display device 44.
[0089]
The storage device 42 has a role as a cell library for storing arrangement data for configuring the block cell 10 that has been subjected to optimization of arrangement and wiring in advance and whose function verification has been completed.
[0090]
The CPU 30 includes a microprocessing unit MPU and the like. When designing a semiconductor integrated circuit, the CPU 30 starts a predetermined program stored in a predetermined area of the ROM 32, and performs design support processing shown in the flowchart of FIG. 2 according to the program. It is supposed to run. FIG. 2 is a flowchart showing the design support process.
[0091]
The design support process is a process for generating chip mask pattern data necessary for manufacturing a semiconductor chip in the semiconductor integrated circuit and wiring mask pattern data necessary for forming a wiring pattern in the semiconductor integrated circuit. When executed in the CPU 30, first, as shown in FIG. 2, the process proceeds to step S100.
[0092]
In step S100, the arrangement data of the block cell 10 is read from the storage device 42, and a plurality of clock terminals C for inputting a clock signal are provided in the vicinity of the periphery in the block cell 10, and the block cell is based on the read arrangement data. Each cell in 10 is arranged. Note that the arrangement here is performed in a space virtually formed on the computer 100. The same applies to the wiring in the block cell 10 and the arrangement / wiring of the block cell 10.
[0093]
Specifically, in step S100, for example, as shown in FIG. ₂ , C ₄ , C ₆ , C ₈ Is provided in the vicinity of the center of each side of the block cell 10 and a clock terminal C is provided. ₁ , C ₃ , C ₅ , C ₇ Is provided in the vicinity of each corner of the block cell 10. FIG. 3 is a diagram illustrating a configuration of the block cell 10.
[0094]
Next, the process proceeds to step S102, where each cell in the block cell 10 is wired based on the read arrangement data, and at this time, each clock terminal C ₁ ~ C ₈ The block cell 10 is wired so that the block cell 10 operates on the basis of the clock signal input from, and the process proceeds to step S104.
[0095]
In step S104, it is determined whether or not the configuration of all block cells 10 has been completed. When it is determined that the configuration of all block cells 10 has been completed (Yes), the process proceeds to step S106 and automatic wiring is performed. According to an algorithm or the like, each block cell 10 and a clock buffer are arranged in the cell arrangement region of the semiconductor chip, and a clock buffer that distributes a clock signal to the block cell 10 and a clock terminal C of the block cell 10 ₁ ~ C ₈ Are connected and wired to the clock terminal closest to the clock buffer, and the process proceeds to step S108.
[0096]
In step S108, chip mask pattern data and wiring mask pattern data are generated based on the placement / wiring results in steps S100, S102, and S106, and the process proceeds to step S110 to generate the generated chip mask pattern data and wiring mask pattern. The data is stored in the storage device 42, and the series of processing ends.
[0097]
On the other hand, when it is determined in step S104 that the configuration of all the block cells 10 is not completed (No), the process proceeds to step S100.
[0098]
Next, the operation of the first embodiment will be described with reference to FIG. FIG. 4 is a plan view showing a state in which the block cells 10 and 12 designed according to the present embodiment are arranged and wired.
[0099]
When designing a semiconductor integrated circuit using a block cell, the designer selects a block cell having a desired function from the storage device 42 and selects the block cell corresponding to the function of the semiconductor integrated circuit to be realized. The connection relationship is defined for the block cells. Here, as shown in FIG. 4, block cells 10 and 12 are selected as block cells.
[0100]
When the block cell is selected and the connection relationship is defined in this way, the arrangement data of the block cell 10 is read from the storage device 42 by the CPU 30 through step S100, and the clock terminal C is in the vicinity of the periphery in the block cell 10. And a plurality of cells in the block cell 10 are arranged based on the read arrangement data. In forming the clock terminal C, the clock terminal C ₂ , C ₄ , C ₆ , C ₈ Are respectively provided in the vicinity of the center of each side of the block cell 10 and the clock terminal C ₁ , C ₃ , C ₅ , C ₇ Is provided in the vicinity of each corner of the block cell 10.
[0101]
Next, in step S102, each cell in the block cell 10 is wired based on the read arrangement data, and at this time, each clock terminal C ₁ ~ C ₈ The inside of the block cell 10 is wired so that the block cell 10 operates based on the clock signal input from.
[0102]
Therefore, the block cell 10 is configured by a series of these processes. Note that the series of processing is similarly performed for the block cell 12.
[0103]
Next, through step S106, each of the block cells 10, 12 and the clock buffer, etc. are arranged in the cell arrangement area of the semiconductor chip by an automatic wiring algorithm, and the clock buffer for distributing the clock signal to the block cells 10, 12. The clock terminals C of the block cells 10 and 12 ₁ ~ C ₈ Are connected and wired to the clock terminal closest to the clock buffer.
[0104]
In the example of FIG. 4, first, the root clock buffer 20, the clock buffers 22 to 26, and the block cells 10 and 12 are arranged. The root clock buffer 20 and the clock buffers 22 to 26 are connected and wired, and the clock buffer 26 and the clock terminal C of the block cell 10 are connected. ₁ ~ C ₈ Clock terminal C closest to the clock buffer 26 ₃ Are connected and wired, and the clock buffer 26 and the clock terminal C of the block cell 12 are connected. ₁ ~ C ₈ Clock terminal C closest to the clock buffer 26 ₁ Are connected and wired.
[0105]
Next, through steps S108 and S110, chip mask pattern data and wiring mask pattern data are generated based on the placement / wiring results in steps S100, S102, and S106, and the generated chip mask pattern data and wiring mask pattern data are generated. Is stored in the storage device 42.
[0106]
Then, based on the chip mask pattern data and the wiring mask pattern data, a semiconductor integrated circuit is manufactured. Specifically, a semiconductor chip is manufactured by forming bulk layers of standard cells and basic cells on a substrate using a mask pattern manufactured based on chip mask pattern data. Then, a wiring layer for wiring the standard cell and the basic cell is formed on the manufactured semiconductor chip by using the mask pattern manufactured based on the wiring mask pattern data, whereby a semiconductor integrated circuit is manufactured.
[0107]
Thus, in this embodiment, the clock terminal C ₁ ~ C ₈ Are provided near the periphery of the block cell 10 and each clock terminal C ₁ ~ C ₈ The inside of the block cell 10 is wired so as to operate based on the clock signal inputted from the above.
[0108]
Thus, when the block cell 10 is arranged, the clock buffer 12 that distributes the clock signal to the block cell 10 and the clock terminal C ₁ ~ C ₈ Clock terminal C closest to the clock buffer 26 ₃ Since the wiring length can be reduced as compared with the prior art, the skew of the clock signal can be reduced without adding an extra circuit.
[0109]
Furthermore, in this embodiment, the clock terminal C ₂ , C ₄ , C ₆ , C ₈ Is provided in the vicinity of the center of each side of the block cell 10 and a clock terminal C is provided. ₁ , C ₃ , C ₅ , C ₇ One is provided in the vicinity of each corner of the block cell 10.
[0110]
As a result, when the block cell 10 is disposed, the distance from the clock buffer 26 that distributes the clock signal to the block cell 10 to the clock terminal may be shortened, and the clock buffer 26 and the clock terminal may be connected and wired. Thus, since the wiring length can be further reduced, the skew of the clock signal can be further reduced.
[0111]
In the above embodiment, step S100 corresponds to the clock terminal forming step according to claim 8, or the clock terminal forming means according to claim 10, and step S102 is the wiring step according to claim 8, or claim 10. It corresponds to the wiring means described.
[0112]
Next, a second embodiment of the present invention will be described with reference to the drawings. 5 to 7 are diagrams showing a second embodiment of a block cell, a block cell design method, and a block cell design support apparatus according to the present invention. Hereinafter, only the parts different from the first embodiment will be described, and the same parts as those in the first embodiment will be denoted by the same reference numerals and the description thereof will be omitted.
[0113]
In this embodiment, a block cell, a block cell design method, and a block cell design support apparatus according to the present invention block a clock terminal C in a block cell 10 that operates based on a clock signal as shown in FIG. The present invention is applied to the case where the wiring length between the block cell 10 and the clock buffer 26 is reduced and the skew of the clock signal is reduced when the block cell 10 is arranged by providing the cell 10 near the center thereof. .
[0114]
When designing a semiconductor integrated circuit, the CPU 30 starts a predetermined program stored in a predetermined area of the ROM 32 and executes a design support process shown in the flowchart of FIG. 5 according to the program. FIG. 5 is a flowchart showing the design support process.
[0115]
The design support process is a process for generating chip mask pattern data necessary for manufacturing a semiconductor chip in the semiconductor integrated circuit and wiring mask pattern data necessary for forming a wiring pattern in the semiconductor integrated circuit. When executed by the CPU 30, as shown in FIG. 5, first, the process proceeds to step S200.
[0116]
In step S200, the arrangement data of the block cell 10 is read from the storage device 42, the clock terminal C for inputting the clock signal is provided in the vicinity of the center in the block cell 10, and the process proceeds to step S202. A wiring region for wiring the clock signal line from a plurality of different locations on the periphery to the clock terminal C is provided in the block cell 10, and each cell in the block cell 10 other than the wiring region is based on the read arrangement data. Place in the area. Note that the arrangement here is performed in a space virtually formed on the computer 100. The same applies to the wiring in the block cell 10 and the arrangement / wiring of the block cell 10.
[0117]
Specifically, in this step S202, for example, as shown in FIG. ₁ Wiring region LP for wiring the clock signal line from the clock terminal C to the clock terminal C ₁ And the side center In of the block cell 10 ₂ Wiring region LP for wiring the clock signal line from the clock terminal C to the clock terminal C ₂ And the side center In of the block cell 10 ₃ Wiring region LP for wiring the clock signal line from the clock terminal C to the clock terminal C ₃ And the side center In of the block cell 10 ₄ Wiring region LP for wiring the clock signal line from the clock terminal C to the clock terminal C ₄ Are provided in the block cell 10. In addition, each cell in the block cell 10 is connected to the wiring region LP in the block cell 10. ₁ ~ LP ₄ Region CP other than ₁ ~ CP ₄ To place. FIG. 6 is a diagram illustrating a configuration of the block cell 10.
[0118]
Next, the process proceeds to step S204, where each cell in the block cell 10 is wired based on the read arrangement data, and at this time, the block cell 10 is operated based on the clock signal input from the clock terminal C. The inside of the block cell 10 is wired, and the process proceeds to step S206.
[0119]
In step S206, it is determined whether or not the configuration of all block cells 10 has been completed. When it is determined that the configuration of all block cells 10 has been completed (Yes), the process proceeds to step S208, and automatic wiring is performed. The block cells 10 and clock buffers are arranged and wired in the cell arrangement region of the semiconductor chip by an algorithm or the like, and the process proceeds to step S210.
[0120]
In step S210, chip mask pattern data and wiring mask pattern data are generated based on the placement / wiring results in steps S200 to S204 and S208, and the process proceeds to step S110 to generate the generated chip mask pattern data and wiring mask pattern. The data is stored in the storage device 42, and the series of processing ends.
[0121]
On the other hand, when it is determined in step S206 that the configuration of all the block cells 10 is not completed (No), the process proceeds to step S200.
[0122]
Next, the operation of the second embodiment will be described with reference to FIG. FIG. 7 is a plan view showing a state in which the block cells 10 and 12 designed according to the present embodiment are arranged and wired.
[0123]
When designing a semiconductor integrated circuit using a block cell, the designer selects a block cell having a desired function from the storage device 42 and selects the block cell corresponding to the function of the semiconductor integrated circuit to be realized. The connection relationship is defined for the block cells. Here, as shown in FIG. 7, block cells 10 and 12 are selected as block cells.
[0124]
When the block cell is selected and the connection relation is defined in this manner, the arrangement data of the block cell 10 is read from the storage device 42 by the CPU 30 through steps S200 and S202, and the clock terminal C is stored in the block cell 10 in the block cell 10. A wiring region is provided in the block cell 10 in the vicinity of the center for wiring the clock signal line from a plurality of different locations on the periphery of the block cell 10 to the clock terminal C, and based on the read arrangement data. Thus, each cell in the block cell 10 is arranged in an area other than the wiring area. In the formation of this wiring region, the wiring region LP ₁ And wiring area LP ₂ And wiring area LP ₃ And wiring area LP ₄ Are provided in the block cell 10. Further, in the arrangement of each cell in the block cell 10, each cell in the block cell 10 is a region CP. ₁ ~ CP ₄ Placed in.
[0125]
Next, through step S204, each cell in the block cell 10 is wired based on the read arrangement data, and at this time, the block cell 10 is operated based on the clock signal input from the clock terminal C. The inside of the block cell 10 is wired.
[0126]
Therefore, the block cell 10 is configured by a series of these processes. Note that the series of processing is similarly performed for the block cell 12.
[0127]
Next, through step S208, the block cells 10, 12 and the clock buffer and the like are arranged in the cell arrangement area of the semiconductor chip by an automatic wiring algorithm or the like.
[0128]
In the example of FIG. 7, first, the root clock buffer 20, clock buffers 22 to 26, and block cells 10 and 12 are arranged. The root clock buffer 20 and each of the clock buffers 22 to 26 are connected and wired, and the wiring region LP of the block cell 10 is set so that the distance between the clock buffer 26 and the clock terminal C of the block cell 10 is the shortest. ₂ The clock buffer 26 and the clock terminal C of the block cell 10 are connected and wired via the circuit, and the wiring of the block cell 12 is made so that the distance between the clock buffer 26 and the clock terminal C of the block cell 12 is the shortest. Region LP ₁ The clock buffer 26 and the clock terminal C of the block cell 12 are connected / wired via.
[0129]
Then, through steps S108 and S110, chip mask pattern data and wiring mask pattern data are generated based on the placement / wiring results in steps S100, S102, and S106, and the generated chip mask pattern data and wiring mask pattern data are generated. Is stored in the storage device 42.
[0130]
In this way, in the present embodiment, the clock terminal C is provided in the block cell 10 in the vicinity of the center thereof, and the clock signal line is wired from the plurality of different locations on the periphery of the block cell 10 to the clock terminal C. Wiring area LP ₁ ~ LP ₄ Is provided in the block cell 10.
[0131]
Thus, when the block cell 10 is arranged, the block cell is arranged such that the distance between the clock buffer 26 and the clock terminal C of the block cell 10 is the shortest from the clock buffer 26 that distributes the clock signal to the block cell 10. If wiring is performed up to the clock terminal C of the block cell 10 via any of a plurality of locations that serve as entrances of the wiring region, the wiring length can be reduced as compared with the prior art. The skew of the clock signal can be reduced without adding an additional circuit.
[0132]
Furthermore, in the present embodiment, the side center In of the block cell 10 ₁ Wiring region LP for wiring the clock signal line from the clock terminal C to the clock terminal C ₁ And the side center In of the block cell 10 ₂ Wiring region LP for wiring the clock signal line from the clock terminal C to the clock terminal C ₂ And the side center In of the block cell 10 ₃ Wiring region LP for wiring the clock signal line from the clock terminal C to the clock terminal C ₃ And the side center In of the block cell 10 ₄ Wiring region LP for wiring the clock signal line from the clock terminal C to the clock terminal C ₄ Are provided in the block cell 10.
[0133]
As a result, when the block cell 10 is disposed, the distance from the clock buffer 26 that distributes the clock signal to the block cell 10 to the clock terminal may be shortened, and the clock buffer 26 and the clock terminal may be connected and wired. Thus, since the wiring length can be further reduced, the skew of the clock signal can be further reduced.
[0134]
In the above embodiment, step S200 corresponds to the clock terminal forming step according to claim 9 or the clock terminal forming means according to claim 11, and step S202 corresponds to the wiring region forming step according to claim 9. This corresponds to the wiring region forming means described in Item 11.
[0135]
In the first embodiment, the clock terminal C ₂ , C ₄ , C ₆ , C ₈ Is provided in the vicinity of the center of each side of the block cell 10 and a clock terminal C is provided. ₁ , C ₃ , C ₅ , C ₇ However, the present invention is not limited to this, and for example, a clock terminal C may be provided as shown in FIG. FIG. 8 is a diagram showing another embodiment of the present invention.
[0136]
First, in the example of FIG. 8A, the clock terminal C is not provided on each side of the block cell 10, and the clock terminal C is not provided. ₁ , C ₃ , C ₅ , C ₇ One is provided in the vicinity of each corner of the block cell 10.
[0137]
Next, in the example of FIG. 8B, the clock terminal C is not provided at each corner of the block cell 10, and the clock terminal C is not provided. ₂ , C ₄ , C ₆ , C ₈ One is provided in the vicinity of the center of each side of the block cell 10. Of course, it is not limited to being provided at the center of each side of the block cell 10 as described above, and may be provided at any location on each side.
[0138]
Next, in the example of FIG. 8C, the clock terminal C ₁ Is provided at an arbitrary position on the periphery of the block cell 10 (for example, one corner of the block cell 10), and the clock terminal C ₅ From the center position of the block cell 10 ₁ Are provided at point-symmetric positions.
[0139]
Next, in the example of FIG. 8D, the clock terminal C ₁ Is provided at an arbitrary position on the periphery of the block cell 10 (for example, one corner of the block cell 10), and the clock terminal C ₃ For the horizontal line passing through the center position O of the block cell 10 ₁ Are provided at positions symmetrical to the line.
[0140]
Next, in the example of FIG. ₁ Is provided at an arbitrary position on the periphery of the block cell 10 (for example, one corner of the block cell 10), and the clock terminal C ₇ For the vertical line passing through the center position O of the block cell 10 ₁ Are provided at positions symmetrical to the line.
[0141]
Next, in the example of FIG. ₃ , C ₅ , C ₈ In providing the clock terminal C ₅ And clock terminal C ₈ Distance a to the clock terminal C ₃ And clock terminal C ₈ Distance b to the clock terminal C ₃ And clock terminal C ₅ These clock terminals C are provided so that the sum total with the distance c is maximized. Although the case where three clock terminals C are provided has been described here, the same procedure can be used when more clock terminals C are provided.
[0142]
As a result, each clock terminal C ₃ , C ₅ , C ₈ Are arranged in a distributed manner, when the block cell 10 is arranged, there is a possibility that the distance from the clock buffer 26 that distributes the clock signal to the block cell 10 to the clock terminal may be shortened. And the wiring length can be further reduced.
[0143]
Next, in the example of FIG. ₃ , C ₅ , C ₈ Each clock terminal C ₃ , C ₅ , C ₈ The internal cell 14 that requires the clock signal input from and the clock terminal C ₈ Wiring length l ₁ And internal cell 14 and clock terminal C ₅ Wiring length l ₂ And internal cell 14 and clock terminal C ₃ Wiring length l ₃ These clock terminals C are provided so that the total sum of the two is minimized. Although the case where three clock terminals C are provided has been described here, the same procedure can be used when more clock terminals C are provided.
[0144]
Thereby, when the block cell 10 is arranged, the distance from the clock terminal C connected to the clock buffer 26 that distributes the clock signal to the block cell 10 to the internal cell 14 may be shortened. If the clock terminal is connected and wired, the wiring length can be further reduced.
[0145]
Note that the example of FIG. 8G is more preferably combined with the example of FIG. 8F from the viewpoint of reducing the wiring length.
[0146]
In the second embodiment, the side center In of the block cell 10 ₁ Wiring region LP for wiring the clock signal line from the clock terminal C to the clock terminal C ₁ And the side center In of the block cell 10 ₂ Wiring region LP for wiring the clock signal line from the clock terminal C to the clock terminal C ₂ And the side center In of the block cell 10 ₃ Wiring region LP for wiring the clock signal line from the clock terminal C to the clock terminal C ₃ And the side center In of the block cell 10 ₄ Wiring region LP for wiring the clock signal line from the clock terminal C to the clock terminal C ₄ However, the present invention is not limited to this, and a wiring region may be provided in the block cell 10 as shown in FIG. FIG. 9 is a diagram showing another embodiment of the present invention.
[0147]
First, in the example of FIG. 9A, each side In of the block cell 10 ₁ ~ In ₄ Wiring region LP for wiring the clock signal line from the clock terminal C to the clock terminal C ₁ ~ LP ₄ Each corner portion In of the block cell 10 ₅ ~ In ₈ Wiring region LP for wiring the clock signal line from the clock terminal C to the clock terminal C ₅ ~ LP ₈ Are provided in the block cell 10.
[0148]
Next, in the example of FIG. 9B, each side In of the block cell 10 ₁ ~ In ₄ Wiring region LP for wiring the clock signal line from the clock terminal C to the clock terminal C ₁ ~ LP ₄ And each corner portion In of the block cell 10 ₅ ~ In ₈ Wiring region LP for wiring the clock signal line from the clock terminal C to the clock terminal C ₅ ~ LP ₈ Are provided in the block cell 10.
[0149]
Next, in the example of FIG. 9C, an arbitrary position on the periphery of the block cell 10 (for example, one corner portion In of the block cell 10). ₅ ) To the clock terminal C, the wiring region LP for wiring the clock signal line ₅ And the corner portion In viewed from the center position of the block cell 10. ₅ And point-symmetrical position In ₇ Wiring region LP for wiring the clock signal line from the clock terminal C to the clock terminal C ₇ Are provided in the block cell 10.
[0150]
Next, in the example of FIG. 9D, an arbitrary position on the periphery of the block cell 10 (for example, one corner portion In of the block cell 10). ₅ ) To the clock terminal C, the wiring region LP for wiring the clock signal line ₅ And a corner portion In with respect to a horizontal line passing through the center position of the block cell 10 ₅ And line-symmetrical position In ₆ Wiring region LP for wiring the clock signal line from the clock terminal C to the clock terminal C ₆ Are provided in the block cell 10.
[0151]
Next, in the example of FIG. 9E, an arbitrary position on the periphery of the block cell 10 (for example, one corner portion In of the block cell 10). ₅ ) To the clock terminal C, the wiring region LP for wiring the clock signal line ₅ And a corner portion In with respect to a vertical line passing through the center position of the block cell 10 ₅ And line-symmetrical position In ₈ Wiring region LP for wiring the clock signal line from the clock terminal C to the clock terminal C ₈ Are provided in the block cell 10.
[0152]
Next, in the example of FIG. ₄ And the point In of the periphery of the block cell 10 ₇ Distance a and point In ₄ And the point In of the periphery of the block cell 10 ₆ Distance b and point In ₆ And point In ₇ The positions of these points are determined so that the sum of the distance c and the distance c becomes the maximum, and the point In ₄ Wiring region LP for wiring the clock signal line from the clock terminal C to the clock terminal C ₄ And point In ₆ Wiring region LP for wiring the clock signal line from the clock terminal C to the clock terminal C ₆ And point In ₇ Wiring region LP for wiring the clock signal line from the clock terminal C to the clock terminal C ₇ Are provided in the block cell 10. Although the case where three wiring areas are provided has been described here, the same procedure can be used when a larger number of wiring areas are provided.
[0153]
As a result, a plurality of locations that serve as the entrances to the wiring regions are arranged in a distributed manner on the periphery of the block cell 10, so that when the block cell 10 is arranged, the clock buffer 26 that distributes the clock signal to the block cell 10 The distance to the clock terminal may be shortened, and the wiring length can be further reduced if the clock buffer 26 and the clock terminal are connected and wired.
[0154]
In the first and second embodiments, the case where the control program stored in advance in the ROM 32 is executed in the processes shown in the flowcharts of FIGS. 2 and 5 has been described. However, the present invention is not limited to this, and the program may be read from the storage medium storing the program showing these procedures into the RAM 34 and executed.
[0155]
Here, the storage medium is a semiconductor storage medium such as RAM or ROM, a magnetic storage type storage medium such as FD or HD, an optical reading type storage medium such as CD, CDV, LD, or DVD, or a magnetic storage type such as MO. / Optical reading type storage media, including any storage media that can be read by a computer regardless of electronic, magnetic, optical, or other reading methods.
[0156]
Further, in the first embodiment, the block cell, the block cell design method, and the block cell design support apparatus according to the present invention are operated based on the clock signal as shown in FIG. In FIG. 5, by providing a plurality of clock terminals C near the periphery of the block cell 10, when the block cell 10 is arranged, the wiring length between the block cell 10 and the clock buffer 26 is reduced, and the skew of the clock signal is reduced. Although it applied about the case, it is not restricted to this, It can apply also to other cases in the range which does not deviate from the main point of this invention.
[0157]
Also, in the second embodiment, the block cell, the block cell design method and the block cell design support apparatus according to the present invention are operated based on a clock signal as shown in FIG. In the case where the clock terminal C is provided in the block cell 10 near the center thereof, the wiring length between the block cell 10 and the clock buffer 26 is reduced when the block cell 10 is arranged, and the skew of the clock signal is reduced. However, the present invention is not limited to this, and can be applied to other cases without departing from the gist of the present invention.
[0158]
【The invention's effect】
As described above, according to the block cells of the first to seventh aspects of the present invention, the wiring length can be reduced as compared with the conventional case, so that the clock signal can be obtained without adding an extra circuit. The effect that the skew can be reduced is obtained.
[0159]
Furthermore, according to the block cell according to the second, fourth, sixth, or seventh aspect of the present invention, there is an effect that the skew of the clock signal can be further reduced.
[0160]
On the other hand, according to the block cell design method according to claim 8 or 9 of the present invention, since the wiring length can be reduced as compared with the conventional case, the clock signal can be generated without adding an extra circuit. The effect that the skew can be reduced is obtained.
[0161]
On the other hand, according to the block cell design support apparatus according to claim 10 or 11 of the present invention, since the wiring length can be reduced as compared with the conventional case, the clock signal can be obtained without adding an extra circuit. The effect that the skew can be reduced is obtained.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a computer system to which the present invention is applied.
FIG. 2 is a flowchart showing a design support process.
3 is a diagram showing a configuration of a block cell 10. FIG.
4 is a plan view showing a state in which block cells 10 and 12 designed according to the present embodiment are arranged and wired. FIG.
FIG. 5 is a flowchart showing design support processing;
6 is a diagram showing a configuration of a block cell 10. FIG.
7 is a plan view showing a state in which block cells 10 and 12 designed according to the present embodiment are arranged and wired. FIG.
FIG. 8 is a diagram showing another embodiment of the present invention.
FIG. 9 is a diagram showing another embodiment of the present invention.
FIG. 10 is a plan view showing a state in which block cells 10 and 12 designed by a conventional design method are arranged and wired.
[Explanation of symbols]
10,12 block cells
20 root clock buffer
22-26 clock buffer
100 computers
30 CPU
32 ROM
34 RAM
38 I / F
40 input devices
42 Storage device
44 Display device
C Reset terminal
LP wiring area
CP cell placement area

Claims (5)

In a block cell that operates based on a clock signal,
A clock terminal for inputting the clock signal is provided in the vicinity of the center of the block cell, and a wiring region for wiring the clock signal line from a plurality of different locations on the periphery of the block cell to the clock terminal is provided. A block cell provided in a block cell. In claim 1,
The wiring area includes a wiring area for wiring a clock signal line from any position of the periphery of the block cell to the clock terminal, and any of the periphery of the block cell as viewed from the center position of the block cell. And a wiring region for wiring a clock signal line from a location that is symmetrical to the location to the clock terminal. In claim 1,
The wiring region includes a wiring region for wiring a clock signal line from one side of the periphery of the block cell to the clock terminal, and a side from the side facing the one side of the periphery of the block cell. A block cell comprising a wiring region for wiring a clock signal line to a terminal. In a block cell design method that operates based on a clock signal,
A clock terminal forming step in which a clock terminal for inputting the clock signal is provided in the block cell in the vicinity of the center thereof, and a clock signal line is wired from a plurality of different locations on the periphery of the block cell to the clock terminal. And a wiring region forming step of providing the wiring region in the block cell. In a block cell design support device that operates based on a clock signal,
Clock terminal forming means for providing a clock terminal for inputting the clock signal in the vicinity of the center in the block cell, and wiring a clock signal line from a plurality of different locations on the periphery of the block cell to the clock terminal And a wiring region forming means for providing the wiring region in the block cell.

Images