JP2004165443A - Automated layout method, program, and recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To miniaturize an LSI by suppressing occurrence of a non-used area. <P>SOLUTION: An outer frame 11 is manufactured for an analogue circuit comprising analogue macros 10a and 10b according to the shape. A plurality of pseudo unit cells 12a-12f that inscribe the outer frame 11 are connected together. The analogue circuit is handled as a single unit cell which is represented by a set of pseudo unit cells 12-12f. The shape of the analogue circuit is represented by a set of coordinates of two opposing corners of the rectangular of pseudo unit cells 12a-12f, for later generation of layout information or automated layout wiring. Thus, even with an analogue circuit whose shape is other than rectangular, the increase in data quantity or calculation amount that follows the automated layout is suppressed while the occurrence of unused area is suppressed, resulting in a smaller size of an LSI chip. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an automatic layout method, and more particularly to an automatic layout method for automatically arranging and wiring circuits, wirings, and the like formed inside an LSI circuit (Large Scale Integrated Circuit) when designing the LSI circuit.
[0002]
[Prior art]
With the recent increase in the scale of LSIs, automatic layout and wiring tools are increasingly used when laying out circuit information (net list). In addition to terminal information, the netlist usually includes unit cells indicating basic logic circuits such as inverters, NANDs, and NORs, and connection information of such unit cells.
[0003]
When the LSI is automatically laid out, first, the unit cells described in the netlist are automatically arranged, and then the unit cells are automatically wired according to the netlist. (For example, refer to Patent Document 1).
[0004]
When an analog circuit / digital circuit mixed LSI is to be manufactured in such a procedure, the analog circuit is often treated as one large unit cell and automatically arranged and wired regardless of the configuration of the analog circuit. This is because, in general, if the connection between analog modules is left to automatic wiring, the required characteristics are often not satisfied. The first cause is that automatic wiring is performed with a minimum line width, so that wiring cannot be performed with a large line width. Second, it is not possible to give priority to wiring in order to reduce the parasitic resistance and capacitance for a specific connection.
[0005]
[Patent Document 1]
JP-A-7-085114 (paragraph numbers [0005] to [008], FIG. 12)
[0006]
[Problems to be solved by the invention]
However, when the unit cells are automatically arranged and routed based on the netlist, there are the following problems.
[0007]
FIG. 6 is a diagram for explaining a method of expressing unit cells in automatic placement and routing.
In the automatic placement and routing, a unit cell is represented by coordinates of two diagonal points 101 and 102 of a rectangle in order to reduce the amount of calculation at the time of automatic placement. Generally, there is no problem if the unit cell is expressed by the method shown in FIG. However, when expressing a large unit cell including an analog circuit, for example, the following problem may occur.
[0008]
FIG. 7 is a diagram for explaining a conventional expression method when expressing a unit cell including an analog circuit by automatic placement and routing.
For example, it is assumed that an analog circuit is configured by two analog macros 201 and 202 having different sizes that are already connected. When these analog macros 201 and 202 are grouped into one unit cell 203, this unit cell 203 is represented by one rectangle specified by the coordinates of two diagonal points, and therefore, no unused cells are arranged. An area 204 occurs.
[0009]
Such a situation cannot be avoided because the unit cell can only be represented by a square as described above. However, since other unit cells cannot be arranged in such an unused area 204, the presence of the unused area 204 hinders a reduction in the LSI chip size.
[0010]
The present invention has been made in view of such a point, and an object of the present invention is to provide an automatic layout method capable of reducing an unused area on an LSI chip without greatly increasing the amount of calculation involved in automatic layout processing. Aim.
[0011]
[Means for Solving the Problems]
The present invention provides an automatic layout method as illustrated in FIG. 1 in order to solve the above problem. An automatic layout method according to the present invention is an automatic layout method for automatically arranging and wiring unit cells of an LSI, wherein an outer frame surrounding the circuit is formed in a shape corresponding to the shape of the circuit, and a plurality of pseudo units inscribed in the outer frame are formed. The circuit is created by connecting cells, and the circuit is treated as one unit cell expressed by a set of the pseudo unit cells.
[0012]
According to such an automatic layout method, as shown in FIG. 1, first, the outer frame 11 is created so as to surround the analog circuit formed of the analog macros 10a and 10b in a shape corresponding to the shape of the analog circuit. You. Then, a plurality of pseudo unit cells 12a to 12f are connected and created so as to be inscribed in the outer frame 11, and the analog circuit is treated as one unit cell expressed by a set of these pseudo unit cells 12a to 12f. Is The shape of the unit cell, that is, the shape of the analog circuit is expressed by a set of expression data of the pseudo unit cells 12a to 12f, for example, the coordinates of two diagonal points as in the related art. And automatic placement and routing can be performed. As described above, by expressing an analog circuit having a shape other than a square by a set of a plurality of pseudo unit cells 12a to 12f corresponding to the shape, generation of an unused area on an LSI chip is suppressed. .
[0013]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
The automatic layout processing in the LSI design is executed by a computer. The program for executing the automatic layout process is stored in, for example, a storage device of the computer, and the computer reads the program from the storage device and executes a process according to the program.
[0014]
The computer can store the netlist in its own storage device, for example. That is, terminal information, a plurality of unit cells prepared in advance, and connection information thereof can be stored.
[0015]
The first embodiment of the automatic layout processing using such a computer will be described first.
FIG. 1 is a diagram for explaining an automatic layout method according to the first embodiment.
[0016]
In the first embodiment, a case will be described in which an analog circuit is composed of two analog macros 10a and 10b having different sizes as indicated by broken lines in the figure. Here, although not shown, the analog macros 10a and 10b are already connected, and wiring terminals are formed on the respective analog macros 10a and 10b at their edges or inside. Shall be
[0017]
In the automatic layout process, first, an outer frame 11 surrounding the periphery of a polygonal analog circuit which is not a square (rectangle or square) as a whole is created. The outer frame 11 is formed so that the wiring (not shown) between the analog macros 10a and 10b and the terminals between the analog macros 10a and 10b and the terminals at the edges of the analog macros 10a and 10b are all included in the outer frame 11. Further, in the outer frame 11, the sides L1, L2, L3, L4, L5, and L6 are straight lines, and the vertices P1, P2, P3, P4, P5, and P6 each have an angle of 90 degrees (°). Is created as follows.
[0018]
Then, a plurality of connected pseudo unit cells 12a, 12b, 12c, 12d, 12e, and 12f are inscribed in the outer frame 11. Here, the pseudo unit cells 12a to 12f are rectangular and are created along the respective sides L1 to L6 of the outer frame 11. The pseudo unit cells 12a to 12f are sequentially connected and created, and a closed circuit of the pseudo unit cells 12a to 12f is formed in the outer frame 11. The shape of each of the rectangular pseudo unit cells 12a to 12f is represented by two diagonal coordinates as in the related art.
[0019]
The analog circuit composed of the analog macros 10a and 10b is treated as one unit cell represented by a set of pseudo unit cells 12a to 12f, and terminal information is created for this unit cell. Subsequent creation of layout information of the entire circuit and automatic placement and routing use the expression data of this unit cell, that is, a set of two diagonal coordinates of the pseudo unit cells 12a to 12f. At this time, the area in each of the pseudo unit cells 12a to 12f and the internal area of the closed circuit formed by connection become an arrangement space of this unit cell.
[0020]
As described above, a polygonal analog circuit which is not a quadrangle as a whole is represented by a set of a plurality of pseudo unit cells 12a to 12f corresponding to the shape, thereby enabling an automatic layout while suppressing the generation of an unused area. become. Here, when expressing the shape of the analog circuit, the constraint that each pseudo unit cell 12a to 12f is represented by coordinates of two diagonal points of a rectangle is the same as the conventional one, and furthermore, the contents of the original netlist Is not changed, so that an automatic layout process can be performed while suppressing an increase in data.
[0021]
The flow of such automatic layout processing will be described.
FIG. 2 is a flowchart of the automatic layout processing according to the first embodiment.
First, an analog circuit, such as an analog circuit composed of the connected analog macros 10a and 10b shown in FIG. 1, which generates an unused area in the conventional method, is extracted from the netlist (step S1). .
[0022]
After the extraction in step S1, an outer frame 11 surrounding the analog circuit is created outside the analog circuit (step S2). As described above, the outer frame 11 is formed such that all the wirings and terminals between the analog macros 10a and 10b are included in the outer frame 11, and each of the sides L1 to L6 of the outer frame 11 is a straight line and each vertex P1. It is created so that the angle of P6 becomes 90 degrees.
[0023]
Next, the pseudo unit cells 12a to 12f are created inside the outer frame 11 along the sides L1 to L6 (step S3). Each of the pseudo unit cells 12a to 12f has a rectangular shape, and is represented by coordinates of two diagonal points. Each of the pseudo unit cells 12a to 12f is created starting from one of the vertices P1 to P6 of the outer frame 11 and, for example, counterclockwise from there along the sides L1 to L6. At this time, the pseudo unit cells 12a to 12f are connected and created without any gap.
[0024]
For example, in FIG. 1, a pseudo unit cell 12a having a rectangular shape along the side L1 and a diagonal point Q1 on the side L2 is created with the vertex P1 of the outer frame 11 as a starting point. Next, a pseudo unit cell 12b having a rectangular shape along the side L2 and having a diagonal point Q2 of the point Q1 on the side L3 and a pseudo unit cell 12c having a diagonal point Q3 of the point Q2 on the side L4 are shown. create. Further, a pseudo unit cell 12d having a diagonal point Q4 of the point Q3 on the extension of the side L5, a pseudo unit cell 12e having a diagonal point Q5 of the point Q4 on the side L6, and a point Q6 of a diagonal point of the point Q5. Creates a pseudo unit cell 12f on the pseudo unit cell 12a.
[0025]
After the creation of the pseudo unit cells 12a to 12f, the analog circuit constituted by the analog macros 10a and 10b is treated as one unit cell represented by a set of the pseudo unit cells 12a to 12f (step S4). Thus, the shape of the analog circuit is represented by the coordinates of two diagonal points of the rectangle of each of the pseudo unit cells 12a to 12f. However, the expression data of the shape of the analog circuit is a set of coordinates of two diagonal points of the rectangle, and does not represent the shape by the coordinates of each vertex of the outer frame 11 of the polygon.
[0026]
Next, only the terminal described in the terminal information of the netlist is set as the terminal of this unit cell to be treated as one unit cell (step S5), and the terminal between this unit cell and another unit cell is set. To enable automatic wiring.
[0027]
For other similar analog circuits, the processing from step S1 to step S5 is performed as necessary, and the analog circuit is handled as one unit cell expressed by a set of pseudo unit cells. The automatic layout processing may be performed for digital circuits as needed.
[0028]
Hereinafter, the entire circuit is arranged by using the netlist and arranging the unit cells using the expression data of all the unit cells together with the expression data of the analog circuit represented by the set of coordinates of the pseudo unit cells 12a to 12f. Is performed to create layout information (step S6). Then, automatic placement and routing is performed based on the layout information (step S7).
[0029]
According to the automatic layout method described above, even when the analog circuit includes two analog macros 10a and 10b having different sizes, it is possible to suppress the generation of the unused area. Furthermore, since the shape of the analog circuit is expressed by a set of coordinates of two diagonal points of the rectangle of the pseudo unit cells 12a to 12f, the amount of data required for automatic arrangement does not significantly increase.
[0030]
Next, a second embodiment will be described.
FIG. 3 is a diagram for explaining an automatic layout method according to the second embodiment. In FIG. 3, the same elements as those shown in FIG. 1 are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0031]
In the second embodiment, as in the first embodiment, an analog circuit including two analog macros 10a and 10b having different sizes will be described, and the analog macro between the analog macros 10a and 10b having terminals formed at the edges and the like will be described. Is already connected.
[0032]
In the second embodiment, for such an analog circuit, first, an outer frame 11 is created, and two pseudo unit cells 20a and 20b are inscribed in the outer frame 11 and connected to each other without gaps. Is done. The pseudo unit cell 20a is mainly formed in the analog macro 10a, and the pseudo unit cell 20b is mainly formed in the analog macro 10b.
[0033]
The analog circuit composed of the analog macros 10a and 10b is treated as one unit cell expressed by a set of these pseudo unit cells 20a and 20b, and terminal information is created for this unit cell. The shape of the analog circuit is represented by a set of coordinates of two diagonal points of the pseudo unit cells 20a and 20b.
[0034]
The flow of the automatic layout processing according to the second embodiment will be described.
FIG. 4 is a flowchart of the automatic layout processing according to the second embodiment.
First, an analog circuit composed of two connected analog macros 10a and 10b is extracted from the netlist (step S10), and an outer frame 11 is created in the analog circuit (step S11). Next, two pseudo unit cells 20a and 20b inscribed in the outer frame 11 are created (step S12). The pseudo unit cells 20a and 20b are each represented by coordinates of two diagonal points of a rectangle, and are created by being connected to each other without gaps.
[0035]
After the creation of the pseudo unit cells 20a and 20b, the analog circuit constituted by the analog macros 10a and 10b is treated as one unit cell represented by a set of the pseudo unit cells 20a and 20b (step S13). However, as in the first embodiment, the expression data of the unit cell shape is a set of coordinates of two diagonal points of a rectangle.
[0036]
Next, only the terminal described in the terminal information of the netlist is set as a terminal of this unit cell treated as one unit cell (step S14). Finally, layout information for all unit cells is created using the netlist together with the unit cells (step S15), and automatic placement and routing is performed based on the layout information (step S16).
[0037]
The automatic layout method described in the second embodiment can also prevent the generation of an unused area. Furthermore, since the shape of this unit cell is represented by a set of coordinates of the two pseudo unit cells 20a and 20b, the amount of data representing the shape can be further reduced.
[0038]
Automatic layout of analog macros that are originally polygons other than quadrangles can be performed in the same manner.
FIG. 5 is a diagram for explaining an automatic layout method for an analog macro that is not originally a square. In FIG. 5, the same elements as those shown in FIG. 3 are denoted by the same reference numerals, and detailed description thereof will be omitted.
[0039]
In the case of the example of FIG. 5, an outer frame 11 surrounding one analog macro 30 having a terminal formed at an edge or the like is formed, and two pseudo unit cells 20a and 20b are inscribed in the outer frame 11. Are connected and created without any gaps. The analog macro 30 is treated as one unit cell represented by a set of pseudo unit cells 20a and 20b, and its shape is represented by a set of two diagonal coordinates of the pseudo unit cells 20a and 20b. .
[0040]
In this case, the flow of the automatic layout processing is the same as the flow shown in FIG. That is, first, the analog macro 30 is extracted from the net list (step S10), and the outer frame 11 is created (step S11). Next, two pseudo unit cells 20a and 20b inscribed in the outer frame 11 are created (step S12), and the analog macro 30 is treated as one unit cell represented by a set of the pseudo unit cells 20a and 20b (step S13). ). Thereafter, terminals are set for this unit cell (step S14), and layout information is created (step S15). Then, automatic placement and routing is performed based on the layout information (step S16).
[0041]
As described above, even for the analog macro 30 which is originally a polygon other than a quadrangle, it is possible to suppress the occurrence of the unused area and the data amount.
[0042]
As described above, an analog circuit is treated as one unit cell represented by a set of a plurality of connected pseudo unit cells inscribed in its outer frame, and its shape is expressed by a set of coordinates of each pseudo unit cell. To create layout information and perform automatic placement and routing. As a result, generation of an unused area can be suppressed, and the chip size of the LSI can be reduced.
[0043]
Further, in the creation of the pseudo unit cell, the conventional restriction that the unit cell is represented by coordinates of two diagonal points of a rectangle is not changed. Therefore, in expressing the shape of the analog circuit that suppresses the generation of the unused area, the data amount does not increase significantly, and the calculation amount required for the automatic layout is suppressed.
[0044]
Note that the circuit shape to which the automatic layout method of the present invention can be applied is not limited to a substantially L-shaped circuit such as the analog circuit described above, and the number of macros constituting the circuit is not limited to the above example. However, the present invention is not limited to this. This automatic layout method can be applied to circuits having various shapes such as a substantially concave shape and a substantially S-shaped shape, and creates an outer frame and a pseudo unit cell inscribed in the outer frame to form the first and second circuits. Automatic layout is possible as in the second embodiment.
[0045]
In creating a pseudo unit cell, a plurality of connected pseudo unit cells can be arranged in a tile shape to fill the outer frame.
Further, as described above, the above-described automatic layout processing is realized by a computer. In that case, the computer executes the program corresponding to the processing, thereby realizing the processing on the computer. Such a program can be recorded on a computer-readable recording medium. Computer-readable recording media include magnetic recording devices, optical disks, magneto-optical recording media, and semiconductor memories. The magnetic recording device includes a hard disk device (HDD), a flexible disk (FD), a magnetic tape, and the like. Examples of the optical disk include a DVD (Digital Versatile Disc), a DVD-RAM (Random Access Memory), a CD-ROM (Compact Disc Read Only Memory), and a CD-R (Recordable) / RW (ReWritable). The magneto-optical recording medium includes an MO (Magneto-Optical disk) and the like.
[0046]
When distributing the program, for example, portable recording media such as DVDs and CD-ROMs on which the program is recorded are sold. Alternatively, the program may be stored in a storage device of a server computer, and the program may be transferred from the server computer to another computer via a network.
[0047]
The computer that executes the program stores, for example, the program recorded on the portable recording medium or the program transferred from the server computer in its own storage device. Then, the computer reads the program from its own storage device and executes processing according to the program. The computer can also read the program directly from the portable recording medium and execute processing according to the program. Further, the computer may execute the processing according to the received program each time the program is transferred from the server computer.
[0048]
【The invention's effect】
As described above, according to the present invention, an outer frame is created in a shape corresponding to the shape of a circuit, a plurality of pseudo unit cells inscribed in the outer frame are connected and created, and the circuit is formed by a set of pseudo unit cells. Is treated as one unit cell represented by As a result, the generation of an unused area in the automatic layout can be suppressed, and the size of the LSI chip can be reduced.
[0049]
Further, since the shape of the circuit is expressed by expressing each pseudo unit cell by coordinates of two diagonal points of a rectangle, it is possible to suppress a remarkable increase in the amount of data and an accompanying increase in the amount of calculation.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining an automatic layout method according to a first embodiment.
FIG. 2 is a flowchart of an automatic layout process according to the first embodiment.
FIG. 3 is a diagram for explaining an automatic layout method according to a second embodiment.
FIG. 4 is a flowchart of an automatic layout process according to a second embodiment.
FIG. 5 is a diagram for explaining an automatic layout method for an analog macro that is not originally a square.
FIG. 6 is a diagram illustrating a method of expressing unit cells in automatic placement and routing.
FIG. 7 is a diagram illustrating a conventional expression method when expressing a unit cell including an analog circuit by automatic placement and routing.
[Explanation of symbols]
10a, 10b, 30 Analog macro 11 Outer frames 12a, 12b, 12c, 12d, 12e, 12f, 20a, 20b Pseudo unit cells L1, L2, L3, L4, L5, L6 Sides P1, P2, P3, P4, P5 P6 vertex Q1, Q2, Q3, Q4, Q5, Q6 point

Claims (7)

In an automatic layout method for automatically arranging and routing unit cells of an LSI,
Create an outer frame surrounding the circuit in a shape according to the shape of the circuit,
A plurality of pseudo unit cells inscribed in the outer frame are connected and created,
An automatic layout method, wherein the circuit is treated as one unit cell expressed by a set of the pseudo unit cells. When the plurality of pseudo unit cells inscribed in the outer frame are connected and created, the plurality of pseudo unit cells are created by connecting the square pseudo unit cells represented by coordinates of two diagonal points. Item 6. The automatic layout method according to Item 1. When creating the outer frame surrounding the circuit in a shape according to the shape of the circuit, the shape of the circuit is such that each side of the outer frame is a straight line and each vertex has an angle of 90 degrees. 2. The automatic layout method according to claim 1, wherein the outer frame surrounding the circuit is created in a corresponding shape. When creating by connecting a plurality of the pseudo unit cells inscribed in the outer frame, a closed circuit according to the shape of the outer frame by connecting the pseudo unit cells along each side of the outer frame. 2. The automatic layout method according to claim 1, wherein the automatic layout method is created so as to configure. The method according to claim 1, wherein, when the plurality of pseudo unit cells inscribed in the outer frame are connected to be created, the pseudo unit cells are connected so as to fill the inside of the outer frame. Automatic layout method. In a program for automatically arranging and wiring unit cells of an LSI,
On the computer,
Create an outer frame surrounding the circuit in a shape according to the shape of the circuit,
A plurality of pseudo unit cells inscribed in the outer frame are connected and created,
A program for executing processing for treating the circuit as one unit cell expressed by the set of the pseudo unit cells. In a computer-readable recording medium recording a program for automatically arranging and wiring unit cells of an LSI,
On the computer,
Create an outer frame surrounding the circuit in a shape according to the shape of the circuit,
A plurality of pseudo unit cells inscribed in the outer frame are connected and created,
A recording medium on which a program is recorded, wherein a process is performed for treating the circuit as one unit cell represented by the set of the pseudo unit cells.

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