JP2005322694A - Method for designing layout of semiconductor integrated circuit and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for designing layout in which required number of flip-flop cells for circuit correction can be secured regardless of the number of clock systems and without deteriorating clock skew of existing flip-flop cells and dummy flip-flop cells by suppressing increase in the number of gates due to addition of dummy cells as much as possible. <P>SOLUTION: In the image drawing, the semiconductor integrated circuit comprises clock systems CTS1, CTS2 and CTS3, cells 4, 8 and 11 connected with respective output lines 5, existing FFs 6, 9 and 12, and dummy cells 7, 10 and 13 connected with respective output lines 5. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit layout design method and manufacturing method, and more particularly to a standard cell type semiconductor integrated circuit design method and manufacturing method.

There are mainly two methods for designing a semiconductor integrated circuit such as an LSI (Large Scale Integrated Circuit). The first design method is called a gate array method, in which ground data in which basic cells (transistors corresponding to two-input NAND gates) are arranged in an array like a grid is prepared in advance. A function desired by the user is realized by arbitrarily performing wiring (upper ground) between the basic cells. In addition, since the manufacturing process only involves changing the wiring mask, the delivery time is short and the cost is low. The second design method is called a standard cell method. Since functional blocks are prepared in advance as some standard cells, transistors can be efficiently arranged and wired. As a result, a high-performance LSI meeting the user's wishes can be produced, but the development period is longer than that of the gate array system.
Further, when a circuit correction is performed with a standard cell type LSI, the cell must be re-arranged and wired each time, and the circuit correction cannot be easily performed. In other words, since the diffusion layer (base) and wiring layer (top) are integrated in the function cell created by the standard cell method, the addition of cells due to circuit modification is only for the wiring mask. Instead, all mask patterns are changed, which is a big problem in terms of cost and development period.
Therefore, as a means for overcoming the above-mentioned drawbacks, Japanese Patent Application Laid-Open No. 11-126823 discloses a method that has been widely known generally. This is a method in which cells that are not necessary for the original function (hereinafter referred to as dummy cells) are arranged in the chip in advance, and when there is a need for circuit correction, a desired function is realized using the dummy cells. is there. In this case, it is only necessary to change the wiring so that a dummy cell is used, so there is no need to redo all the work as in the conventional standard cell method, and the circuit can be corrected with a short delivery time and low cost like the gate array method. It becomes.
The design flow using dummy cells will be briefly described below. First, the user prepares a net list in which the necessary number and type of dummy cells are added in advance to the logic function block that may require circuit correction. In the layout process, first, macro cells (including dummy cells) and mega cells such as RAM, ROM, and CPU are arranged based on the information of the net list. Next, clock tree synthesis processing (details will be described later) is performed. Since the arrangement of the cells necessary for the circuit has been completed so far, wiring between the cells is finally performed. All that remains is to output the layout data and netlist based on the placement and routing information. When it is necessary to correct the circuit after the layout is completed, a layout device is used by directly correcting the layout data and using a technique called ECO (Engineering Change Order) by creating a netlist reflecting the circuit correction. The circuit is corrected by any one of the methods for changing the layout.
JP-A-11-126823

The first problem in the conventional standard cell system is that too many dummy cells may be inserted to fit within the desired chip size. This problem can be avoided by reducing the number of dummy cells and performing the layout again, but the problem that the layout construction period becomes longer remains. In addition, since the determination of how many dummy cells can be reduced depends on human feeling, there is a possibility of repetition.
The second problem is that when the flip-flop cell is actually used for circuit correction, if the clock skew with the existing flip-flop cell is not matched, the timing adjustment with the existing flip-flop cell becomes complicated. It is easy to use it. This problem can be avoided by connecting dummy flip-flop cells to all clock systems that may require circuit correction in advance and adjusting the clock skew together with the existing flip-flop cells by clock tree synthesis. FIG. 4 shows an image diagram of a conventional clock tree. In the example of FIG. 4, since there are three clock systems CTS1, CTS2, and CTS3, it is necessary to connect a dummy flip-flop cell 21 in addition to the existing flip-flop cell 20.

The third problem is that in the workaround for the second problem, as the number of clock systems increases, a larger number of dummy flip-flop cells 21 must be added, resulting in the first problem. It is. For this reason, in order to reduce the total number of dummy flip-flop cells 21 to be added, the number put in each clock system may be reduced, or may not be included in the clock system determined to have a low possibility of circuit correction. Conceivable. As a result, there may be a shortage of dummy flip-flop cells with matching clock skew that can be used when an unexpected circuit correction actually occurs, or there may be no dummy flip-flop cells. In this case, the only option is to use a dummy flip-flop cell of another clock system that does not match the clock skew, accepting that the layout is redone again at the expense of the construction period or that time adjustment is required.
In view of such problems, the present invention suppresses an increase in the number of gates due to the addition of dummy cells as much as possible, does not deteriorate the clock skew of the existing flip-flop cells and the dummy flip-flop cells, and does not depend on the number of clock systems. An object of the present invention is to provide a layout design method capable of securing the number of flip-flop cells necessary for correction.

In order to solve such a problem, the present invention provides a layout design method for a semiconductor integrated circuit based on a standard cell system in which functional blocks are prepared in advance as a plurality of standard cells, and includes a clock for a flip-flop cell. A dummy dummy cell which is a macro cell having an input gate capacitance equivalent to the input gate capacitance of the input pin is provided, and the clock dummy synthesis is performed by connecting the dummy dummy cell instead of the dummy flip-flop cell, and then the flip-flop When circuit correction including addition of a pcell is required, the dummy dummy cell connected to the circuit correction portion is replaced with a flip-flop cell.
In the standard cell system semiconductor integrated circuit layout design method, a dummy flip-flop cell is usually provided in advance, assuming that a design change occurs due to circuit correction. However, many dummy cells cannot be provided because of the circuit scale. Therefore, in the present invention, a dummy dummy cell having an input gate capacity equivalent to the clock input pin of the flip-flop cell is connected to the same circuit as the clock input pin to perform clock tree synthesis, and circuit correction including addition of the flip-flop cell is necessary. In this case, the dummy dummy cell is replaced with a flip-flop cell.
Here, the clock tree synthesis means that a buffer tree is formed in the clock signal, and not only the flip-flop cells necessary for the original function but also dummy dummy cells, the buffers are arranged at optimal locations so that the clock skew is matched. Say that.
According to a second aspect of the present invention, the dummy dummy cell has a width equivalent to an inverter cell formed by an integral multiple of one grid.
In the present invention, first, a dummy dummy cell having an input gate capacitance equivalent to the clock input pin of the flip-flop cell is prepared. A smaller dummy dummy cell size (area) is advantageous because an increase in the number of gates can be suppressed. Usually, the heights of standard cell type macro cells are all the same. The horizontal width is managed in a basic unit called a grid, and each macro cell is created with a width that is an integral multiple of one grid. Therefore, the dummy dummy cell may have a structure equivalent to the inverter cell which is the smallest macro cell.

According to a third aspect of the present invention, when the semiconductor integrated circuit requires a plurality of clock systems, the dummy dummy cells are arranged in each clock system.
If a sufficient number of dummy dummy cells are connected to each clock system in advance, the number of flip-flop cells necessary for circuit correction can be secured regardless of the number of clock systems.
According to a fourth aspect of the present invention, there is provided a layout design method for a semiconductor integrated circuit using a standard cell system in which functional blocks are prepared in advance as a plurality of standard cells, and an input equivalent to an input gate capacitance of a clock input pin of a flip-flop cell. A dummy dummy cell having a gate capacitance and a dummy flip-flop cell are provided, and the dummy flip-flop cell is arranged in the vicinity of the dummy dummy cell in advance, and then metal revision including the addition of the flip-flop cell is required. In this case, the wiring to the dummy dummy cell in the vicinity of the circuit requiring circuit correction is cut, and the dummy flip-flop cell arranged in the vicinity of the dummy dummy cell is connected instead of the dummy dummy cell. Features.
In the metal revision, cells cannot be added or deleted. Therefore, considering the metal revision, it is absolutely necessary to lay out the dummy flip-flop cells in advance. Therefore, according to the present invention, dummy dummy cells of each clock system are fixedly arranged at the time of initial layout, and further, dummy flip-flop cells are arranged in the vicinity thereof.
A fifth aspect of the present invention relates to a method of manufacturing a semiconductor integrated circuit using a standard cell system in which functional blocks are prepared in advance as a plurality of standard cells, and an input gate equivalent to an input gate capacitance of a clock input pin of a flip-flop cell When a macro cell having a capacity is provided, clock macro synthesis is performed by connecting the macro cell instead of the dummy flip-flop cell, and then the circuit correction including the addition of the flip-flop cell is necessary, the circuit correction is performed. The macro cell connected to the portion is replaced with a flip-flop cell.
According to this invention, there exists an effect similar to Claim 1.

A sixth aspect of the present invention is characterized in that the dummy dummy cell has a structure equivalent in width to an inverter cell formed by an integral multiple of one grid.
According to this invention, there exists an effect similar to Claim 2.
According to a seventh aspect of the present invention, when the semiconductor integrated circuit requires a plurality of clock systems, the macro cells are respectively arranged in the clock systems.
According to this invention, there exists an effect similar to Claim 3.
Claim 8 is a method of manufacturing a semiconductor integrated circuit by a standard cell system in which functional blocks are prepared in advance as a plurality of standard cells, and an input gate equivalent to an input gate capacitance of a clock input pin of a flip-flop cell A macro cell having a capacity and a dummy flip-flop cell, and the dummy flip-flop cell is disposed in the vicinity of the macro cell in advance, and then a metal revision including the addition of the flip-flop cell is required. It is characterized in that wiring to a macro cell in the vicinity of a circuit that requires correction is cut and a dummy flip-flop cell arranged in the vicinity of the macro cell is connected instead of the macro cell.
According to this invention, there exists an effect similar to Claim 4.

According to the first and fifth aspects of the present invention, the dummy dummy cell having the input gate capacitance equivalent to the input gate capacitance of the clock input pin of the flip-flop cell is provided, and the dummy dummy cell is the same as the clock input pin instead of the dummy flip-flop cell. When the circuit modification including the addition of the flip-flop cell is necessary after that, the dummy dummy cell can be replaced with the flip-flop cell, so that the original clock skew is deteriorated. It is possible to add a flip-flop cell necessary for circuit correction without making it.
In the second and sixth aspects, since the width of the dummy dummy cell has a structure equivalent to that of an inverter cell formed by an integral multiple of one grid, the size of the grid can be greatly reduced by one cell.
Further, in the third and seventh aspects, when the semiconductor integrated circuit requires a plurality of clock systems, dummy dummy cells are arranged in each clock system, so that it is necessary for circuit correction regardless of the number of clock systems. A number of flip-flop cells can be secured.
According to the fourth and eighth aspects of the present invention, the dummy dummy cells of each clock system are preliminarily arranged and arranged in advance, a dummy flip-flop cell is arranged in the vicinity of the macro cell, and then the metal including the addition of the flip-flop cell is included. When revision is necessary, the wiring to the dummy dummy cell in the vicinity of the circuit requiring the circuit correction is cut, and the dummy flip-flop cell arranged in the vicinity of the dummy dummy cell is connected instead of the dummy dummy cell. As a result, the dummy dummy cell can be switched to the dummy flip-flop cell without significantly changing the wiring length, and the dummy flip-flop cell can be used with minimal influence on the clock skew. It becomes possible.

Hereinafter, the present invention will be described in detail with reference to embodiments shown in the drawings. However, the components, types, combinations, shapes, relative arrangements, and the like described in this embodiment are merely illustrative examples and not intended to limit the scope of the present invention only unless otherwise specified. .
First, before describing embodiments of the present invention, portions common to each embodiment will be described below. First, a dummy dummy cell having an input gate capacitance equivalent to the clock input pin of the flip-flop cell is prepared. A smaller dummy dummy cell size (area) is advantageous because an increase in the number of gates can be suppressed. Usually, the heights of standard cell type macro cells are all the same. The size of the horizontal width is managed in a basic unit called a grid, and each macro cell is created with a width that is an integral multiple of one grid. Therefore, the dummy dummy cell may have a structure equivalent to the inverter cell which is the smallest macro cell. FIG. 3 is a diagram comparing the size of each cell based on a certain technology library in order to relatively compare the size of each cell. In FIG. 3, the FF 32 with an asynchronous set and reset, which is normally used as a flip-flop cell for dummy, is 35 grids, whereas the dummy dummy cell 30 is 3 grids like the inverter cell 31, so The cell can reduce the size of 32 grids.

Instead of the conventional flip-flop cell for dummy, the user creates a netlist in which the dummy dummy cell is connected to a clock signal that is the basis of clock tree synthesis (hereinafter referred to as CTS). In the layout process, CTS is executed based on the information of the net list. A buffer tree is formed in the clock signal by the CTS, and not only the flip-flop cells necessary for the original function but also the dummy dummy cells, the buffers are arranged at optimal locations so that the clock skew is matched.
In the embodiment described below, it is assumed that circuit correction including addition of flip-flops is required after the layout process is completed. In the first embodiment, not only the mask for wiring but all the mask patterns are displayed even when the addition or deletion of cells is possible during the development of the chip, or the revision after the completion of the chip. It is assumed that it can be changed. In the second embodiment, it is assumed that only the wiring mask can be changed by revision after the completion of the chip (hereinafter referred to as metal revision).

FIG. 1 is an image diagram of a clock tree according to the first embodiment of the present invention. In this image diagram, the clock systems CTS1, CTS2, and CTS3, the cells 4, 8, and 11 connected to the respective output lines, the existing FFs 6, 9, and 12 connected to the respective output lines 5, and the output lines as well. And dummy dummy cells 7, 10, 13 connected to 5.
When circuit correction including addition of flip-flop cells is required, the user first selects a dummy dummy cell connected to a desired clock system arranged in the vicinity of the circuit requiring circuit correction by looking at the layout. Next, correction is performed to replace the selected dummy dummy cell with a flip-flop cell for the netlist after layout. Of course, other circuit modifications are made here. Next, the modified netlist is read into the layout device and ECO (Engineering Change Order) is executed. At this time, a flip-flop cell to be replaced with the original dummy dummy cell position is arranged. This is done automatically by the layout device by keeping the instance name the same. Since the small cells in the grid are replaced with the large cells in the grid here, it is natural that there is no space to place the flip-flop cells, but the layout device automatically places the flip-flop cells by slightly shifting the surrounding cells and wiring. Give me.
For example, if the existing FF 6 circuit connected to the output line 5 of the cell 4 of the CTS 1 in FIG. 1 needs to be modified including the addition of flip-flop cells, a plurality of dummy dummy cells 7 are selected by looking at the layout. . Next, a modification is made to replace the selected dummy dummy cell 7 with the flip-flop cell 14 for the netlist after the layout. By arranging the flip-flop cell 14 at the same position as the dummy dummy cell 7 in this way, the cell can be replaced without changing the wiring length from the cell 4 in the previous stage. Further, the input gate capacities of the dummy dummy cell 7 and the flip-flop cell 14 are made to be the same as described above. Accordingly, since the total load capacity added to the cell 4 in the previous stage does not change at all, it is possible to prepare a flip-flop cell necessary for circuit correction without deteriorating the original clock skew.
In addition, regarding the size, in the present embodiment, since the dummy dummy cells are replaced by flip-flop cells as many times as necessary after the circuit correction is decided, unnecessary flip-flop cells do not need to be arranged in advance, and the advantage for that. Is born. However, if a large-scale circuit modification that requires all dummy dummy cells added in advance to be replaced with flip-flop cells is performed, the advantage will be lost because it becomes exactly the same as the conventional method. .
Further, the problem of securing the number of flip-flop cells necessary for circuit correction regardless of the number of clock systems is to connect a sufficient number of dummy dummy cells 7, 10, 13 to each clock system CTS1 to CTS3. Can be achieved.

FIG. 2 is an image diagram of a layout according to the second embodiment of the present invention. In this image diagram, clock systems CTS1, CTS2, CTS3, cells 45, 46, 48 connected to the respective output lines, and existing dummy dummy cells 40, 41, 42 connected to the respective output lines 44, 47, 49 are shown. And a dummy FF 43 adjacent thereto. Since addition and deletion of cells are impossible in the metal revision, it is absolutely necessary to lay out a dummy flip-flop cell in advance in consideration of the metal revision. Therefore, as shown in FIG. 2 in the first layout, dummy dummy cells 40, 41, and 42 of each clock system are fixed and arranged, and further, dummy flip-flop cells 43 are arranged and arranged in the vicinity thereof. Here, the logic level of the input pin of the dummy flip-flop 43 may be fixed to “0” or “1”. When a metal revision including the addition of a flip-flop cell is required, the user first lays out a dummy dummy cell connected to a desired clock system arranged in the vicinity of the circuit requiring circuit correction and a dummy flip-flop cell. To choose from. Next, the netlist after the layout is corrected by cutting the wiring to the dummy dummy cell and connecting the flip-flop cell instead. Of course, other circuit modifications are made here.
For example, the dummy dummy cell 40 connected to the output line 44 of the cell 45 of the CTS 1 in FIG. 2 and the dummy flip-flop cell 43 are selected by looking at the layout. Next, for the netlist after layout, the wiring 44 to the dummy dummy cell 40 is cut, and the dummy flip-flop cell 43 is connected instead.

Next, the modified netlist is read by the layout device and ECO is executed. Here, unlike the case of the first embodiment, since the wiring length to the dummy flip-flop cell after switching to the wiring length to the first dummy dummy cell cannot be made exactly the same, the clock skew is adversely affected. However, since the dummy dummy cell and the dummy flip-flop cell are originally arranged in the vicinity, the influence on the clock skew can be minimized.
In terms of size, the advantage is less than that of the first embodiment because a dummy flip-flop cell must be arranged in advance, but it is not included in each clock system as in the prior art. Because there is no, there is an advantage for that. In addition, regardless of the number of clock systems, the problem of securing the required number of flip-flop cells for circuit correction is to connect a sufficient number of dummy dummy cells to each clock system in advance and a sufficient number of dummy cells. This can be achieved by arranging flip-flop cells.
It goes without saying that a standard cell type semiconductor integrated circuit can be manufactured by the layout design method of this embodiment.

It is an image figure of the clock tree which concerns on the 1st Embodiment of this invention. It is an image figure of the layout which concerns on the 2nd Embodiment of this invention. It is the figure which compared the size of each cell based on a certain technology library, in order to compare the size of each cell relatively. It is an image figure of the clock tree of a prior art.

Explanation of symbols

  1, 2, 3 Clock system CTS 4, 8, 11 cells, 5 output lines, 6, 9, 12 Existing FF, 7, 10, 13 Dummy dummy cells

Claims (8)

A layout design method for a semiconductor integrated circuit by a standard cell system in which functional blocks are prepared as a plurality of standard cells in advance,
A dummy dummy cell that is a macro cell having an input gate capacitance equivalent to an input gate capacitance of a clock input pin of the flip-flop cell;
The dummy dummy cell is connected in place of the dummy flip-flop cell and clock tree synthesis is performed. After that, when a circuit correction including the addition of the flip-flop cell is necessary, it is connected to the circuit correction portion. A layout design method of a semiconductor integrated circuit, wherein the dummy dummy cell is replaced with a flip-flop cell.   2. The layout design method of a semiconductor integrated circuit according to claim 1, wherein the dummy dummy cell has a width equivalent to an inverter cell formed by an integral multiple of one grid.   3. The layout design method for a semiconductor integrated circuit according to claim 1, wherein when the semiconductor integrated circuit requires a plurality of clock systems, the dummy dummy cells are arranged in each clock system. A layout design method for a semiconductor integrated circuit by a standard cell system in which functional blocks are prepared as a plurality of standard cells in advance,
A dummy dummy cell having an input gate capacitance equivalent to the input gate capacitance of the clock input pin of the flip-flop cell, and a dummy flip-flop cell;
When the dummy flip-flop cell is disposed in the vicinity of the dummy dummy cell in advance and then a metal revision including the addition of the flip-flop cell is required, the dummy dummy cell in the vicinity of the circuit requiring circuit correction is placed on the dummy dummy cell. A layout design method for a semiconductor integrated circuit, wherein wiring is cut and a dummy flip-flop cell arranged in the vicinity of the dummy dummy cell is connected instead of the dummy dummy cell. A method of manufacturing a semiconductor integrated circuit by a standard cell method in which functional blocks are prepared in advance as a plurality of standard cells,
A dummy dummy cell having an input gate capacitance equivalent to the input gate capacitance of the clock input pin of the flip-flop cell;
When the macro cell is connected instead of the dummy flip-flop cell and clock tree synthesis is performed, and then a circuit correction including the addition of the flip-flop cell is necessary, the circuit connected to the circuit correction portion is connected. A method of manufacturing a semiconductor integrated circuit, wherein a dummy dummy cell is replaced with a flip-flop cell.   6. The method of manufacturing a semiconductor integrated circuit according to claim 5, wherein the width of the dummy dummy cell has a structure equivalent to an inverter cell formed by an integral multiple of one grid.   7. The method of manufacturing a semiconductor integrated circuit according to claim 5, wherein when the semiconductor integrated circuit requires a plurality of clock systems, the dummy dummy cells are arranged in each clock system. A method of manufacturing a semiconductor integrated circuit by a standard cell method in which functional blocks are prepared in advance as a plurality of standard cells,
A dummy dummy cell having an input gate capacitance equivalent to the input gate capacitance of the clock input pin of the flip-flop cell, and a dummy flip-flop cell;
When the dummy flip-flop cell is disposed in the vicinity of the dummy dummy cell in advance, and then metal revision including the addition of the flip-flop cell is required, wiring to the dummy dummy cell in the vicinity of the circuit requiring circuit correction And a dummy flip-flop cell arranged in the vicinity of the dummy dummy cell is connected instead of the dummy dummy cell.

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