JP2005123537A - Semiconductor device and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To obtain an effect of timing improvement more than only an addition of repeater upon designing a layout. <P>SOLUTION: When supposing an united construction of eight of two input AND gates and one of eight input OR gates as a macro connection multi input complex cell, if being out of accord with the invention, the whole multi input complex cell 41 is positioned in a standard cell location area as shown in Figure (A). However, if being in accord with the invention, the whole multi input complex cell 41 is not positioned in the standard cell location area as shown in Figure (B). For example, four of two input AND gates are separately positioned between the macros, and the remainder includes four of two input AND gates, one of four input OR gates, one of three input OR gates, and one of two input OR gates, and they are positioned in the standard cell location area. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device including a plurality of macros, and in particular, a semiconductor device in which a macro-connected first-stage cell among macro-connected cells decomposed into simple cells of three inputs or less is arranged between macros as a repeater, and It relates to a manufacturing method.

  In the conventional layout design, when improving the path timing of a macro (a large-scale functional block such as a RAM) and a multi-input composite cell connected to the macro, the timing is improved by the arrangement of the connected cells.

Incidentally, in Patent Document 1, when a layout is generated while hierarchically generating blocks, a part of logic cells in a lower-layer lower functional block are temporarily arranged, and lower-layer functional blocks are assembled to an upper layer. An automatic placement and routing method for layout design that optimizes temporary placement logic cells when generating hierarchical functional blocks is disclosed. Further, in Patent Document 2, logic cells that are close to the input terminal and output terminal of the group and are related to the critical path are arranged in an outer divided region, and a logic cell having a large number of stages from the input terminal and the output terminal is more By being arranged in the inner divided area, automatic arrangement reflecting the circuit configuration is possible.
JP-A-9-199598 JP 2001-68551 A

  However, if the connection cells are arranged as they are between the plurality of macros, it is necessary to give a margin to the macro interval, which causes a large expansion of the plurality of macro group areas, resulting in an increase in chip size. was there. If the macros are narrowed to suppress the increase in chip size, the multi-input composite cells cannot be arranged in the gap, and are arranged away from the connection macro pins. In this case, the delay as a total path has been improved by inserting a repeater buffer to improve the path delay, but it is only an improvement in the direction of simply adding the number of logical stages of the cell, and higher. A method of improvement level is required.

  In addition, there were cases where it was determined that it would be better to disassemble the multi-input composite cell in terms of timing, but the macro interval remains fixed for the purpose of simple speed improvement and placement congestion improvement. The effect was not improved. Furthermore, there is a method in which a multi-input composite cell is not used at the stage of creating a net first, but whether or not a multi-input composite cell is used is set at the initial net generation stage regardless of the cell arrangement. Therefore, the request to use it in a place where it can be placed could not be satisfied.

  It is an object of the present invention to obtain a timing improvement effect more than just adding a repeater without performing a trial and error of macro interval adjustment many times and without greatly increasing a plurality of macro intervals. Another object of the present invention is to provide a semiconductor device having a layout design and a method for manufacturing the semiconductor device.

  The semiconductor device according to the present invention includes a plurality of macros. However, as a part of improving the macro boundary timing at the time of layout design, the semiconductor device has a plurality of macro connection multi-layers decomposed into at least three simple cells or less. Of the input composite cells, the cell in the first stage of macro connection is configured as a repeater between the macros.

  Macro-connected multi-input composite cells, that is, multi-input composite cells connected to a macro, are not arranged between macros as they are, but are decomposed into simple cells of three inputs or less and Since the first cell connected to the macro, in other words, only the first cell connected to the macro is arranged between the macros as a repeater, the macro interval adjustment is not repeated many times and the timing is improved. In this case, the timing improvement effect can be obtained more than simply adding a repeater without increasing the interval between macros.

  The layout is designed so that the timing improvement effect can be obtained more than just adding repeaters, without adjusting the macro interval many times and without improving the timing of multiple macro intervals. And a method for manufacturing the semiconductor device.

Hereinafter, an embodiment of the present invention will be described with reference to FIGS. 1 to 5. Prior to specific description thereof, an outline of a layout design according to the present invention will be described as follows.
That is, in the layout of a semiconductor device including a plurality of macros, the plurality of macros are arranged in a packed state while ensuring a level at which repeater cells can be inserted between the macros to improve path timing. Further, at the path timing before the layout of the net, the influence of the macro boundary timing can be determined before the layout by multiplying the delay of the cell connected to the macro and the macro by a coefficient. Therefore, if necessary, the multi-input composite cell connected to the macro is disassembled into simple cells of 3 inputs or less, and only the first simple cell connected to the macro is inserted between the macros as a repeater. By doing so, the macro-to-macro is not greatly expanded, and a large timing improvement effect can be obtained as compared with the simple buffer insertion.

  Further, a general layout process considered to be most desirable in the processing order will be described. FIG. 5 shows an outline processing flow. In this case, first, the cells are simply arranged, and the process for setting the setup condition to be converged with zero clock delay is performed (process 51). In this phase, the buffer is inserted to increase the cell drive capability and the fanout and transition constraints are satisfied, so that the estimated wiring distance is short and the necessary wiring area is secured when not wired. In addition, the arrangement is performed in consideration of the degree of congestion.

  Next, in the phase in which the clock tree is set, processing is performed so that constraints such as phase delay and skew are satisfied (processing 52). Incidentally, (clock tree) phase delay refers to the total delay from the clock source to the end, although the tree is constructed so that the clock delay from the clock source to the end becomes an appropriate value. .

  The subsequent phase is a phase for converging hold violation, and adjustment of the clock tree, insertion of a buffer into the data line, and the like are performed (processing 53). After the various timing constraints are satisfied as described above, DRC (DRC: design rule check), LVS (LVS: layout versus schematic), and timing verification are performed as a layout design stage (process 54). ). Thus, there are several phases as described above for timing convergence, and changes are made to the initial arrangement for each phase.

Now, the present invention will be described in detail. FIG. 1 shows a processing flow in an example of layout design according to the present invention. In this case, first, the repeater insertion interval is manually designated from the process, library, etc. to be used, and the relative positional relationship between the plurality of macros is designated (processing 101, 102). After that, the area of the entire macro group for which the relative positional relationship is specified is specified separately from the normal cell placement area and is set as a normal cell placement prohibition area. A port position of an area for connecting a normal cell is set (process 103). This prevents the wiring from detouring from an unintended direction.
The size margin at the boundary between the macro group area and the normal cell arrangement area is estimated at an appropriate ratio from the number of macro ports.

Thereafter, the network analysis phase is started, and a tag indicating the plurality of macros is attached to a cell connected to the plurality of macros (process 104). Specifically, for example, as shown in FIG. 1 and Macro 2) 21 and 22 exist, and the output signals from these macros 21 and 22 are respectively two-input cells (cells) as shown in FIG. o1) Assuming the case of being input to 23, the tags attached to the cell 23 are set with M1 and M2 indicating the macros 21 and 22, respectively.

  After a cell is tagged, the correspondence between the net name to which the cell and the macro are connected and the area port name is searched, and the coordinates relative to the area port with respect to the initial macro layout are used. Further, the number of repeater (repeater buffer) insertions (including the case where the number of insertions is zero) is determined by coordinate calculation based on a comparison between the calculated value and the initially set repeater insertion interval (processing 105). ). As a result of the determination, the number of insertions may be determined to be zero (processing 106).

  Next, given the path timing (path speed, delay) in the ideal state before the layout, the delay of the tagged cell and the connected macro in the given path timing is multiplied by a specific coefficient, and the macro It is estimated how the connection timing path changes, and it is determined whether or not the set value is exceeded (processes 107 and 108). If it is determined in this determination that the set value is not exceeded, a repeater buffer is inserted as necessary as in the conventional processing (processing 109). However, when it is determined that the set value is exceeded, the process according to the present invention is performed for the first time. For example, when the output delay of a macro and the delay of a connected cell are doubled as an example, if the path delay of that part becomes the worst in the whole, it is necessary to pay attention to the path even after layout In the pre-layout stage, the portion is set as a processing target location according to the present invention. On the other hand, even after multiplying by the coefficient, if the worst path group is not obtained, it is not a target of processing according to the present invention, and is a point where there is no problem even in the conventional processing.

  As described above, cells to be processed are narrowed down in order to finally suppress an increase in the area of the macro region. When cells connected to a plurality of macros have greatly different path timings depending on the macro, the arrangement relationship with a specific macro may be a problem, and there may be no problem with other macros. In order to distinguish such a situation, a tag based on timing priority is added in addition to the connection macro tag described above (process 110). That is, for a multi-input composite cell connected to a macro, in addition to a connection macro tag indicating which macro is connected, a connection path to any of these macros is severe in terms of timing. Or for each connected macro, information on the order of strict timing is set as the contents of the tag by priority.

  Thereafter, the tagged multi-input composite cell is decomposed under a predetermined rule (process 111). As an example of the rule, the multi-input composite cells 301, 311, 321, and 331 shown in FIGS. 3A to 3D are cells having three or less inputs connected to the macro output side (preferably Is decomposed so that it becomes 2 input cells). Incidentally, the multi-input composite cell (consisting of two two-input AND gates and one two-input OR gate) 301 shown in FIG. 3A is composed of two elements, a two-input AND gate 302 and a two-input AND gate 303. , OR gate 304 is disassembled. A multi-input composite cell (4-input 1-output selector (selection control signal lines for 2 bits not shown)) 311 shown in FIG. 3B includes a 3-input 2-input 1-output selector (for 1 bit). 3, a 2-input 1-output selector (a 1-bit selection control signal line is not shown) 313, a 2-input 1-output selector (a 1-bit selection control signal line is not shown) 314 Is broken down into

  Further, the multi-input composite cell (4-input OR gate) 321 shown in FIG. 3C is broken down into three elements, a 2-input OR gate 322, a 2-input OR gate 323, and a 2-input OR gate 324. Furthermore, the multi-input composite cell (consisting of two two-input AND gates and one two-input OR gate) 331 shown in FIG. 3D is composed of a high-priority two-input AND gate 332 and a low-priority timing. The three-input composite gate (integrated configuration of one 2-input AND gate and one 2-input OR gate) 333 is decomposed. As described above, the cells connected to the macro output side are disassembled as cells having 3 inputs or less. The reason why the cells are disassembled into cells having 3 inputs or less in this way is to increase their drive capability and This is because if the arrangement is made in the macro group area instead, an increase in the arrangement wiring area can be suppressed. As a result, the area increases as compared with insertion as a repeater of a buffer which is a one-input cell, but it is clear that it does not increase greatly.

  Now, returning to FIG. 1 again and continuing the description, the multi-input composite cell has been decomposed as described above. Of the decomposed cells, cells connected to the macro are re-tagged. (Process 112). When the tag is re-attached, a tag relating to two macros may be attached to the 2-input 1-output selector, but usually a tag relating to one macro is attached to one cell. In addition, when tags related to two macros are attached and only one of them has a high priority in terms of timing, only the high priority part is shown as shown in FIG. It is possible to be separated from others and leave the rest as a composite gate state.

  Thereafter, regarding the difference between the final tagged cell count and the initially estimated repeater insertion count, the repeater buffer is inserted, and the macro interval is determined from the repeater count, the tagged cell size, and the wiring count ( Process 113). Next, the macros in the macro group area are moved outward so that the estimated macro interval is the same, but at this time, the size variable area on the outermost side of the area is removed, so that the macro group area Is not enlarged (process 114). In this way, after moving the macro, a tagged cell is placed between the macro group region port and the macro port with respect to the final position, but the placement position is from the macro position toward the macro group port. Are inserted at positions within the designated repeater insertion interval (process 115). In the case of a 2-input 1-output selector connected to two macros, the position within the repeater insertion interval from the macro far from the macro group area port to the macro group area port in the relationship between the two macros and the macro group port Placed in.

  The processing flow for layout design according to the present invention has been described above. Here, FIG. 4A shows a layout design result not according to the present invention, and FIG. 4B shows a layout design result according to the present invention. As shown in FIG. 4A, in this example, an integrated configuration of eight 2-input AND gates and one 8-input OR gate is assumed as a multi-input composite cell connected to a macro. However, if the present invention is not according to the present invention, it can be seen that the entire multi-input composite cell is located in the standard cell layout area. However, according to the present invention, the entire multi-input composite cell is not placed in the normal cell arrangement region, and the four 2-input AND gates are distributed as macros between the macros as repeaters, but the rest are four It is arranged in the normal cell arrangement area as a 2-input AND gate, one 4-input OR gate, one 3-input OR gate, and one 2-input OR gate.

  With the above processing, a multi-input composite cell with a large delay and low layoutability is decomposed into a cell with simple three inputs or less and other cells, particularly at a macro boundary, and a cell with simple three inputs or less is used instead of a repeater. By decomposing the delay of the multi-input composite cell that originally existed on the net, and sharing a part of the delay with the repeater addition part, the delay improvement effect is greater than the method by simple buffer addition Will be obtained. In addition, this method decomposes multi-input composite cells around macros with strict timing, so that the decomposed cells other than the repeater are usually placed in the cell placement area. Even if it is arranged in the vicinity, layoutability is improved by being disassembled to a size smaller than the original size. Furthermore, since the macro interval is adjusted by estimating the timing of the macro portion before layout, estimating the decomposition of multi-input composite cells, and estimating the arrangement position of the connected cells of the decomposed cells, time loss due to trial and error of the layout of the macro portion is improved. It will be.

  As described above, to summarize the effect of the present invention, unlike the simple repeater insertion, the influence on the worst path of the multi-input composite cell around the existing macro is determined before the layout. By disassembling a multi-input composite cell and inserting a simple three-input cell or less obtained by this decomposition into the macro group region as a repeater, while suppressing the increase in gaps between macros, the worst path involving macros Rather than simply adding a repeater buffer, the cell delay can be accelerated by the cell decomposition effect. Also, by disassembling the multi-input composite cells around the worst path entangled macro, the layout around the macro is improved and the increase in the degree of congestion can be easily suppressed.

  As mentioned above, the invention made by the present inventor has been specifically described based on the embodiment. However, the present invention is not limited to the embodiment described above, and various modifications can be made without departing from the scope of the invention. Needless to say.

It is a figure which shows the processing flow in an example of the layout design which concerns on this invention. It is a figure for demonstrating assignment | providing of the tag to the cell connected with a some macro. It is a figure which shows the example of a decomposition | disassembly process of a multi-input composite cell. It is a figure which shows the contrast of the layout design result which is not based on this invention, and that by this invention. It is a figure which shows the general | schematic process flow of the general layout process considered to be the most desirable.

Explanation of symbols

  41,301,311,321,331 ... multiple input composite cells

Claims (4)

A semiconductor device including a plurality of macros,
As part of improving macro boundary timing during layout design, at least one macro-connected multi-input composite cell decomposed into simple cells with 3 inputs or less is placed between the macros as a repeater. A semiconductor device. A semiconductor device including a plurality of macros manufactured through a layout design in which circuit arrangement and wiring are performed by a computer based on circuit information,
At least giving the repeater insertion interval from the process to be used, the library,
A step of setting a stepwise size variable region in a placement prohibition region other than a specific cell adjacent to the macro boundary and outside the macro boundary;
Attaching a tag for connection macro identification to a cell connected to the macro;
Providing path timing information before placement;
Multiplying a cell to which the tag is attached with respect to the timing information and a macro connected to the cell by a set multiplier to estimate an influence of a layout change around the macro on a path timing before the layout; and ,
Decomposing the cell with the tag from the estimate into simple cells with 3 or fewer inputs;
Including the disassembled macro-connected first-stage cell and the cells necessary for the design rule check repeater in addition to the cell, and estimating the number of cells inserted and the insertion position in the macro group region;
In order to expand the related macro interval by the number of inserted cells and the insertion position, the step of cutting the outer margin in the macro group region and moving the macro outward,
And a step of arranging the disassembled macro-connected first stage cell as a repeater between macros vacated by the movement of the macro, and being manufactured through a layout design for improving macro boundary timing. Semiconductor device. A method of manufacturing a semiconductor device including a plurality of macros,
As part of macro boundary timing improvement, at least macro connected multi-input composite cells decomposed into simple cells of 3 inputs or less, the macro connected first stage cell is placed between macros as a repeater, improving macro boundary timing A method of manufacturing a semiconductor device manufactured through a layout design for a semiconductor device. A method for manufacturing a semiconductor device including a plurality of macros, which is manufactured through a layout design in which circuit arrangement and wiring are performed by a computer based on circuit information,
At least giving the repeater insertion interval from the process to be used, the library,
A step of setting a stepwise size variable region in a placement prohibition region other than a specific cell adjacent to the macro boundary and outside the macro boundary;
Attaching a tag for connection macro identification to a cell connected to the macro;
Providing path timing information before placement;
Multiplying a cell to which the tag is attached with respect to the timing information and a macro connected to the cell by a set multiplier to estimate an influence of a layout change around the macro on a path timing before the layout; and ,
Decomposing the cell with the tag from the estimate into simple cells with 3 or fewer inputs;
Including the disassembled macro-connected first-stage cell and the cells necessary for the design rule check repeater in addition to the cell, and estimating the number of cells inserted and the insertion position in the macro group region;
In order to expand the related macro interval by the number of inserted cells and the insertion position, the step of cutting the outer margin in the macro group region and moving the macro outward,
A semiconductor manufactured through a layout design for improving macro boundary timing, including a step of arranging the disassembled macro-connected first-stage cells as repeaters between macros vacated by movement of the macro Device manufacturing method.

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