JPH113945A - Clock tree design method of semiconductor integrated circuit and semiconductor integrated circuit by the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock tree design method which can reduce skews between clock signals of different systems in a semiconductor integrated circuit which operates in synchronism with a plurality of clock signals of different systems and a semiconductor integrated circuit by it. SOLUTION: A clock tree of two systems includes a clock buffer cell 401, having two output terminals corresponding to two input terminals wherein clock signals CK1, CK2 of two systems are input respectively and clock buffer cells 402 to 405 which amplify a clock signal from an output terminal of the clock buffer cell 401 and supply it to functional cells 406 to 433. Since two clock signal wirings from a clock pad 41 to the clock buffer cell 401 and the clock buffer cells 402 to 405 are arranged in parallel in the device, they are of equal wiring length so that skew is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for designing a semiconductor integrated circuit and a semiconductor integrated circuit using the method.
The present invention relates to a method for designing a clock tree used in a semiconductor integrated circuit that operates in synchronization with a plurality of clock signals, and a semiconductor integrated circuit based on the method.

[0002]

2. Description of the Related Art In recent years, as a layout design method for a large-scale semiconductor integrated circuit, in order to shorten the design and development period,
CAD (C) for automatically arranging and automatically routing “functional cells” having certain functions such as flip-flops
(Operator Aided Design) is widely used.

Further, large-scale semiconductor integrated circuits are generally designed as synchronous logic circuits. In a semiconductor integrated circuit including a synchronous logic circuit, a clock signal must be supplied to the entire semiconductor integrated circuit at the same timing. A semiconductor integrated circuit including a general synchronous logic circuit amplifies current of a clock signal supplied from an external or internal clock signal generation source by a clock driver having a relatively large load driving capability, and flip-flops through a clock signal wiring. And other functional cells.

At this time, signal delay occurs due to the wiring resistance and wiring capacitance of the clock signal wiring and the capacitance of the clock input terminal of the functional cell. However, the wiring length from the clock driver to each functional cell such as each flip-flop is reduced. If they are different, they will each have their own signal transmission delay time, so that a clock signal transmission delay difference (hereinafter referred to as clock skew) occurs. When the clock frequency of a semiconductor integrated circuit including a synchronous logic circuit is increased, the clock skew causes a malfunction due to a timing error. Therefore, it is desirable that the clock skew be as small as possible.

An ASIC using an automatic placement and routing CAD represented by a gate array system or a standard cell system (AP
application Specific Integr
The clock skew can be reduced as much as possible by a hand-crafted full custom layout method instead of an applied circuit method. However, as described above, in recent years, semiconductor integrated circuits have increased in size to tens of thousands of gates.
It is difficult to design the layout by the full custom method of this handcraft in terms of cost. Therefore, automatic placement and routing is performed using CAD. Then
Unless the factors that cause clock skew, such as the wiring length from the clock driver to each flip-flop, are controlled by the automatic placement and wiring CAD, clock skew will occur.

A wiring path for supplying a clock signal to a functional cell that requires it is called a clock line. In a layout design method using automatic placement and routing CAD, a clock signal is current-amplified stepwise by a plurality of clock buffer cells in order to reduce the clock skew of the clock line. That is, a connection from a bonding pad (hereinafter, referred to as a clock pad) to which a clock signal is input to a functional cell requiring a clock signal is connected via a plurality of stages of clock buffer cells. This network is called a clock tree because of its configuration.

Next, a conventional clock tree forming method will be described with reference to FIGS. 6, 7 and 8. FIG.

FIG. 6 is a flowchart of a conventional method for forming a clock tree. In step S1, the CA of a functional cell is determined based on connection information between functional cells constituting a semiconductor integrated circuit not including a clock tree.
D performs automatic arrangement. Next, in step S2,
The arrangement information of all the functional cells to which the clock signal is input and the terminal capacitance of the clock signal input terminal of all the functional cells to which the clock signal is input, the same hierarchical functional layer driven by one clock buffer cell Generation of clock tree connection information such that the total input terminal capacity and total wiring capacity of the cell are equal to the total input terminal capacity and total wiring capacity of functional cells driven by other clock buffer cells in the same hierarchy And the arrangement of clock buffer cells on the clock tree. Here, the clock buffer circuit of the same hierarchy refers to an aggregate of clock buffer cells in which the same number of other clock buffer cells exist in the middle of the path connecting the clock buffer cell and the clock pad.

Next, in step S3, step S2
When the clock buffer cells on the clock tree are placed on top of the functional cells already placed in, avoiding a significant change in the placement position so that their overlapping placement does not affect the clock skew. Correct by automatic placement CAD.

In step S4, based on the final arrangement information created in step S3, the entire semiconductor integrated circuit is wired by giving priority to the clock line by using the automatic wiring CAD for the entire semiconductor integrated circuit. Clock skew is reduced.

FIG. 7 is a conceptual diagram showing the configuration of the clock tree generated in step S2 of FIG. 6, in which a clock pad 1000 is connected to an external lead (not shown) by wire bonding or the like and an external clock signal is output. Is applied. The clock signal applied to the clock pad 1000 passes through one of the first-stage clock buffer cell 1001 and the second-stage clock buffer cells 1002 to 1005, and the functional cells 1006 to 1005 such as flip-flops requiring the clock signal. 1021.

As shown in FIG. 7, the clock tree is literally branched like a tree branch, and the clock buffer cell 1001 drives 1002 clock buffer cells.
1005 to 1005, each of which is driven by 1006 to 1009, 1010 to 1013,
It is an aggregate of four function cells of any of 1014 to 1017 and 1018 to 1021. This clock tree is composed of one clock buffer cell based on the arrangement information of the functional cells receiving the clock signal in step S2 of FIG. 6 and the terminal capacitance of the clock signal input terminal of the functional cell receiving the clock signal. Regarding the total input terminal capacity and the total wiring capacity of the driven functional cells of the same hierarchy, the clock cells generated by other clock buffer cells existing in the same hierarchy are generated so as to be equal.

FIG. 8 is a plan view of a semiconductor integrated circuit using a conventional clock tree forming method described in Japanese Patent Application Laid-Open No. 6-204435.

Referring to FIG. 8, a semiconductor integrated circuit 1101
Clock pad 1 for applying a clock signal from outside
The clock pad 1102 is connected to the first-level clock buffer cell 1103. Also, the clock buffer cell 1103 of the first hierarchy has 4
Second-stage clock buffer cells 1104 to 110
7 is connected. The connection relationship of these clock trees is the same as that of FIG. 7, but the clock tree of FIG. 8 is characterized by the arrangement position of the clock buffer cells constituting the clock tree.

That is, the first-level clock buffer cell 1103 for supplying a clock signal from the clock pad 1102 is arranged at the center of the semiconductor integrated circuit 1101. Then, the first level clock buffer cell 1
103 is connected to four clock buffer cells, and these second-level clock buffer cells 1104 to 1107 are connected.
At a position where the sum of the horizontal coordinate difference and the vertical coordinate difference between any one of the input terminals and the output terminal of the first-level clock buffer cell 1103 is the same.
Clock buffer cells 1104 to 1107 of the second hierarchy are arranged.

As described above, the sum of the absolute value of the difference between the coordinates of a certain point and the other point in the horizontal and vertical directions is generally called the Manhattan distance. In FIG. 8, a point at which the distance from the output terminal of the clock buffer cell 1103 of the first hierarchy becomes constant is indicated by a broken line.
The clock buffer cells of the second hierarchy are all arranged such that their input terminals are located on this broken line. Generally, wiring on a semiconductor integrated circuit is stretched in the horizontal and vertical directions. That is, generally, wiring in an oblique direction is not performed. Under such conditions, the length of the wiring from one point to another point is the Manhattan distance between the points.

Therefore, as shown in FIG. 8, if all the clock buffer cells of the second hierarchy are arranged at positions where the Manhattan distance from the output terminal of the clock buffer cell 1103 of the first hierarchy is constant, the second hierarchy The wiring connecting the input terminal of each clock buffer cell and the output terminal of the clock buffer cell of the first hierarchy has substantially the same length. Therefore, the wiring resistance and the wiring capacitance from the clock pad 1102 to the clock buffer cells 1104 to 1107 of each second hierarchy are all equal, and
It is possible to reduce the skew of the clock signal between the clock buffer cells 1104 to 1107 in the hierarchy. Similarly, if a functional cell such as a clock buffer circuit or a flip-flop branched from and connected to each clock buffer cell is always arranged at a Manhattan distance from the output terminal of the clock buffer cell, it is supplied. Skew between clock signals can be reduced.

From the above description, it is possible to make all the delay times of the functional cells 1108 to 1123 to which the clock signal is supplied from the clock pad the same in the conventional clock tree forming method. The arrival time difference of the clock signals in the functional cells 1108 to 1123, that is, the clock skew becomes almost zero, and it is possible to prevent a malfunction due to the skew.

[0019]

SUMMARY OF THE INVENTION Conventional automatic placement and routing C
A method of forming a clock tree by AD is that, in a semiconductor integrated circuit including a logic circuit operating in synchronization with a single-phase clock signal, clock skew is reduced to almost zero in all functional cells that need to supply the same clock signal. Can be supplied.

However, in a semiconductor integrated circuit including a logic circuit operating in synchronization with a plurality of clock signals of different systems, such as using a two-phase clock signal, clock skew is reduced between clock signals of different systems. Not done.

Next, referring to FIGS. 9, 10 and 11, two-phase clock signals that do not overlap each other (hereinafter, non-overlapping two-phase clock signals) will be described.
The above-described problem will be described using a semiconductor integrated circuit including a logic circuit operating in synchronization with a phase clock signal) as an example.

FIG. 9 is a waveform diagram of the clock signal at the clock pad and at the end of the clock tree. FIGS. 10A and 10B are conceptual diagrams of a clock tree when a conventional clock tree performed on a single-phase clock signal is applied to a non-overlapping two-phase clock signal. FIG. 11 shows a conventional clock tree forming method performed on a single-phase clock as described above.
FIG. 14 is a layout design flowchart applied to a phase clock signal.

In FIGS. 9 and 10, the first clock signal CK1 and the second clock signal CK2 are supplied to the original clock buffer cells 801 and 817 of the first clock tree for each clock signal. This is a clock signal. The first clock signal CK1 is the first clock signal CK1.
The clock signal CK1A is supplied to the functional cells 805 to 816 that pass through the clock buffer cell 801 of the second stage and the clock buffer cells 802 to 804 of the second stage and are connected to the ends of the clock tree requiring the first clock signal CK1. Supplied as At this time, the original clock signal CK1 and the functional cells 805-8
A transmission delay time tDP1 is generated between the clock signal CK1A and the clock signal CK1A.

Similarly, with respect to the second clock signal CK2, the second clock signal CK2 passes through the first-stage clock buffer cell 817 and the second-stage clock buffer cells 818 to 821 and passes through the second clock signal CK2. The clock signal CK2A is supplied to the functional cells 823 to 838 connected to the end of the clock tree requiring the signal CK2. At this time, the original clock signal C
K2 and the clock signal CK2A supplied to the functional cells 823 to 838 have a transmission delay time tD
P2A occurs.

Next, the reason why a difference occurs in the transmission delay time between the clock signals CK1 and CK2 will be described below.

As shown in FIG. 10A, the number of functional cells connected to the clock tree of the first clock signal CK1 is 12, and the clock of the second clock signal CK2 is used as shown in FIG. Sixteen functional cells connected to the tree and the first clock signal CK
Between the first clock signal CK2 and the second clock signal CK2.
anIn number). In such a case, the conventional clock tree forming method using the automatic placement and routing CAD generates a clock tree corresponding to the total load capacity of each clock signal by adjusting the number of clock buffer cells and the number of clock buffer cell stages in the clock tree. I do.

Therefore, the clock trees of the clock signals having different total load capacities have different structures such as the number of clock buffer cells and the number of clock buffer cells in the clock tree. There is a difference between the transmission delay time tDP1 from the input of the clock buffer cell 817 to the transmission delay time tDP2B from the input of the clock buffer cell 817 to the functional cells 823 to 838. Therefore, at the end of the clock tree of each of the clock signals CK1 and CK2,
At t2 to t3 shown in FIG. 9, a state occurs in which two clocks that should not be overlapped overlap each other.

Generally, in a semiconductor integrated circuit using a non-overlapping two-phase clock signal as a basic clock of a logic circuit, the clock skew is reduced for the purpose of improving the clock frequency, and the two clock signals CK1 as shown in FIG. , C
A clock signal that maintains the non-overlap period tNOV provided between K2 must be supplied to functional cells that require the clock signals CK1 and CK2. As in the relationship between the clock signal CK1A when the first clock signal CK1 propagates to the terminal of the clock tree and the clock signal CK2A when the second clock signal CK2 propagates to the terminal of the clock tree in FIG. Clock signal C
If the transmission delay time tDP1 of K1 is substantially equal to the transmission delay time tDP2A of the clock signal CK2A, the non-overlapping period tNOVB between clock signals at the end of each clock tree of each clock signal can be maintained.

However, if a clock signal maintaining the non-overlapping period tNOV cannot be supplied to a functional cell that requires each clock signal, a transparent latch that latches data using one clock signal as a master clock and the other latches Between the transparent latches that latch data using a clock signal as a slave clock, data cylinders may drop out, resulting in malfunction.

Next, a layout design flow for automatically generating a clock tree of a non-overlapping two-phase clock signal using a conventional automatic placement and routing CAD and a clock tree forming method will be described with reference to FIG.

As in the conventional clock tree layout design flow for a single-phase clock shown in FIG. 6, in step S1, based on the information on the connection between the functional cells constituting the semiconductor integrated circuit which does not include the clock tree, the functional is determined. Automatic placement of cells by CAD is performed.

Next, in step S21, one clock is determined by the arrangement information of all the functional cells to which the clock signal CK1 is input and the terminal capacity of the clock signal input terminals of all the functional cells to which the clock signal CK1 is input. The total input terminal capacity and the total wiring capacity of the functional cells of the same hierarchy driven by the buffer cell become equal to the total input terminal capacity and the total wiring capacity of the functional cells driven by other clock buffer cells existing in the same hierarchy. Thus, the connection information of the clock tree to the clock CK1 is generated and the clock buffer cells on the clock tree are arranged.

Next, in step S22, as in step S21, the generation of the connection information of the clock tree with respect to the clock CK2 and the placement of the clock buffer cells on the clock tree are performed.
When the clock buffer cells on the clock tree are arranged so as to overlap the functional cells already arranged in step 21 and step S22, a large arrangement position is set so that their overlap arrangement does not affect the clock skew. Modify with automatic placement CAD while avoiding changes.

Finally, in step S4, based on the final arrangement information created in step S3, the clock line is prioritized, and the entire semiconductor integrated circuit is subjected to wiring processing using automatic wiring CAD, and the clock skew is reduced. We are trying to reduce it.

In the layout design flow of the clock tree shown in FIG. 11, since the clock trees are individually generated for the first clock signal CK1 and the second clock signal CK2, the clock supplied in each clock tree is generated. Although the clock skew of the signal is reduced, there is a problem that the clock skew is not reduced at all between a plurality of clock signals supplied from a plurality of clock trees and having different systems.

An ASIC using an automatic placement and wiring CAD represented by a gate array system and a standard cell system.
(Application Specific Int
In the case of the handcrafted full custom layout method, instead of the [e.g.
Clock skew between a plurality of clock signals having different systems can be minimized. However, in recent years, the scale of semiconductor integrated circuits has increased to several tens of thousands of gates, and it is difficult to design a layout of a large-scale semiconductor integrated circuit by a full custom method of this handcraft due to high cost, and automatic placement is difficult. It is necessary to use the wiring CAD. Therefore, unless the cause of the clock skew due to the difference in the wiring length from each clock driver to each functional cell is controlled by the automatic placement and wiring CAD, the clock skew between a plurality of clock signals of different systems cannot be reduced. .

Therefore, an object of the present invention is to provide a method for designing a clock tree of a semiconductor integrated circuit and a semiconductor integrated circuit using the same, which enable a reduction in clock skew between clock trees of a plurality of clock signals having different systems. Is to provide.

[0038]

Therefore, a method for designing a clock tree of a semiconductor integrated circuit according to the present invention is a method for designing a clock tree of a semiconductor integrated circuit incorporating a logic circuit operating in synchronization with a plurality of clock signals. From each clock input terminal to which a plurality of clock signals are input.
A clock tree design method for supplying each clock signal to functional cells constituting the logic circuit from a clock buffer circuit in an upper hierarchy of the clock buffer circuits existing in the number of or more to the clock buffer circuit in a lower hierarchy, The clock buffer circuit includes a plurality of buffer circuits for amplifying a clock signal applied to an input terminal and outputting the amplified signal to an output terminal, is fixed in layout, and includes the logic circuit that does not include the clock buffer cell on the clock tree. A logic circuit arranging step of arranging all the functional cells based on the constituent inter-functional cell connection information, and a plurality of clock tree connection information for the plurality of clock signals; The clock generated in common with the clock A clock tree connection information generating step, and a clock buffer arranging step of arranging the clock buffer circuit based on the clock tree connection information. The wiring connecting each input terminal of the clock buffer circuit and the wiring connecting each output terminal of the clock buffer circuit of a predetermined upper hierarchy and each input terminal of the corresponding lower hierarchy clock buffer circuit are connected in parallel. It is characterized by:

Further, according to the semiconductor integrated circuit of the present invention, each clock input terminal to which a plurality of clock signals are input, and one
In a semiconductor integrated circuit including a clock tree that supplies each clock signal to a functional cell forming a logic circuit from a clock buffer circuit in an upper layer of the clock buffer circuit that is present or more to the clock buffer circuit in a lower layer, The clock buffer circuit has a plurality of built-in buffer circuits for amplifying a clock signal applied to an input terminal and outputting the amplified signal to an output terminal. The buffer circuit is fixed in layout, and each input of the clock buffer circuit corresponding to each clock input terminal A wiring connecting terminals and a wiring connecting each output terminal of a predetermined upper-layer clock buffer circuit and each input terminal of a corresponding lower-layer clock buffer circuit are connected in parallel.

[0040]

Next, embodiments of the present invention will be described with reference to the drawings. The semiconductor integrated circuit of the present embodiment is described as including a logic circuit that operates in synchronization with a non-overlapping two-phase clock signal.

FIG. 1 shows a clock buffer cell 101 used in a clock tree forming method according to the present invention. The clock buffer cell 101 is configured as a single functional cell, and includes two buffer circuits 1 to cope with formation of a clock tree of two clock signals.
02 and 103 are built-in. Clock buffer cell 101
Are input terminals H01, H for inputting a clock signal.
02 and output terminals N01 and N02 for outputting a current-amplified clock signal. First buffer circuit 1
Numeral 02 current-amplifies the first clock signal applied to the input terminal H01 and outputs the amplified signal from the first output terminal N01.
Similarly, the second buffer circuit 103 includes an input terminal H02
, And amplifies the current of the second clock signal applied thereto, and outputs the amplified signal from the second output terminal N02.

FIG. 2 shows the clock buffer cell 10 of FIG.
2 is a symbol diagram corresponding to No. 1 and has two input terminals H01 and H02 and two output terminals N01 and N02 according to the circuit connection information shown in FIG.

In the present embodiment, the first clock signal C
The number of functional cells supplying K1 is smaller than the number of functional cells supplying the second clock signal CK2, that is, the second clock signal CK.
It is assumed that the total load capacity (FanIn number) of No. 2 is larger than that of the first clock signal CK1.

FIG. 3 is a layout design flow in the clock tree forming method to which the present invention is applied. In step S1, as in the layout design flow in the conventional clock tree forming method, all the func- tions are performed by the automatic placement CAD based on the connection information between the functional cells of the logic circuit portion not including the clock tree in the semiconductor integrated circuit. Place the optional cell.

Next, in step S210, for the clock signal CK2 whose total load capacity is larger than the other clock signal, that is, the clock signal CK1, the arrangement information of the functional cell that supplies the clock signal CK2;
Due to the terminal capacity of the functional cell that supplies the clock signal CK2 for inputting the clock signal, the total input terminal capacity and the total wiring capacity of the functional cell of the same hierarchy driven by one clock buffer cell exist in the same hierarchy. The generation of the connection information of the clock tree and the arrangement of the clock buffer cells on the clock tree are performed so that those of the other clock buffer cells become equal. The clock buffer cells on the clock tree generated at this time are clock buffer cells incorporating the two buffer circuits shown in FIGS.

FIG. 4 is a conceptual diagram of the configuration of the clock tree formed in step S210 of FIG. 3, and the clock buffer cells 401 to 405 use the symbol diagram of FIG. As described above, a clock tree is formed by using clock buffer cells 401 to 405 containing two buffer circuits on the clock line of the clock signal CK2 whose total load capacity is larger than the other clock signal CK1. Is applied to a clock pad 42 connected to an external lead by a bonding wire or the like. The clock signal CK2 passes through the first-stage clock buffer cell 401 and the second-stage clock buffer cells 402 to 405,
The clock signal CK2 is supplied to a functional cell such as a flip-flop that requires the clock signal CK2.

The clock buffer cell forming the clock tree has two input terminals and two output terminals. In step S210, one pair of input terminals of one buffer circuit in the clock buffer cell is connected to the input terminal. Output terminal is
The clock signal CK2 is connected to form a clock tree, and a pair of input terminals and output terminals of the remaining one buffer circuit are not connected. That is, the output terminals of the clock buffer cells 402 to 405 are not connected to the clock input terminals of the functional cells 422 to 433 that supply the clock signal CK1 whose total load capacity is smaller than the other clock signal CK2.

Next, in step S220 in FIG.
The clock buffer cells 401 to 401 on the clock tree for the clock signal CK2 generated in step S210
Using 405, a clock tree of the clock signal CK1 whose total load capacity is smaller than that of the other clock signal is generated. That is, in FIG. 4, the clock pad 41 to which the clock signal CK1 is applied is different from the clock pad 41 already in step S210.
1st stage clock buffer cell 40
The first unconnected input terminal is connected, and the unconnected output terminal of the first-stage clock buffer cell 401 and the unconnected input terminals of the second-stage clock buffer cells 402 to 405 are connected.

Further, the information such as the arrangement position information of the functional cells 422 to 433 and the terminal capacity of the clock input terminal shown in FIG.
Second-stage clock buffer cells 402 to 40 directly connected to the functional cells arranged at 210
5, the unconnected output terminals of the second-stage clock buffer cells 402 to 405 and the clock signal CK while controlling to reduce the clock skew.
1 is connected to the clock signal input terminals of the functional cells 422 to 433 that supply the signal "1".

That is, in the method of designing a semiconductor integrated circuit according to the present embodiment and the semiconductor integrated circuit according to the method, the clock pad 4 to which the clock signal CK1 is supplied is provided.
A path from the lowest level clock buffer cells 402 to 405 shared by each clock tree of one to a plurality of clock signals, and each clock tree of a plurality of clock signals from the clock pad 42 to which the clock signal CK2 is supplied. Clock buffer cells 402-
Regarding the path up to 405, using the connection information of the path, between the output terminals of all the clock buffer cells 401 to 405 on the predetermined clock tree and the input terminals of the lower clock buffer cells 402 to 405, ie, general Is characterized in that all wirings on the clock tree corresponding to all clock signals are connected in parallel.

FIG. 5 is a conceptual diagram showing the configuration of the clock tree in the semiconductor integrated circuit according to the present embodiment after completing step S220. The clock signal CK1 is applied to the clock pad 41, and the clock signal C is applied to the clock pad 42.
K2 is applied, and the clock pad 41 and the clock pad 42 are connected to the input terminals of the single clock buffer cell 401, respectively. In addition, 2 corresponding to two clock signals of a single clock buffer cell 401
One output signal line is connected to input terminals of four clock buffer cells 402 to 405 without crossing two clock signal lines.

The clock signal input terminals of the functional cells 406 to 421 for supplying the clock signal CK2 are output terminals for outputting a signal corresponding to the clock signal CK2 among the output terminals of the second stage clock buffer cell. Connected. Further, the functional cell 4 for supplying the clock signal CK1 which has not been connected in FIG.
The output terminals for outputting a signal corresponding to the clock signal CK1 among the output terminals of the second-stage clock buffer cell are connected to the clock signal input terminals 22 to 433.

Next, in step S30, when the clock buffer cells are arranged so as to overlap the functional cells already arranged in steps S210 and S220, similar to the layout design method in the conventional clock tree forming method, The overlapping placement is corrected by automatic placement CAD while avoiding a significant movement of the placement position of the functional cells so as not to affect the clock skew.

Subsequently, in step S40, similarly to the layout design method in the conventional clock tree forming method, the functional cells of the entire semiconductor integrated circuit including the final arrangement information and clock line connection information created in step S220. The wiring of the entire semiconductor integrated circuit is subjected to wiring processing using automatic wiring CAD by giving priority to the clock line based on the connection information between them.

The semiconductor integrated circuit design method and the semiconductor integrated circuit according to the present embodiment share the same clock buffer cell group in forming a clock tree through which two clock signals propagate as shown in FIG. And by sharing the same clock buffer cell group, the wiring lengths of the two clock signals can be equalized.
The clock skew of the two clock signals up to the input terminal 405 can be made substantially equal.

Therefore, it is possible to form a clock tree of a plurality of clock signals of different systems, and at the same time, to reduce both clock skew between different clock signals and between the same clock signals.

Although not particularly specified in the above description, it goes without saying that automatic design using a computer can be more easily performed by designing using a master slice method or a cell-based method, which is an ASIC method.

[0058]

As described above, the clock tree designing method of the semiconductor integrated circuit and the semiconductor integrated circuit according to the present invention cannot be realized by the conventional clock tree forming method and the layout designing method using the automatic placement and routing CAD. Thus, it is possible to reduce the clock skew between the clock trees in which the plurality of clock signals of different systems propagate respectively.

[Brief description of the drawings]

FIG. 1 is a logic circuit diagram of a clock buffer cell constituting a clock tree according to the present embodiment.

FIG. 2 is a symbol diagram of a clock buffer cell constituting a clock tree according to the present embodiment.

FIG. 3 is a flowchart showing a clock tree designing method of the semiconductor integrated circuit according to the present embodiment;

FIG. 4 is a conceptual diagram illustrating a configuration of a clock tree formed in step S210 of FIG. 3;

FIG. 5 is a conceptual diagram showing a configuration of a clock tree configuring a semiconductor integrated circuit to which a preferred embodiment of the present invention is applied.

FIG. 6 is a layout design flowchart in a conventional clock tree forming method for a single clock.

FIG. 7 is a conceptual diagram illustrating a configuration of a clock tree according to a conventional clock tree forming method.

FIG. 8 is a plan view of a semiconductor integrated circuit designed using a conventional single-phase clock tree forming method so that the Manhattan distance between clock buffers is equal.

FIG. 9 is a timing waveform diagram of a non-overlapping two-phase clock signal.

FIG. 10 is a conceptual diagram illustrating a configuration of a clock tree for two non-overlapping two-phase clock signals configured by applying a conventional clock tree forming method.

FIG. 11 is a flow chart of a layout design of a semiconductor integrated circuit using a non-overlapping two-phase clock signal as a basic clock configured by applying a conventional clock tree forming method.

[Explanation of symbols]

41, 42, 1000, 1102 Clock pad 101, 401-405, 801-804, 817-8
21, 1001 to 1005, 1103 to 1107 Clock buffer cells 102, 103 Buffer circuits 406 to 433, 805 to 816, 823 to 838, 1
006 to 1021, 1108 to 1123 Functional cell 1101 Semiconductor integrated circuit designed using conventional single-phase clock tree forming method

──────────────────────────────────────────────────の Continued on the front page (51) Int.Cl. ⁶ Identification code FI H03K 19/0175

Claims (9)

[Claims] 1. A method for designing a clock tree of a semiconductor integrated circuit incorporating a logic circuit operating in synchronization with a plurality of clock signals, wherein at least one clock input terminal is present from each clock input terminal to which the plurality of clock signals are input. A method for designing a clock tree for supplying clock signals to functional cells forming the logic circuit from a clock buffer circuit in an upper hierarchy of the clock buffer circuit toward the clock buffer circuit in a lower hierarchy, wherein the clock buffer circuit comprises: A plurality of buffer circuits that amplify a clock signal applied to an input terminal and output the amplified signal to an output terminal, are fixed in layout, and constitute the logic circuit that does not include the clock buffer cell on the clock tree. Based on the connection information between the functional cells, all the functions A logic circuit arranging step of arranging a null cell; a clock tree connection information generating step of generating the plurality of clock tree connection information for the plurality of clock signals by sharing the clock buffer cell for each clock; A clock buffer arranging step of arranging the clock buffer circuit based on tree connection information, wherein each clock input terminal and each input terminal of the clock buffer circuit corresponding to the clock input terminal are arranged based on the clock tree connection information. And a wiring connecting the respective output terminals of the predetermined upper-layer clock buffer circuit and the corresponding input terminals of the lower-layer clock buffer circuit is connected in parallel to the clock of the semiconductor integrated circuit. Tree design method. 2. The method according to claim 1, further comprising a step of changing an overlapping arrangement of the functional cell and the clock buffer circuit on the clock tree by changing an arrangement position of the functional cell or the clock buffer circuit. 2. The clock tree designing method for a semiconductor integrated circuit according to claim 1, wherein: 3. A wiring step for preferentially wiring a clock line through which a clock propagates based on the information on connection between functional cells and the clock tree connection information. A clock tree design method for a semiconductor integrated circuit as described in the above. 4. When arranging a lower clock buffer circuit belonging to a lower hierarchy among the clock buffer circuits, the clock input terminals are present on a path through which each clock propagates corresponding to the input terminals. 4. The clock tree designing method for a semiconductor integrated circuit according to claim 1, wherein the same number of the lower clock buffer circuits are connected to the predetermined same-level clock buffer circuits. 5. The clock tree connection information is generated such that a load capacity driven by a predetermined clock buffer circuit is equal to a load capacity driven by another clock buffer circuit existing in the same hierarchy. 4. The method for designing a clock tree of a semiconductor integrated circuit according to claim 1, 2 or 3. 6. A logic circuit is formed from each clock input terminal to which a plurality of clock signals are input, and from a clock buffer circuit in an upper hierarchy of one or more clock buffer circuits to the clock buffer circuit in a lower hierarchy. In a semiconductor integrated circuit including a clock tree that supplies clock signals to functional cells, the clock buffer circuit includes a plurality of buffer circuits that amplify a clock signal applied to an input terminal and output the amplified signal to an output terminal. A wiring connecting each of the clock input terminals and the corresponding input terminal of the clock buffer circuit, and each input of a lower-layer clock buffer circuit corresponding to each output terminal of the predetermined upper-layer clock buffer circuit. Wherein the wires connecting the terminals are connected in parallel. Body integrated circuit. 7. The semiconductor device according to claim 6, wherein the same number of said lower-order clock buffer circuits are connected to clock buffer circuits of the same hierarchy existing on a path through which each clock propagates. Integrated circuit. 8. The semiconductor integrated circuit according to claim 6, wherein the semiconductor integrated circuit is formed by a master slice method.
A semiconductor integrated circuit as described in the above. 9. The semiconductor integrated circuit according to claim 6, wherein the semiconductor integrated circuit is formed by a cell-based method.
A semiconductor integrated circuit as described in the above.