JP2972719B2 - Semiconductor integrated circuit device and arrangement method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of designing a semiconductor integrated circuit device, and more particularly, to a design method and a semiconductor integrated circuit device for securing a flip-flop hold time and facilitating design. is there.

[0002]

2. Description of the Related Art FIG. 6 shows a design flow of a conventional one-phase synchronous circuit. A conventional design flow will be described with reference to FIG.

After circuit design, in step 202, a temporary wiring delay is estimated from the circuit connection information 201.

If the delay between flip-flops is insufficient and the hold time cannot be satisfied, step 20 is executed.
At 4, the delay element is inserted. Also, countermeasures are taken against other timing violations.

At step 203, the arrangement is executed.

After placement, verification is performed in step 205 with the actual wiring delay.

If the delay between flip-flops is insufficient and the hold time cannot be satisfied, a delay element is inserted in step 204 and the process returns to the wiring process in step 203, or the flip-flop in which the hold time is not satisfied is determined in step 206.・ Increase the wiring length between flops,
Increase the wiring delay to secure the hold time. Also, countermeasures are taken against other timing violations.

As described above, the designer repeats the above flow while considering the timing and the like until the timing violation converges, and the development time is increased.

[0009] For example, Japanese Patent Application Laid-Open No. 5-175467 includes a register unit for storing multi-bit data and a random logic unit for processing data output from the register unit. ASIC composed of flip-flop arrays concentrated in a part
(Application specific IC) devices have been proposed. The same publication also describes a method of arranging flip-flops, but this is to reduce the bias of clock signal delay by intensively arranging flip-flop arrays in one corner, It does not provide a means for ensuring the hold time of the flip-flop.

[0010] For example, Japanese Patent Application Laid-Open No. H5-250891 discloses a shift register that prevents a subsequent stage of a shift register circuit from malfunctioning due to a clock delay due to a wiring delay. A shift register circuit has been proposed that can be completed with a book and guarantees a sufficient hold time.However, this circuit method adds a wiring delay to the clock, and is used for large-scale one-phase synchronous circuits. Is not suitable.

[0011]

As described above, in the conventional design method, after placement, the delay time between flip-flops is determined by actual wiring verification, and if there is a shortage, a delay element is inserted. Alternatively, the hold time is ensured by increasing the wiring length and the wiring capacity.

However, the insertion of the delay element takes a lot of trouble and increases the number of transistors.

In addition, in the method of increasing the wiring length, since the wiring is performed manually, the amount of work is enormous when there are many corresponding locations.

Accordingly, the present invention has been made in view of the above-mentioned problems, and has as its object the purpose of making the hold time of the flip-flop transparent to the designer.
An object of the present invention is to provide a semiconductor integrated circuit device capable of securing a sufficient hold time and a method of arranging the same.

[0015]

In order to achieve the above object, according to the arrangement method of the present invention, when a one-phase synchronous circuit is arranged on an LSI chip, (a) a clock is used as a common input from circuit connection information. Extracting a plurality of flip-flops, arranging the plurality of flip-flops as macros having a substantially rectangular planar shape, and (b) inputting data of each of the plurality of flip-flops in the macro A terminal group respectively corresponding to a terminal and a data output terminal is divided into an input terminal and an output terminal and arranged on the opposite side of the outer periphery of the rectangular macro, and (c) the terminal group corresponds to the flip-flop of the flip-flop. (D) corresponding to a data output terminal of an arbitrary one of the plurality of flip-flops; By temporarily pulling out from the output terminal of the macro outer peripheral portion to the outside of the macro and wiring to the input terminal of the macro outer peripheral portion corresponding to the data input terminal of the next flip-flop, a wiring delay of at least one side of the rectangle is provided. Is added to guarantee the hold time of the flip-flop in the subsequent stage without inserting a delay element.

Further, according to the semiconductor integrated circuit device of the present invention, in the one-phase synchronous semiconductor integrated circuit device including a plurality of flip-flops driven by a common clock, the plurality of flip-flops have a substantially rectangular planar shape. As a macro of a type, it is concentratedly arranged on a part on a chip, and the outer periphery of the rectangular macro is respectively connected to a data input terminal and a data output terminal of each flip-flop of the plurality of flip-flops in the macro. The corresponding terminal group is divided into an input terminal and an output terminal and provided on the opposite side of the outer periphery of the rectangular macro, and is directly connected to the data input terminal and the data output terminal, so that any of the plurality of flip-flops is provided. A wiring delay of at least one side of the rectangle is added between the output of the flip-flop and the input of the flip-flop of the next stage. It is made of is.

[0017]

Embodiments of the present invention will be described below. In a preferred embodiment of the method of arranging a semiconductor integrated circuit device according to the present invention, in the method of arranging a one-phase synchronous circuit, a flip-flop is extracted from circuit connection information and is extracted as a flip-flop macro on a chip. Terminals are concentrated and arranged, and these terminals are divided into input and output, and each is arranged on the opposite side of the outer periphery of the flip-flop and macro, so that a wiring delay is added between the data of the flip-flop and the subsequent flip-flop The flop hold time is guaranteed without inserting a delay element.

More specifically, (a) circuit connection information (FIG. 4)
101), a plurality of flip-flops having a clock as a common input are extracted (102 in FIG. 4), and the plurality of flip-flops are concentratedly arranged as macros having a substantially rectangular planar shape (105 in FIG. 4). (B) At this time, a terminal group corresponding to a data input terminal and a data output terminal of each flip-flop of the plurality of flip-flops in the macro is divided into an input terminal and an output terminal. (D1 to D4, Q1 to Q4 in FIG. 1 (b)) are disposed on opposite sides of the outer periphery of the rectangular macro, and (c) the terminal group corresponds to the data input terminal and the data output terminal of the flip-flop. (D) a terminal at the outer peripheral portion of the macro corresponding to a data output terminal of an arbitrary one of the plurality of flip-flops (FIG. 1)
From (Q) of (b), it is once pulled out of the macro, and wired to a terminal (D2 in FIG. 1 (b)) on the outer periphery of the macro corresponding to the data input terminal of the flip-flop of the next stage.

With this, a wiring delay of at least one side of the macro rectangle is added, and the hold time of the flip-flop in the subsequent stage is guaranteed without inserting a delay element.

In the embodiment of the present invention, the processes (a) to (d) are controlled by a program executed on a computer constituting a CAD system for performing automatic placement and routing or interactive placement and routing. Of course, it may be realized.

FIG. 1 is a diagram for explaining a preferred embodiment of the semiconductor integrated circuit device of the present invention. That is, FIG. 1A is a diagram showing an example of a circuit configuration of a one-phase synchronous circuit, and FIG. 1B is a diagram illustrating a flip-flop of FIG. FIG.

Referring to FIG. 1A, flip-flops FF1 to FF4 input a common clock CLOCK to a clock terminal and input an A terminal to a data input.
Is connected to the data input of FF2, its output is connected to terminal D, and the output Q of FF3, which inputs the terminal B to the data input, is connected to the data input of FF4 via the combinational circuit 1 and its output is connected to the terminal The input from the terminal C is connected to the terminal F through the combinational circuit 2. Referring to FIG. 1B, flip-flops FF1 to FF4 are arranged in a concentrated manner.

FIG. 2 is a diagram showing the operation timing of the circuit shown in FIG. 2, A is a data input signal input to the terminal A of FIG. 1, CLOCK is a clock signal, FF1: Q is a signal waveform of the data output terminal Q of the flip-flop FF1, and FF2: D is a signal of the flip-flop FF2. The signal waveform at the data input terminal D, where D is the terminal D
FIG. In FIG. 2, if the delay time ま で from the data output terminal Q of the flip-flop FF1 to the data input terminal D of the next-stage flip-flop FF2 is small, the hold time with respect to the rising edge of the clock signal (data after clock transition is constant) (Time to hold the logical value). Therefore, in the embodiment of the present invention, the data output terminal Q of the flip-flop FF1 is
Is provided with a wiring delay of at least one side of the outer periphery of the macro from the first stage to the data input terminal D of the next flip-flop FF2, thereby satisfying the condition of the hold time.

In the embodiment of the present invention, flip-flops FF1 to FF4 operating on the same clock are:
It is configured as a macro (flip-flop macro) irrespective of the connection of the data signal.

At this time, in the embodiment of the present invention,
Data inputs D and outputs Q of all flip-flops FF1 to FF4 inside the flip-flop macro are directly connected to different terminals provided on the outer periphery of the flip-flop macro in a one-to-one correspondence.

Further, with respect to different terminals provided on the outer periphery of the flip-flop macro, a data input terminal directly connected to the data input D of the flip-flop and a data output terminal directly connected to the output Q are connected to the flip-flop. It is arranged on the opposite side of the outer periphery of the flop / macro, and the minimum value of the wiring delay is the wiring delay of one flip side of the flip-flop / macro side.

In FIG. 1, since the wiring delay in the vertical direction on the paper is similarly applied to the clock signal, the wiring delay in the horizontal direction on the paper is guaranteed.

As for the clock (CLOCK), a terminal (CLK) is arranged at the center of the flip-flop macro, or a clock signal is distributed from the center of the flip-flop macro, and variations in delay due to clock wiring are removed. -The length is reduced to half the length of the macro side (see FIG. 3 described later).

The hold time of the flip-flop is ensured by the above-described wiring delay difference.

In the conventional method, after arrangement, the delay time between flip-flops is obtained by back annotation,
For the shortage, a delay element is inserted, or the hold time is ensured by increasing the wiring length and increasing the wiring capacity. However, according to the embodiment of the present invention,
When the flip-flop macro hierarchy information is provided on the circuit connection information (net list), the placement and routing process ensures the designer to secure the hold time without being aware of the hold time・ Wiring can be performed.

[0031]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below with reference to the drawings. FIG. 3 is a diagram for explaining one embodiment of the present invention, and is a diagram showing an example of a flip-flop macro to which the present invention is applied.

It is assumed that 16 flip-flops are used in the one-phase synchronous circuit. In this case, a macro composed of 16 flip-flops is created.

In FIG. 3, the terminals (D1 to D16) on the left side of the outer periphery of the rectangular flip-flop macro are directly connected to the data input terminals D of the flip-flop inside the flip-flop macro, respectively. Each of the terminals (Q1 to Q16) is directly connected to the data output terminal Q of the flip-flop inside the flip-flop macro.

The number of data input terminals and the number of data output terminals are equal to the number of flip-flops inside the flip-flop macro, that is, in the example shown in FIG.
Sixteen output terminals are provided.

The branch point in the flip-flop macro of the clock input (CLK) is arranged at the center of the flip-flop macro, and wired so as to minimize the variation (clock skew).

The operation of one embodiment of the present invention will be described with reference to FIG.

When the data output Q of a certain flip-flop is directly connected to the data input D of the next flip-flop, first, the flip-flop macro is output from the output terminal of the flip-flop macro on the right side of FIG. Output outside the macro.

Here, the data input D of the next stage flip-flop is input from the input terminal of the flip-flop macro on the left side of FIG. 3, so that the width (terminal) of the flip-flop macro even at the shortest distance Wiring for the distance between sides always occurs.

As a result, the hold time of the next stage flip-flop can be secured.

Another embodiment of the present invention will be described. Hereinafter, an example in which the present invention is applied to a large-scale circuit will be described as a second embodiment of the present invention. FIG. 5 is a diagram showing a chip layout for explaining a second embodiment of the present invention.

The one-phase synchronous circuit has a problem that the voltage becomes unstable due to the simultaneous operation of flip-flops as the scale increases. Here, when flip-flops are scattered throughout the chip, measures such as adding a power supply must be performed on the entire chip.

On the other hand, according to one embodiment of the present invention, when configuring a large-scale flip-flop macro, it is necessary to take measures against the power supply by strengthening the power supply only for the flip-flop macro through which the most current flows. You can do it. FIG.
In this case, a power supply strengthening measure is taken by providing a peripheral power supply wiring on the outer periphery of the flip-flop macro, and a useless additional power supply area is eliminated. As a result, the size of the LSI can be reduced.

[0043]

As described above, according to the present invention,
At the point when the flip-flop macro hierarchy information is provided on the circuit connection information, in the placement / wiring process, the designer performs placement / wiring while ensuring the hold time without being aware of the hold time. It has the effect of being able to do things.

The reason is that, in the arrangement method of arranging a one-phase synchronous circuit on an LSI chip, a plurality of flip-flops are collectively arranged on a chip as a group of terminals as a rectangular flip-flop macro. Then, a terminal group is divided into an input terminal and an output terminal, and arranged on opposite sides of the outer periphery of the flip-flop macro, respectively, and the data input terminal and the data output terminal of the flip-flop are directly connected to the input terminal and the output terminal, respectively. By wiring the terminals around the flip-flop macro, a wiring delay is added to the data output and input between the flip-flops, and the hold time of the subsequent flip-flop is guaranteed without inserting a delay element. This is because

[Brief description of the drawings]

FIG. 1 is a diagram for describing an embodiment of the present invention, and is a diagram illustrating an example of a one-phase synchronous circuit to which the present invention is applied.

FIG. 2 is a diagram for explaining the embodiment of the present invention, and is a diagram showing operation timing of the circuit of FIG. 1;

FIG. 3 is a diagram showing one embodiment of a flip-flop macro to which the present invention is applied.

FIG. 4 is a flowchart showing one embodiment of a design flow according to the present invention.

FIG. 5 is a diagram for explaining a second embodiment of the present invention.

FIG. 6 is a flowchart showing an example of a conventional design flow.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 LSI chip 10 Flip-flop macro 11 Loop power supply 12 Power supply pad 101 Circuit connection information 102 Flip-flop extraction processing 103 Flip-flop-less circuit connection information 104 Flip-flop list 105 Macro conversion processing 106 Flip-flop macro 107 Synthesis Processing 108 Flip-flop macro hierarchical circuit connection information 109 Wiring processing FF1 to FF4 Flip-flop CLOCK Clock signal

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-8-320893 (JP, A) JP-A-8-83299 (JP, A) JP-A-10-154793 (JP, A) JP-A-10-108 22789 (JP, A) JP-A-9-54796 (JP, A) JP-A-7-192031 (JP, A) (58) Fields investigated (Int. Cl. ⁶ , DB name) H01L 27/04 G06F 17 / 50 H01L 21/82 H01L 21/822

Claims (4)

(57) [Claims] When arranging a one-phase synchronous circuit on an LSI chip, (a) extracting a plurality of flip-flops having a clock as a common input from circuit connection information;
The flops are arranged in a concentrated manner as macros having a substantially rectangular planar shape, and (b) one-to-one correspondence is made between the data input terminals and the data output terminals of each of the plurality of flip-flops in the macro. (C) directing the terminal group directly with the data input terminal and the data output terminal of the flip-flop corresponding to the input terminal and the output terminal; (D) once leading out of the macro from an output terminal of the outer peripheral portion of the macro corresponding to a data output terminal of an arbitrary flip-flop among the plurality of flip-flops;
By wiring to the input terminal on the outer periphery of the macro corresponding to the data input terminal of the flip-flop in the next stage, a wiring delay of at least one side of the rectangle is added, and the hold time of the flip-flop in the subsequent stage is delayed A method for arranging a semiconductor integrated circuit device, wherein the method is guaranteed without insertion of a semiconductor integrated circuit device. 2. A one-phase synchronous semiconductor integrated circuit device including a plurality of flip-flops driven by a common clock, wherein the plurality of flip-flops are at least on a chip as macros having a substantially rectangular planar shape. A group of terminals arranged in a centralized manner, and a set of terminals corresponding to the data input terminal and the data output terminal of each flip-flop of the plurality of flip-flops in the macro, A plurality of flip-flops by directly connecting the input terminal and the output terminal to the data input terminal and the data output terminal of the flip-flop. Between the output of any flip-flop and the input of the next stage flip-flop. The semiconductor integrated circuit device, characterized in that one side portion of the wiring delay becomes is added. 3. The semiconductor integrated circuit device according to claim 2 , wherein a peripheral power supply wiring is provided on an outer periphery of said flip-flop macro to enhance power supply. 4. A CAD system for arranging and wiring a one-phase synchronous circuit on an LSI chip, comprising: (a) extracting a plurality of flip-flops having a clock as a common input from circuit connection information;
(B) one-to-one correspondence between a data input terminal and a data output terminal of each flip-flop of the plurality of flip-flops in the macro Processing of dividing the group of terminals into input terminals and output terminals and arranging them on opposite sides of the outer periphery of the rectangular macro, (c) the data input terminal and the data output terminal of the flip-flop corresponding to the terminal group (D) once leading out of the macro from an output terminal of the outer periphery of the macro corresponding to a data output terminal of an arbitrary flip-flop among the plurality of flip-flops;
A recording medium for recording a program for causing the computer to execute the above-described processes of wiring the wires to the input terminals on the outer periphery of the macro corresponding to the data input terminals of the flip-flop in the next stage.