JPH1074840A - Auto placement and routing device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain such a device for increasing the operating speed of a circuit and the degree of integration in layout by extracting repetition logic which uses a prescribed logic element as the cell of the first stage from a net list and rewriting the extracted repetition logic to cell information constituted into one cell. SOLUTION: A repetition logic extracting section 102 extracts repetition logic using a prescribed logic element as a first-stage cell from a net list 101, and a repetition logic rewriting section 103 rewrites repetition logic on the list 101 to cell information constituted into one cell. An automatic placement and routing section 106 makes auto placement and routing, based on the cell information on the list 101. In addition, for example, a dummy cell inserting section 105 inserts a dummy cell between each logic constituting the repetition logic, and a repetition logic library 104 stores the cell information in which the repetition logic is constituted into one cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to the field of information processing, and more particularly to an automatic placement and routing apparatus used for layout design of electronic circuits.

[0002]

2. Description of the Related Art A conventional automatic placement and routing apparatus will be described below with reference to the drawings. In a conventional automatic placement and routing apparatus, placement and routing are performed uniformly in cell units. FIG.
It is a conceptual diagram which shows an example of the repetition logic part in the circuit which performed the automatic placement and routing by the conventional automatic placement and routing apparatus. Referring to FIG. 9, a circuit 900 includes logics A, B,
C and D are included. Logic A, B, C, and D
Includes macro cell 1, macro cell 2, macro cell 3, and macro cell 4, respectively. Logic A includes wirings 9, 10, and 11 for connecting the respective macro cells.
including. Similarly, logic B includes wirings 12, 13, and 14 for connecting each macro cell, and logic C includes wirings 1 for connecting each macro cell.
5, 16, and 17, and the logic D includes wirings 18, 19, and 20 for connecting the respective macro cells.
including.

Next, the operation of the circuit 100 will be described. Logic A, logic B, logic C, and logic D propagate signals in the order of macro cell 1, macro cell 2, macro cell 3, and macro cell 4, respectively.

[0004]

The circuit using the conventional automatic placement and routing apparatus as described above has the following problems.

That is, since the arrangement and wiring are uniformly performed in units of cells, the intervals between the arranged cells may be unnecessarily large, which has been a cause of hindering high integration of the layout.

In addition, since the arrangement and wiring are performed uniformly in units of cells, even if there are a plurality of combinations of cells having the same connection relationship, the length of the wiring for connecting them is not constant. May be set to any length. As a result, a delay more than necessary in the operation of the circuit may occur, which causes a timing problem in the circuit operation, which hinders an increase in the speed of the circuit.

The purpose of the present invention is to solve the above-mentioned problems, and an object of the present invention is to achieve a high-speed circuit and a high integration of a layout. It is an object of the present invention to provide an automatic placement and routing apparatus that can perform the above. In addition, when the circuit layout is highly integrated and the circuit is operated at high speed, it is important that the product development period is not lengthened and the development period is shortened.

[0008] The object of the invention described in claim 3 is that of claim 1
Another object of the present invention is to provide an automatic placement and routing apparatus capable of shortening a product development period.

An object of the present invention described in claim 4 is that of claim 3
Another object of the present invention is to provide an automatic placement and routing apparatus capable of shortening the layout design period of a high-speed and highly integrated circuit.

[0010]

An automatic placement and routing apparatus according to claim 1, further comprising: a repetition logic extracting means for extracting a repetition logic having a predetermined logic element as a first-stage cell from a netlist; , Repetition logic rewriting means for rewriting the repetition logic into cell information in one cell, and automatic placement and routing means for performing automatic placement and routing based on the cell information in the netlist. It is characterized by.

According to a second aspect of the present invention, there is provided an automatic placement and routing apparatus according to the first aspect, further comprising a dummy cell insertion unit for inserting a dummy cell between logics constituting the repetition logic. It is further characterized by including.

An automatic placement and routing apparatus according to a third aspect is the automatic placement and routing apparatus according to the first aspect, wherein the automatic placement and routing apparatus stores the cell information obtained by converting the repetition logic into one cell. The repetition logic rewriting means stores the rewritten cell information in the repetition logic library.

According to a fourth aspect of the present invention, there is provided the automatic placement and routing apparatus according to the third aspect, wherein the automatic placement and routing means is configured to perform automatic placement and routing based on cell information read from the repetitive logic library. Wiring is performed.

The automatic placement and routing apparatus according to a fifth aspect is the automatic placement and routing apparatus according to the first aspect, wherein the predetermined logic element is a flip-flop.

According to the first aspect of the invention, the repetitive logic extracting means for extracting a predetermined logic element as a first-stage cell from the netlist by the repetitive logic extracting means. The repetition logic rewriting means rewrites the repetition logic in the extracted netlist to cell information that is made into one cell. Automatic placement and routing is performed by the automatic placement and routing means based on the rewritten cell information in the netlist.

Therefore, a repetitive logic including a predetermined logic element, which is likely to cause a timing problem, in the first stage is provided.
Since it can be cellized and used for automatic placement and routing,
Higher speed of the circuit and higher integration of the layout can be achieved while ensuring consistency of operation timing in the circuit.

According to the invention described in claim 2, according to claim 1
In addition to the operation of the invention described in (1), the dummy cell is inserted between the logics of the repetitive logic constituting the cell information by the dummy cell inserting means.

Therefore, the wiring of the other circuits only needs to pass through the dummy cells, and there is no need to bypass the one-cell repetitive logic. For this reason, it is not necessary to provide extra wiring again, so that high integration of the layout can be maintained, the consistency of the operation timing of the circuit can be ensured, and the speed of the circuit can be increased.

According to the invention of claim 3, according to claim 1,
In addition to the operation of the invention described in (1), the cell information rewritten by the repetition logic rewriting means is stored in a repetition logic library for storing cell information obtained by converting the repetition logic into one cell.

Therefore, the cell information in which the repetition logic is formed into one cell is stored in the repetition logic library, so that a list of the cell information of the repetition logic formed into one cell can be created. For this reason, the list of cell information can be used for layout design of another type, so that the type development period can be shortened.

According to the invention set forth in claim 4, according to claim 3,
In addition to the operation of the invention described in the above, by automatic placement and routing means,
Automatic placement and routing is performed based on the cell information read from the repetitive logic library.

Therefore, the cell information already stored can be used. Therefore, the layout design can be started immediately without extracting the same repetitive logic again, so that the layout design period of a high-speed and highly integrated circuit can be shortened.

According to the invention described in claim 5, according to claim 1,
In addition to the operation of the invention described in (1), the repetition logic extraction means extracts the repetition logic using the flip-flop as the first-stage cell from the netlist.

Therefore, since the repetitive logic including the flip-flop in which the timing problem easily occurs in the first stage is formed into one cell and used for the automatic placement and routing, the consistency of the operation timing in the circuit including the flip-flop is ensured. In addition, it is possible to increase the speed of the circuit and increase the integration of the layout.

[0025]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of the automatic placement and routing apparatus according to the present embodiment. Referring to FIG. 1, automatic placement and routing apparatus 100 includes a netlist 101 storing circuit connection information, and a netlist 10.
A repetition logic extraction unit 102 for extracting a repetition logic using a predetermined logic element as a first-stage cell from 1 and a repetition logic rewriting unit for rewriting the repetition logic in the netlist 101 into cell information of one cell 103
A repetition logic library 104 for storing cell information obtained by converting repetition logic into one cell, a dummy cell insertion unit 105 for inserting a dummy cell between logics constituting the repetition logic, and a netlist 101
And an automatic placement and routing unit 106 for performing automatic placement and routing based on cell information in the cell.

Next, the operation of the automatic placement and routing apparatus according to this embodiment will be described. FIG. 2 is a flowchart showing the operation of the automatic placement and routing apparatus according to the present embodiment. With reference to FIG. 2, first, at the time of automatic placement and routing, it is determined whether or not to use a previously registered repetition logic library 104 as cell information in which repetition logic is made into one cell (S201). When it is determined that the repetition logic library 104 is to be used, cell information obtained by pre-registering the repetition logic into one cell is read from the repetition logic library 104 (S206).

On the other hand, when it is determined that the repetition logic library 104 is not used, the repetition logic extraction unit 102 extracts the repetition logic. Next, the repetition logic rewriting unit 103 rewrites the extracted repetition logic into cell information in one cell,
It is recorded in the netlist 101 (S203). next,
The cell information obtained by converting the repetition logic into one cell is registered in the repetition logic library 104 (S204). next,
Cell information obtained by converting the repetition logic into one cell is read from the netlist 101 (S205). Next, the dummy cell insertion unit 105 inserts a dummy cell between logics constituting the cell information read from the netlist 101 or the repetitive logic library 104 (S207). Next, automatic placement and routing is performed based on the cell information of one cell into which the dummy cell has been inserted (S208). Thereafter, the automatic placement and routing apparatus ends the operation.

Next, the extraction of the repetition logic will be described in more detail. FIG. 3 is a circuit diagram showing an example of a circuit including the repetition logic according to the present embodiment. Referring to FIG. 3, logic A and logic B correspond to FIG.
Are equivalent to the logic A and the logic B. Logic A includes macro cells 1, 2, 3, and 4, as in FIG. The macro cell 1 is an OR (logical sum) element, the macro cell 2 is a NAND (exclusive logical product) element, and the macro cell 3 is an AND (logical product) element. However, the present invention is not limited to this, and may be applied to any logic element. The macro cell 4 is a flip-flop. However, the present invention is not limited to this, and is applied to any logic element that easily causes a timing problem.

That is, an example is shown in which repetitive logics A and B are extracted in which a predetermined logic element such as a flip-flop or the like in which a timing problem is likely to occur is used as a first stage cell. Elements 15 and 16 are other circuit elements connected to logic A. Elements 17 and 18 are other circuit elements connected to logic B. Logic A
Includes wirings 9, 10, and 11 connected from the output side to the input side of each cell 1, 2, 3, and 4. Logic B includes wirings 12, 13, and 14 connected from the output side to the input side of each of cells 1, 2, 3, and 4. Logic A and logic B each include a stage 20, a stage 21, a stage 22, and a stage 23 starting from the macrocell 4.

From the netlist 101, repetitive logic such as the above-described logic A and logic B is extracted as follows. First, a predetermined logic element existing in the circuit, here, for example, a flip-flop 4
Is extracted. Next, from the data input side of the extracted flip-flop 4 to the output side of the next-stage cell, and further from the input side of that cell to the output side of the next-stage cell, the connection information of the cell is arbitrary for each stage. It is searched (trace back) to the column. Similar search is performed for other flip-flops, and search information of the entire circuit is obtained. From this search information, logics having the same connection information, such as logic A and logic B shown in FIG. 3, are searched and repeatedly extracted as logic.

Next, the rewriting of the extracted repetition logic by one cell will be described in more detail. FIG.
FIG. 14 is a diagram showing cell connection information when the repetition logic according to the present embodiment is made into one cell. Referring to FIG. 4, the same elements as those described in FIG. 3 are denoted by the same reference numerals. The same description of these will not be repeated here. Logic A and logic B, including macrocells 1, 2, 3, and 4, respectively, described above in FIG.
The repetition logic rewriting unit 103 makes the netlist 10
At 1, it is rewritten to logic A including only one macro cell 40. That is, the repetition logic is made into one cell. As described above, the cell information made into one cell is registered in the logic library 104 repeatedly.

Next, the layout composed of the cell information made into one cell will be described in more detail. FIG.
It is a conceptual diagram in case the repetition logic concerning this Embodiment is made into one cell. Referring to FIG. 5, the same elements as those described above with reference to FIG. 3 are denoted by the same reference numerals. The same description of these will not be repeated here. When automatic placement and routing is performed based on cell information of one cell, FIG.
As shown in FIG.
They come together. That is, logic A and logic B
Have the same arrangement and the same wiring as the macro cell 40. The cells 1, 2, 3, and 4 are arranged in the same group, and the wirings 9 and 12, the wirings 10 and 13, and the wirings 11 and 14 are wired in the same layout.

FIG. 6 is a conceptual diagram showing an example of a one-cell repetition logic in a circuit highly integrated by the automatic placement and routing apparatus according to the present embodiment. Referring to FIG. 6, the same elements as those described above with reference to FIG. 3 are denoted by the same reference numerals. The same description of these will not be repeated here. The circuit 800 includes logics A, B, C,
And D. The macrocell 40, which is a repetitive logic formed into one cell, is arranged and wired with the same arrangement and the same wiring as the logic A and the logic B. The same applies to logic C and logic D.

As described above, according to the present embodiment, the repetition logic in which a predetermined logic element is used as a first-stage cell is formed into one cell, and the wiring is performed. Therefore, it is possible to increase the speed of a circuit including a logic element in which a timing problem is likely to occur and to achieve a higher integration of a layout. In addition, since the cells are separated into one by this one cell, the wiring area is reduced and the degree of integration is improved. Furthermore, since the wiring area is reduced, the signal propagation time between each repetition logic becomes equal, and the delay time of the signal propagation time between cells, which has been different despite having the same connection information, is unified. Also, it solves timing problems.

The cell information made into one cell is repeatedly stored in the logic library. Therefore, a list of cell information of the repetition logic can be created. Therefore, the list of cell information can be used for layout design of another type, so that the type development period can be shortened.

Automatic placement and routing is performed based on the cell information read from the repetitive logic library. Therefore, the layout design can be started immediately without repeatedly extracting the logic, so that the layout design period of a high-speed and highly integrated circuit can be shortened.

Further, the repetition logic in which the flip-flop is the first-stage cell is formed into one cell and the wiring is performed. Therefore, it is possible to increase the speed of a circuit including a flip-flop in which a timing problem is likely to occur and to achieve a higher integration of a layout.

Next, insertion of a dummy cell will be described in more detail. FIG. 7 is a conceptual diagram showing an example of wiring of another circuit passing near a cell in which the repetition logic according to the present embodiment is formed into one cell. FIG. 8 is a conceptual diagram in the case where a dummy cell is inserted into a cell obtained by converting the repetition logic according to the present embodiment into one cell. The same elements as those described in FIG. 3 are denoted by the same reference numerals. The same description of these will not be repeated here. Referring to FIG. 7, when the placement and routing by the macro cell 40 is performed as described above, the wiring 24 of another circuit must largely detour outside the macro cell 40. Therefore, it is necessary to perform extra wiring.

Referring to FIG. 8, in the present embodiment, macro cell 40 is provided between dummy cells 1 and 2, macro cells 2 and 3, and macro cells 3 and 4 constituting macro cell 40 by dummy cell insertion section 105. Includes inserted dummy cell 25. Therefore, the wiring 24 of another circuit
Can pass over the dummy cell 25. Although the wiring 24 and the wiring 10 look as if they intersect, actually, the wiring 24 and the wiring 10 do not contact each other because the wiring layers are different.

As described above, according to the present embodiment, the dummy cell is inserted between the logics of the repetitive logic constituting the cell information by the dummy cell insertion unit.

Therefore, the wiring of the other circuits only needs to pass through the dummy cells, and the repetitive logic of one cell can be avoided. For this reason, it is not necessary to provide extra wiring again, so that it is possible to solve the timing problem of the circuit and to increase the speed of the circuit without hindering the high integration of the layout.

[0042]

As described above, according to the first aspect of the present invention, the iterative logic extracting means extracts a repetitive logic having a predetermined logic element as a first-stage cell from the netlist and repeats the repetitive logic. By the logic rewriting means, the repetition logic in the extracted netlist becomes 1
It is rewritten with the cell information converted into cells.

Therefore, a repetitive logic including a predetermined logic element, which is likely to cause a timing problem, in the first stage is used as one.
The cell can be used for automatic placement and routing. For this reason, while ensuring the consistency of the operation timing in the circuit,
Higher circuit speed and higher integration of the layout can be achieved.

According to the second aspect of the present invention, the first aspect is provided.
In addition to the effects of the invention described in (1), dummy cells are inserted between the logics of the repetitive logic constituting the cell information by the dummy cell insertion means.

Therefore, the wiring of the other circuits only needs to pass through the dummy cells, and does not need to bypass the repetitive logic formed into one cell. For this reason, it is not necessary to provide extra wiring again, so that high integration of the layout can be maintained, the consistency of the operation timing of the circuit can be ensured, and the speed of the circuit can be increased.

According to the third aspect of the present invention, a first aspect is provided.
In addition to the effects of the invention described in (1), the cell information rewritten by the repetition logic rewriting means is stored in a repetition logic library for storing cell information obtained by converting the repetition logic into one cell.

Therefore, since the cell information obtained by converting the repetition logic into one cell is stored in the repetition logic library, a list of the cell information of the repetition logic formed into one cell can be created. For this reason, the list of cell information can be used for layout design of another type, so that the type development period can be shortened.

According to the invention set forth in claim 4, according to claim 3,
In addition to the effects of the invention described in the above, by automatic placement and routing means,
Automatic placement and routing is performed based on the cell information read from the repetitive logic library.

Therefore, the cell information already stored can be used. Therefore, the layout design can be started immediately without extracting the same repetitive logic again, so that the layout design period of a high-speed and highly integrated circuit can be shortened.

According to the invention of claim 5, according to claim 1,
In addition to the effects of the invention described in (1), the repetitive logic extracting means extracts the repetitive logic having the flip-flop as the first stage cell from the netlist.

Therefore, the repetition logic including a flip-flop in the first stage, which is likely to cause a timing problem, is one.
Since the cell is used for automatic placement and routing, it is possible to increase the speed of the circuit and increase the layout integration while ensuring the consistency of the operation timing in the circuit including the flip-flop.

[Brief description of the drawings]

FIG. 1 is a block diagram of an automatic placement and routing apparatus according to an embodiment.

FIG. 2 is a flowchart showing an operation of the automatic placement and routing apparatus according to the present embodiment.

FIG. 3 is a circuit diagram illustrating an example of a circuit including repetition logic according to the present embodiment;

FIG. 4 is a diagram showing cell connection information when the repetition logic according to the present embodiment is made into one cell.

FIG. 5 is a conceptual diagram when the repetition logic according to the present embodiment is formed into one cell.

FIG. 6 is a conceptual diagram showing an example of one-cell repetition logic in a circuit highly integrated by the automatic placement and routing apparatus according to the present embodiment.

FIG. 7 is a conceptual diagram showing a wiring example of another circuit passing in the vicinity of a cell in which the repetition logic according to the present embodiment is formed into one cell.

FIG. 8 is a conceptual diagram in a case where a dummy cell is inserted into a cell obtained by converting the repetition logic according to the present embodiment into one cell.

FIG. 9 is a conceptual diagram showing an example of a repetitive logic unit in a circuit in which automatic placement and routing has been performed by a conventional automatic placement and routing apparatus.

[Explanation of symbols]

Reference Signs List 101 netlist, 102 repetition logic extraction unit, 103 repetition logic rewriting unit, 104 repetition logic library, 105 dummy cell insertion unit, 106
Automatic placement and routing section.

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yuji Kawamoto 3-1-1-17 Chuo, Itami-shi, Hyogo Mitsubishi Electric Corporation Semiconductor Software Co., Ltd. (72) Masae Murakami 2-chome, Marunouchi, Chiyoda-ku, Tokyo No. 3 Inside Mitsubishi Electric Corporation

Claims (5)

[Claims] 1. A repetition logic extracting means for extracting a repetition logic having a predetermined logic element as a first-stage cell from a netlist, and rewriting the repetition logic in the netlist into cell information in one cell. Logic rewriting means for automatic placement and routing, and automatic placement and routing means for performing automatic placement and routing based on the cell information in the netlist. 2. The automatic placement and routing apparatus according to claim 1, further comprising a dummy cell inserting unit for inserting a dummy cell between logics constituting the repetitive logic. 3. The automatic placement and routing apparatus further includes a repetition logic library for storing the cell information obtained by converting the repetition logic into one cell, wherein the repetition logic rewriting means repeats the rewritten cell information. 2. The method according to claim 1, wherein the information is stored in a logic library.
6. The automatic placement and routing apparatus according to claim 1. 4. The automatic placement and routing apparatus according to claim 3, wherein said automatic placement and routing means performs automatic placement and routing based on cell information read from said iterative logic library. 5. The automatic placement and routing apparatus according to claim 1, wherein said predetermined logic element is a flip-flop.