JPH08278992A - Designing method for semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE: To increase the degree of freedom of layout design by increasing the number of logic calls which can be connected to one branch wire in a gate array having grating-shaped power wires. CONSTITUTION: To decide whether or not the layout of logic cells C1-C8 connected to branch wires L1-L4, and 11-14 of the grating-shaped power wires 2A and 2B formed on an LSI chip is good, noise coefficients of the respective logic cells C1-C8 are previously calculated and on the basis of arrangement wiring information obtained by the layout designing, the operation timing of the respective logic cells C1-C8 is recognized. Further, plural logic cells which are connected to one branch wire are put in groups for simultaneous operation and noise values generated on power branch wires when the respective cells operate, group by group, are calculated. Then it is decided whether or not the cell layout is acceptable according to whether or not the noise values are larger than a limit value.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout design technique for a semiconductor integrated circuit device, and further a standard cell type L circuit.
The present invention relates to a technique particularly effective when applied to the layout design of a logic cell in SI, for example, a technique useful when applied to the layout design of a gate array having a power supply wiring formed in a grid pattern.

[0002]

2. Description of the Related Art In designing a master slice type LSI, a desired logic function is realized by determining a signal line connecting a plurality of basic logic cells forming a logic gate formed in advance on a chip. .

By the way, in an LSI, a voltage power supply V
The wirings for CC and GND are composed of a trunk wiring having a relatively wide width and branch wirings branched therefrom, and a terminal circuit (a basic logic cell in a gate array) is often connected to each branch wiring. In that case, if one branch wiring is provided for each end circuit, the branch wiring becomes too complicated and competes with the signal line. Therefore, a plurality of end circuits are connected to one branch wiring. A method of supplying power by using

Further, in the gate array, the power supply wirings are arranged in advance along the basic logic cell rows arranged in a matrix form so as to form a grid shape as a whole. A design method of connecting each logic cell may be adopted.

In the gate array designed by such a method, when a plurality of logic cells connected to one branch wiring operate simultaneously, sufficient current is supplied to the logic cell farthest from the main wiring. There is a risk that the output signal amplitude of such a logic cell becomes small and the logic gate in the subsequent stage malfunctions. In addition, the total current consumption of the logic cells connected to one branch line that operate simultaneously is the power supply capacity of the branch line (hereinafter referred to as the current capacity).
If it exceeds, power supply noise may occur. Therefore, at the stage of designing the layout of the logic cell, whether or not the noise generated in the power supply wiring does not exceed a certain value even when a plurality of logic cells connected to one branch wiring are simultaneously turned on / off. It is conceivable to check whether or not the number of cells included in one cell string is limited.

[0006]

However, the present inventors have clarified that the above-mentioned technique has the following problems.

That is, in the above-mentioned design method, the number of cells included in one cell column is limited on the assumption that all the logic cells connected to one branch wiring operate simultaneously. However, in an actual LSI, all the logic cells connected to one branch wiring do not operate at the same time, and some logic cells do not operate at the same time. Therefore, in the above method, the number of cells that can be connected to one branch wiring is limited more than necessary, the degree of freedom in layout design is reduced, the burden on DA is increased, and the optimum LSI chip as a whole is obtained. There is a problem that cells and power lines cannot be placed. Further, in order to increase the flexibility of the cell layout design as described above, it is necessary to narrow the pitch of the power supply wiring or widen the line width,
If this is done, the degree of freedom in the layout design of signal lines and contact holes will be reduced.

The present invention has been made in view of the above circumstances, and its main object is to provide a method for checking a cell layout of a semiconductor integrated circuit device, which can increase the degree of freedom in designing an LSI.

Another object of the present invention is to provide a layout design method for a semiconductor integrated circuit device capable of shortening the turn around time (TAT).

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0011]

The typical ones of the inventions disclosed in the present application will be outlined below.

That is, according to the present invention, the noise coefficient of each logic cell is calculated in advance when determining the quality of the layout of the logic cell connected to the branch wiring of the grid-shaped power supply wiring formed on the LSI chip. In addition, the operation timing of each logic cell is recognized based on the layout and wiring information obtained by the layout design, and the plurality of logic cells that are connected to the one power supply branch wiring are divided into cell groups that operate simultaneously. , Calculates a noise value that can occur in the power supply branch wiring when each cell group operates, and determines whether or not the cell layout is possible depending on whether or not the noise value is equal to or more than a limit value. It is the one.

[0013]

According to the above-described means, the noise value is not recognized on the assumption that all the logic cells connected to the same branch wiring operate at the same time, but the noise value is recognized by recognizing the logic cells actually operating at the same time. Therefore, the number of logic cells connectable to one power supply branch wiring can be increased, and the degree of freedom in layout design can be increased.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the accompanying drawings.

FIG. 1 is a plan view showing a power supply wiring of a gate array and an arrangement state of logic cells as an example of an LSI to which the design evaluation method of the present invention is applied, and FIG. 2 shows a cell layout check procedure of this embodiment. It is a flowchart shown. In this embodiment, the “logic cell” means NA
A minimum unit logic circuit such as an ND gate or a NOR gate and a logic function block (for example, a flip-flop circuit) frequently used in a circuit configured by combining a plurality of these logic circuits to have a desired logic function. Or latch circuit) is specifically designed in advance up to the element layout and registered in a data file as a library.

Explaining the gate array shown in FIG. 1, reference numeral 1 is a semiconductor chip made of single crystal silicon, and 2A and 2B are Vcc lines and ground lines as power supply wirings formed on the semiconductor chip 1. , Vcc line 2A supplies a power supply voltage Vcc such as 5 V to each circuit on the chip, and ground line 2B supplies a ground potential (0 V). Each of the Vcc line 2A and the ground line 2B has a frame-shaped trunk wiring with a relatively wide line width (a rectangular outer frame in the figure and two vertical lattices VDD1 and V inside the outer frame).
SS1) and branch wirings having narrower line widths (horizontal grids VDD2 and VSS2 between vertical grids in the figure), and are formed so as to form a grid shape as a whole.

In the gate array of this embodiment, although not particularly limited, cell rows CR1, CR2, CR3, CR4 in which a plurality of logic cells C are arranged along the horizontal direction of FIG.
... are provided in a plurality of columns at appropriate intervals from each other, and branch wirings L constituting the Vcc line 2A are provided along each cell column.
1, L2, L3, L4, ..., And branch wirings 11, 12, 13, 4, forming the ground line 2B are arranged, and the space between each cell row is a wiring. It is prepared as a formation area. Although not shown, a plurality of power supply branch wirings are similarly arranged between the other trunk wirings (vertical grids). Note that K1 and K2 are power terminals connected to the Vcc line 2A and the ground line 2B, respectively, and P
Reference numerals 1 and P2 are terminals (input / output pins) for signal input / output.

In such a gate array, signal lines for connecting the respective logic cells are formed by forming the wiring in the master slice system, so that a desired logic function is realized.

Next, the cell layout checking method of this embodiment will be described with reference to the flow chart of FIG.

The cell layout check method of the present embodiment comprises four processes of a placement / wiring information input process M1, a simultaneous switching cell recognition process M2, a simultaneous switching noise value calculation process M3, and a layout propriety determination process M4. These processes are performed using, for example, a DA (design automation) computer or the like.

The layout and wiring information input process M1 is necessary for logic design from logic gates and logic function blocks registered in the library as basic logic cells in order to realize an LSI having a desired logic specification. Based on the information necessary to select the ones and determine the layout of the selected logic cells and the route of the signal line (function or type of logic cell to be used, connection information between terminals of each logic cell, etc.). This is a process of inputting the provisional design information obtained by the DA into a computer.

In the next simultaneous switching cell recognition processing M2, whether or not each logic cell is a flip-flop circuit (FF circuit) and whether or not it is a flip-flop based on the information input by the layout and wiring information input processing M1. Recognizes its operation timing (step S2). Next, from this operation timing, the operation timing of each logic cell directly or indirectly connected to the flip-flop circuit is recognized (step S3).

Specifically, paying attention to a certain flip-flop circuit on the chip, starting from that point, a logical trace is performed along the signal line until it reaches another flip-flop circuit or the input / output pin (P), and during tracing. All the logic cells that have passed through are recognized as "simultaneous switching cells" that operate at the same timing. By performing this logic trace for all flip-flops, it is possible to know the operation timing of all logic cells in the LSI.

In the next simultaneous switching noise value calculation process M3, the cell group is first determined based on the logic cell layout information and the power supply wiring information provided by the layout and wiring information input process M1 (step S4). . Here, the determination of the cell group is to recognize a plurality of logic cells connected to one branch wiring sandwiched between the trunk wirings in the vertical direction in FIG. 1 as one group. In FIG. 1, one cell group is marked with CR.

Next, the plurality of logic cells included in each cell group recognized by the above cell group determination (step S4) are further divided into groups according to their operation timing (step S5). In this case, grouping is performed depending on which flip-flop circuit (FF) the logic cell is connected to.

In the next cell layout propriety determination processing M4, attention is paid to one cell group operating at the same time, the magnitude of noise that can be generated in one branch wiring by the cell group is calculated, and then the calculation is performed. The noise value is
Whether the provisional design information input by the "placement and wiring information input process" in step S1 is good or bad is determined by whether or not the preset allowable range is exceeded (steps S6 and S7).
When the noise value exceeds the limit value, a message is output by a printer, a CRT display device or the like (step S8). The above noise check is performed for all cell groups and all operation timings, and after completion, the process proceeds to countermeasure processing such as layout correction (step S9).

Next, the cell grouping performed in step S5 described above, the simultaneous switching noise value calculation performed in steps S6 and S7, and the power supply noise checking method by the determination process will be specifically described with reference to FIG. explain.

Focusing on the flip-flop FF1 belonging to the cell group CR1 in FIG. 1, this flip-flop FF1
Signal is supplied to the logic cells C1 and C2 belonging to the cell group CR2, and signals are further inputted from the logic cells C1 and C2 to the logic cells C3, C4 and C5 belonging to the cell group CR3, and further to the logic. Signals are input from the cells C3, C4, C5 to the logic cells C6, C7, C8 belonging to the cell group CR4, and in this embodiment, these logic cells C1 to C8 operate at the same timing as the flip-flop FF1. It is determined to be a cell group (simultaneous switching cell).

As in the logic cell C8 shown in FIG.
The logic cells on the route from the plurality of flip-flops (FF1, FF2) belong to the plurality of cell groups and are subjected to noise check at their respective operation timings.

After the classification (grouping) of the simultaneous switching cells is completed as described above, the "simultaneous switching noise value N" is calculated for each logical cell group included in one cell group and having the same operation timing. It is performed according to the following equation (1).

N = (A1 × B1) + (A2 × B2) + ... + (An × Bn) (1) where B1, B2, ... Are noise coefficients of each logic cell, and A
1, A2 ... Is the number of logic cells having the same noise coefficient,
When the current capacity of the branch wiring is “1”, the noise coefficient becomes “1” which is the same as the current capacity when the number of the logic cells connected for each cell type is equal to the current consumption of the logic cell. Is a value calculated in advance based on the above, that is, a value obtained by dividing the current consumption of each logic cell by the current capacity of the branch wiring. For example, when the total of four current consumptions of a certain type of logic cell is the same as the current capacity of one branch wiring, the noise coefficient of that logic cell is 0.25 (= 1/4).

The value N calculated by the above equation (1) is
It is compared with a limit value NPD (= 1) representing an allowable range, and when it is larger than the limit value NPD, it is determined that the layout design is unsuitable. For example, in FIG. 1, the logic cell C
1 to C4 have a noise coefficient of "0.2" and logic cells C5 to C
Assuming that the noise coefficient of No. 8 is “0.4”, the simultaneous switching noise value N of the cell group CR2 is 2 × from the equation (1).
0.2 = 0.4 <1 is suitable, the simultaneous switching noise value N of the cell group CR3 is (2 × 0.2) + 0.4 = 0.8 <1 is suitable, simultaneous switching noise value N of the cell group CR4 Is 3 × 0.4 =
It can be seen that 1.2> 1 is non-conforming.

In the case of non-conformity, for example, a reinforcing power supply wiring for short-circuiting the branch wiring to which the inappropriate cell group is connected and another branch wiring adjacent to this is provided, or the inappropriate cell group is provided. Measures are taken such as changing the layout to move a part of the logic cells belonging to the cell group to another cell group, widening the width of the power supply voltage wiring, or narrowing the pitch. After the measures are completed, D
The signal line is changed at A, the changed layout and wiring information is input to the computer again, the cell layout check (steps S1 to S9) of the above-described embodiment is executed, and the process is repeated until all the nonconformities are eliminated.

FIG. 3 shows a configuration example of a computer system to which the above embodiment is applied. In the figure,
CPU is a microcomputer, ROM is a read-only read-only memory, RAM is a random access memory that can be read and written at any time, CRT is a display device, C
RTC is CRT controller, PRT is printer, HD
D is an auxiliary storage device using a hard disk as a medium, F
The DD is an auxiliary storage device using a floppy disk as a medium. A program for executing the cell layout checking method of the above-described embodiment and a program for executing DA are stored in the hard disk device HDD and loaded and executed in the RAM during actual operation. Also, the layout and wiring information is input to the system by the floppy disk device FDD. D
When the layout check is performed by the computer that performs A, the layout and wiring information obtained by the DA is stored in the hard disk device HDD, so that it can be used as it is. The noise coefficient for each cell type used to calculate the noise value is stored in the hard disk device HDD in advance.

As described above, according to the cell layout checking method of the above-described embodiment, the quality of the layout of the logic cell connected to the branch wiring of the grid-like power supply wiring formed on the LSI chip is determined. In addition, the noise coefficient of each logic cell is calculated in advance, the operation timing of each logic cell is recognized based on the layout and wiring information obtained by the layout design, and it is connected to the one power supply branch wiring. The plurality of logic cells that have been operated are divided into cell groups that operate simultaneously, and the noise value that can occur in the power branch wiring when it operates for each cell group is calculated, and whether or not this noise value is greater than or equal to the limit value According to the above, it is determined whether or not the cell layout can be performed.Therefore, the noise value is calculated assuming that all the logic cells connected to the same branch wiring operate at the same time. The number of logic cells that can be connected to one power supply branch line can be increased because the judgment is performed by recognizing the logic cells that actually operate simultaneously and determining the noise value. Has the effect of being increased.

Although the invention made by the present inventor has been specifically described based on the embodiments, the invention is not limited to the above embodiments, and various modifications can be made without departing from the scope of the invention. Needless to say. For example, in the above embodiment, all the logic cells on the route starting from a certain flip-flop to reaching another flip-flop or an input / output pin are classified as a group having the same operation timing. The accuracy of the simultaneous switching noise value calculation may be improved by classifying the cell groups having the same operation timing in consideration of the delay time of the transmitted signal.

In the above description, the case where the invention made by the present inventor is mainly applied to the check of the cell layout of the gate array which is the field of application which is the background of the invention has been described, but the present invention is not limited thereto. Instead, it can be used for a standard cell type LSI and other LSIs in which wiring is formed by a master slice method.

[0038]

The effects obtained by the representative one of the inventions disclosed in the present application will be briefly described as follows.

That is, a layout design with a high degree of freedom is possible. Further, since the power supply noise can be accurately determined at the time of layout design, the turn around time (TAT) can be shortened.

[Brief description of drawings]

FIG. 1 is a plan view showing an arrangement state of power supply wirings and logic cells of a gate array as an example of an LSI to which a design evaluation method of the present invention is applied.

FIG. 2 is a flowchart showing an example of a cell layout check procedure to which the present invention is applied.

FIG. 3 is a block diagram showing a configuration example of a computer system for implementing the design evaluation method of the present invention.

[Explanation of symbols]

 1 semiconductor chip 2A, 2B power supply line CR1-CR4 cell group C1-C8 logic cell FF1, FF2 flip-flop circuit L1-L4, l1-l4 branch wiring

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Masatoshi Kawashima 2326 Imai, Ome-shi, Tokyo Inside Device Development Center, Hitachi, Ltd. (72) Inventor Miyake Unification 1 Horiyamashita, Hadano-shi, Kanagawa Hitachi Computer Engineering Within the corporation

Claims (4)

[Claims] 1. A power supply wiring is formed in a grid pattern, and a plurality of logic cells are connected to one power supply branch wiring,
In a layout design method for a semiconductor integrated circuit device in which each logic cell is connected by a master slice type wiring formation to realize a desired logic function, noise that may occur in branch wiring depending on the operation of the logic cell A coefficient representing the size is calculated in advance for each logic cell, and the operation timing of each logic cell is recognized based on the layout and wiring information obtained by the layout design, and connected to the one power supply branch wiring. The plurality of logical cells are divided into cell groups that operate simultaneously, and the noise value that can occur in the power supply branch wiring when it operates for each cell group is calculated. A method for designing a semiconductor integrated circuit device, wherein the availability of the cell layout is determined according to 2. When a flip-flop is included as one of the logic cells, the logic cells on the route from the same flip-flop circuit to the next flip-flop or signal input / output terminal operate at the same timing. 2. The method for designing a semiconductor integrated circuit device according to claim 1, wherein the cell grouping is performed by recognizing the cells as cells. 3. When the signals from a plurality of flip-flops are input to the same logic cell, the noise value is calculated and determined for each operation timing. Item 3. A method for designing a semiconductor integrated circuit device according to Item 1 or 2. 4. A layout nonconformity is found by performing an evaluation by the method according to claim 1, 2 or 3 based on arrangement and wiring information designed by DA (Design Automation), and the cell layout of the nonconformance portion is changed, A method for designing a semiconductor integrated circuit device, characterized in that the evaluation according to the method of claim 1, 2 or 3 is repeated.