KR20230173904A - Semiconductor integrated circuit design method and apparatus - Google Patents

Abstract

A semiconductor integrated circuit design method according to an embodiment includes a design area preparation step including a standard cell, a cell area division step of dividing the design area into an upper cell area and a lower cell area, and a cell area division step of dividing the design area into an upper cell area and a lower cell area, A lower cut layer placement step of arranging a cut layer between the lower metals based on position and separation distance, and placing the cut layer placed in the lower cell area between metals in the upper cell area based on the placement position. It may include a top cut layer placement step for placing the cut layer.

Description

Semiconductor integrated circuit design method and apparatus}

The present invention relates to a semiconductor integrated circuit design method and device. More specifically, when designing a semiconductor integrated circuit, the cut layer is automatically cut so as not to violate layout design rules that require consideration of the spacing between adjacent metal layers. It is an invention related to the technology to create.

The design of a semiconductor integrated circuit is the task of converting a behavior model for a chip that describes the operation desired from a semiconductor system into a specific structural model that describes the connections between necessary components. In the process of designing such a semiconductor integrated circuit, a library for the cells included in the semiconductor integrated circuit is created, and when the semiconductor integrated circuit is implemented using the generated library, the time required to design and implement the semiconductor integrated circuit is reduced. It has the advantage of reducing costs.

When manufacturing an integrated circuit, transistors are interconnected using metal interconnects composed of various layers. At this time, the structure of the metal interconnect is described and designed in the form of a layout, and the metal layout must be manufactured to satisfy the design rule, which is a rule that guarantees stable yield in the process.

However, as technology develops and semiconductor processes become very fine, the size of metal interconnects and the spacing between metal interconnects gradually decreases, so the spacing between metal interconnects required by integrated circuits does not satisfy the design rules according to conventional manufacturing methods. Problems arise that make it impossible to do so.

To solve this problem, a method of placing cut layers at intervals that must satisfy design rules has been proposed. The cut area layer refers to a method of implementing high-density interconnects by cutting one interconnect into two. Specifically, when designing the layout as shown in Figure 1, the separation distance (B) between metals is a design rule. If it is smaller than the required minimum separation distance between metals (Space min), it refers to a layer that removes metal by the distance.

However, this method also had the problem of taking a long time for the overall design because the designer had to measure each spacing and manually place the cut area.

In addition, when measuring and placing the cut layer according to the conventional method, the cut layer to be placed also has its own design rules, so there is a problem that complexity increases significantly when designing the circuit, which ultimately leads to a decrease in circuit design productivity.

Republic of Korea Open Patent Application No. 10-2013-00110961 A (Semiconductor integrated circuit and design method thereof)

Accordingly, the semiconductor integrated circuit design method and device according to one embodiment are inventions designed to solve the problems described above, and, unlike the prior art, provide an automated design method that automatically calculates and places necessary points in the cut area, and accordingly , the purpose is to increase the productivity of the entire semiconductor design process by shortening the layout design process.

More specifically, after dividing the standard cell area into an upper cell area and a lower cell area, completing the cut layer for the lower cell area, and then creating a cut layer for the upper cell area based on the cut layer for the completed lower cell area. The purpose is to provide a method to place cut layers more easily and effectively by proceeding with the cut layers in ascending order.

The problem to be solved by the present invention is not limited to the above problem, and other problems not mentioned will be clearly understood by those skilled in the art from the description below.

A semiconductor integrated circuit design method according to an embodiment includes a design area preparation step including a standard cell, a cell area division step of dividing the design area into an upper cell area and a lower cell area, and a cell area division step of dividing the design area into an upper cell area and a lower cell area, A lower cut layer placement step of arranging a cut layer between the lower metals based on position and separation distance, and placing the cut layer placed in the lower cell area between metals in the upper cell area based on the placement position. It may include a top cut layer placement step for placing the cut layer.

The lower cut layer arranging step may include arranging the cut layer at the first separation distance when the first separation distance between the outer line of the lower cell area and the upper lower metals is less than a preset distance. there is.

The lower cut layer arranging step may include not arranging the cut layer at the first separation distance when the first separation distance between the outer line of the lower cell area and the upper lower metals is greater than a preset distance. You can.

The step of arranging the lower cut layer may include not arranging the cut layer in the PIN area of the lower cell area.

In the sub-cut layer arrangement step, if there are a plurality of sub-cell areas within the standard cell, the cut layer of the sub-cell area where the sub-cut layer was placed first is arranged and the cut layer is equally applied to other sub-cell areas. It may include the step of proceeding with placement.

The upper cut layer placement step is to place a cut layer at the second separation distance when the second separation distance between the outer line between the upper metals of the upper cell area and the upper metals is smaller than a preset distance. May include steps.

In the upper cut layer placement step, if the second separation distance between the outer line between the upper metals of the upper cell area and the upper metals is greater than the preset distance, the cut layer is not placed at the second separation distance. It may include steps that do not occur.

A semiconductor integrated circuit design device according to an embodiment divides a design area including a standard cell into an upper cell area and a lower cell area, and the lower metal is based on the location and separation distance of the lower metals in the lower cell area. a layout creation unit for arranging a cut layer between metals in the lower cell area and arranging a cut layer between metals in the upper cell area based on the placement position of the cut layer placed in the lower cell area; and a layout generated from the layout. It may include a mask manufacturing unit that generates a mask based on .

The semiconductor integrated circuit design method according to one embodiment automatically calculates the point where the cut layer is needed and then places the cut layer, unlike the existing conventional technology in which the ray user directly finds and places the point where the cut layer is needed. The time and cost required to deploy can be reduced, and thus there is an advantage in that the entire semiconductor process can be carried out more efficiently.

The accompanying drawings, which are included as part of the detailed description to aid understanding of the present invention, provide embodiments of the present invention and explain technical features of the present invention along with the detailed description.
1 is a diagram for explaining a method of measuring a cut area and arranging a cut layer according to the prior art.
Figure 2 is a flowchart showing the process sequence of a semiconductor integrated circuit design method according to an embodiment of the present invention.
Figure 3 is a flowchart showing the process sequence of a semiconductor integrated circuit design method according to another embodiment of the present invention.
Figure 4 is a flowchart showing the order of arranging cut areas according to an embodiment of the present invention, and is a flowchart showing step S130 of Figure 3 in detail.
Figure 5 is a diagram showing an upper cell area and a lower cell area to explain the cut layer arrangement method according to the present invention.
Figure 6 is a diagram for explaining a method of arranging a cut layer in a lower cell area according to an embodiment of the present invention.
Figure 7 is a diagram for explaining a method of arranging a cut layer in an upper cell area according to an embodiment of the present invention.
Figure 8 is a diagram showing the number of comparisons and the number of cut layer arrangement for arranging cut layers based on four areas according to the prior art.
Figure 9 is a diagram showing the number of comparisons and the number of cut layer arrangement for arranging cut layers based on four areas according to the prior art.
Figure 10 is a diagram showing the number of comparisons and the number of cut layer arrangement for arranging cut layers based on four areas according to the present invention.
11 is a diagram schematically showing a semiconductor integrated circuit manufacturing system according to an embodiment of the present invention.
12 is a diagram schematically showing a semiconductor module including a semiconductor integrated circuit manufactured using a design method according to an embodiment of the present invention.
Figure 13 is a diagram showing an electronic system including a semiconductor integrated circuit manufactured using a design method according to an embodiment of the present invention.

The embodiments described in this specification and the configurations shown in the drawings are only preferred examples of the disclosed invention, and at the time of filing this application, there may be various modifications that can replace the embodiments and drawings in this specification.

Throughout this specification, when a part is said to be “connected” to another part, this includes not only direct connection but also indirect connection, and indirect connection refers to connection through a wireless communication network. Includes.

Additionally, the terms used herein are used to describe embodiments and are not intended to limit and/or limit the disclosed invention. Singular expressions include plural expressions unless the context clearly dictates otherwise. In this specification, terms such as “comprise” or “have” are intended to indicate the presence of features, numbers, steps, operations, components, parts, or combinations thereof described in the specification, but are not intended to indicate the presence of one or more other features. The existence or addition of numbers, steps, operations, components, parts, or combinations thereof is not excluded in advance.

In addition, terms including ordinal numbers such as “first”, “second”, etc. used in this specification may be used to describe various components, but the components are not limited by the terms, and the terms It is used only for the purpose of distinguishing one component from another. For example, a first component may be named a second component, and similarly, the second component may also be named a first component without departing from the scope of the present invention.

Additionally, terms such as "~unit", "~unit", "~block", "~member", and "~module" may refer to a unit that processes at least one function or operation. For example, the terms may refer to at least one hardware such as a field-programmable gate array (FPGA) / application specific integrated circuit (ASIC), at least one software stored in memory, or at least one process processed by a processor. there is.

The codes attached to each step are used to identify each step, and these codes do not indicate the order of each step. Each step is performed differently from the specified order unless a specific order is clearly stated in the context. It can be.

Hereinafter, embodiments according to the present invention will be described in detail with reference to the attached drawings.

In embodiments of the present invention described below, the cell library may be a standard cell library. The standard cell method refers to a method of preparing logic circuit blocks (or cells) with various functions in advance and arbitrarily combining these cells to design a dedicated large-scale integrated circuit (LSI) tailored to the specifications of the customer or user. Cells are designed and verified in advance and registered on a computer, and logical design, placement, and routing of cells are performed using computer-aided design (CAD).

Specifically, when designing/manufacturing a large-scale integrated circuit, if standardized logic circuit blocks (or cells) of a certain size are already preserved in the library, the logic circuit block that suits the current design purpose is taken out of these and used as a chip. The entire circuit can be created by arranging a plurality of cells in rows on a cell and performing optimal wiring with the shortest wiring length in the wiring space between cells. The more types of cells preserved in the library, the more flexibility there is in design, and the greater the possibility of optimal chip design.

As such, an integrated circuit using standard cells is a type of semi-custom integrated circuit, and is implemented by using standard cells designed in advance and stored in a standard cell library and arranging the cells to minimize wiring between them. Therefore, development costs are lower and the development period can be shortened compared to fully custom integrated circuits.

Figure 2 is a flowchart showing a method of manufacturing a semiconductor device according to an embodiment of the present invention.

Referring to FIG. 2, the semiconductor device manufacturing method according to this embodiment can be divided into an integrated circuit design (S10) and an integrated circuit manufacturing process (S20).

The design (S10) of the integrated circuit includes steps S11 and S12 and is a step of designing a layout for the integrated circuit, which may be performed in a tool for designing the integrated circuit. At this time, a tool for designing an integrated circuit may be a program including a plurality of instructions executed by a processor. Accordingly, the design of the integrated circuit (S10) can be referred to as a computer implemented method for designing the integrated circuit. Meanwhile, the integrated circuit manufacturing process (S20) is a step of manufacturing a semiconductor device according to an integrated circuit based on a designed layout, and may be performed in a semiconductor process module.

In S11, a standard cell library is provided. Here, the standard cell library may include information about a plurality of standard cells and may be stored in a computer-readable storage medium. The standard cell library may include layout information and timing information of standard cells. In one embodiment, providing a standard cell library may include generating a standard cell library, and more specifically, designing a standard cell.

A standard cell or a semiconductor device formed according to a standard cell may include a structure in which a plurality of layers are stacked, and each of the plurality of layers may include a plurality of patterns. To improve the degree of integration of integrated circuits, the spacing between adjacent patterns is required to be reduced. Accordingly, a plurality of patterns corresponding to one layer may be formed using a plurality of masks rather than a single mask, taking patterning resolution into consideration.

In this way, patterning technology using a plurality of masks is referred to as multi-patterning technology (MPT). For example, the technology for forming multiple patterns using two masks is called DPT (Double Patterning Technology), and the technology for forming multiple patterns using three masks is called TPT (Triple Patterning Technology). The technology for forming multiple patterns using four masks is called QPT (Quadruple Patterning Technology).

In one embodiment, designing a standard cell may include a color decomposition step of designing a plurality of patterns using a plurality of colors respectively corresponding to a plurality of masks. At this time, the color decomposition step may be referred to as a coloring step, and data including the correspondence between a plurality of patterns and a plurality of masks may be referred to as coloring information.

Specifically, through the color decomposition step, a plurality of colors can be assigned to a plurality of patterns corresponding to one layer of a standard cell. Accordingly, patterns with the same color can be formed using the same mask, and patterns with different colors can be formed using different masks.

In step S12, the layout is designed by placing and routing (P&R) standard cells using a standard cell library. Specifically, first, input data defining an integrated circuit is received. Here, the input data may be data generated by synthesis using a standard cell library from data defined in an abstract form for the behavior of the integrated circuit, for example, RTL (Register Transfer Level). For example, the input data may be a bitstream or netlist generated by synthesizing an integrated circuit defined as a Hardware Description Language (HDL) such as VHSIC Hardware Description Language (VHDL) and Verilog.

Next, a storage medium storing the standard cell library is accessed, and standard cells selected according to input data among a plurality of standard cells stored in the standard cell library are arranged and wired. Here, arrangement and wiring refers to the task of placing selected standard cells and connecting the placed standard cells. With placement and wiring complete, a layout for the integrated circuit can be created.

As such, the design of the integrated circuit (S10) may include steps S11 and S12 described above. However, the present invention is not limited to this and may further include various steps according to a general integrated circuit design method, such as modification of a standard cell library, layout verification, and post simulation.

In step S13, a mask is manufactured based on the layout. Specifically, first, OPC (Optical Proximity Correction) can be performed based on the layout. OPC refers to a process of changing the layout by reflecting errors due to the optical proximity effect. Subsequently, the mask can be manufactured according to the changed layout according to the OPC performance results. At this time, the mask can be manufactured using a layout that reflects OPC, for example, a graphic design system (GDS) that reflects OPC. Here, the number of masks manufactured may correspond to the number of colors assigned to patterns included in the layout.

In step S14, a semiconductor device is formed using the manufactured mask. A semiconductor device is formed by performing various semiconductor processes on a semiconductor substrate such as a wafer using a mask.

For example, a process using a mask may mean a patterning process through a lithography process. Through this patterning process, a desired pattern can be formed on a semiconductor substrate or material layer. Meanwhile, the semiconductor process may include a deposition process, an etching process, an ion process, a cleaning process, etc. Here, the deposition process may include various material layer formation processes such as CVD, sputtering, and spin coating.

Ion processes may include processes such as ion implantation, diffusion, and heat treatment. Additionally, the semiconductor process may include a packaging process of mounting a semiconductor device on a PCB and sealing it with a sealing material, and may also include a test process of testing the semiconductor device or package.

Figure 3 is a flowchart showing a method of manufacturing a semiconductor integrated circuit according to an embodiment of the invention.

Referring to FIG. 3, the method of manufacturing a semiconductor integrated circuit according to an embodiment of the present invention includes steps of generating a schematic circuit (S1), creating a layout (S2), and manufacturing a semiconductor integrated circuit. It may include step (S3).

A schematic circuit can represent the connection state of various circuit elements that make up a semiconductor integrated circuit. The design of the schematic circuit may be performed by a circuit design tool such as CAD (Computer Aided Design).

The step (S1) of generating a schematic circuit may include a pre-simulation step that simulates the operation of the designed circuit.

The step of creating a layout (S2) may be the same as the semiconductor integrated circuit design method shown in FIG. 1. For example, the step of creating the layout (S2) includes dividing the design area into cells (S110), designing a layout to create a cut layer in the design area including the cells (S130), and moving from lower cells to upper cells. It may include a cut layer placement step (S140) in which cut layers are placed in ascending order.

Manufacturing the semiconductor integrated circuit (S3) includes performing post-simulation (S310), performing optical proximity correction (OPC) and manufacturing a mask (S230), and forming a semiconductor integrated circuit (S230). may include.

The step of performing post-simulation (S310) may include performing layout versus schematic (LVS) on the completed layout and performing elective rule check (ERC). The LVS may refer to the process of checking whether the schematic circuit and the completed layout match. The ERC may refer to the process of checking whether circuits and wiring are properly electrically connected in the completed layout.

The step of performing OPC (S220) may include correcting the layout by reflecting the error due to the optical proximity effect, and the step of manufacturing the mask (S320) may include manufacturing a mask using the layout corrected by performing OPC. It may include steps. Meanwhile, the mask can be manufactured for each colored layout. The step of forming a semiconductor integrated circuit (S250) may include forming a semiconductor integrated circuit on a wafer through a photo-lithography process using the manufactured mask.

Figure 4 is a flowchart showing the order of arranging cut areas according to an embodiment of the present invention, and is a flowchart showing step S130 of Figure 3 in detail, and Figure 5 is a flowchart for explaining the cut layer arrangement method according to the present invention. It is a diagram illustrating an upper cell area and a lower cell area. FIG. 6 is a diagram illustrating a method of placing a cut layer in a lower cell area according to an embodiment of the present invention, and FIG. 7 is a diagram according to an embodiment of the present invention. This is a diagram to explain how to place a cut layer in the upper cell area.

4 to 7, for convenience of explanation, the description is based on two cells (upper cell, lower cell), but the embodiment of the present invention is not limited to this, and the principle of the present invention is more than two. Of course, this can also be applied if you have cells.

In addition, in the case of the present invention, as described above, there is a feature of sequentially arranging cut layers from the lower cell area to the upper cell area, and here, the concepts of upper and lower are not absolute concepts but relative concepts. For example, if there are a total of 5 cells (1st cell, 2nd cell, 3rd cell, 4th cell, 5th cell) and you place a cut layer for 5 layouts, the 1st cell is the lowest area. cell, and the 5th cell becomes the cell of the highest area. According to the relative concept, the 2nd cell becomes the upper cell based on the 1st cell, but the 2nd cell becomes the lower cell based on the 3rd cell. do.

Referring to FIG. 4, after arranging standard cells and creating a wiring pattern according to S120, the layout with the wiring pattern completed is received and the layers are selected one by one, moving up from the lower cell area to the upper cell area. (S210)

A cell is selected, and information on the wiring location and the numerical spacing between wiring within the selected cell is extracted. (S220)

Step S220 extracts the location to check whether the location of the wiring violates the separation distance. The objects to be extracted are the pins of the lower cell, the pins and metal of the current layer, and it is assumed that there is virtual metal on both sides of the cell. Afterwards, wiring position information and numerical spacing information between wires are extracted. Specifically, as shown in (a) of Figure 6, the location information to be extracted is 2 outer positions and 3 subcell metal and pin positions, so there are a total of 5 locations.

Once the information has been extracted, it is determined whether the extracted separation value information satisfies the design rules. (S230).

If the design rule is not satisfied, whether the metal in question is a pin intended to connect to a cell higher than the corresponding layer is checked based on whether the pin is located on the outer side (S240).

Specifically, according to (b) of FIG. 6, the number of times to compare whether to place a cut layer or not is performed a total of 6 times (comparisons 1 to 6). As a result of comparison, the cut layer is not placed in comparisons 5 and 6 because a sufficient separation distance is secured, but in comparisons 1 to 4, the separation distance is smaller than the preset distance at which the cut layer must be placed, so (c) in Figure 6 Cut layers must be placed for the four areas as shown.

However, as it is a pin area on the outside according to comparisons 3 and 4, a cut layer is not placed because it can be used later for connection with other cells, and it is not for pin use like comparisons 1 and 2, and the separation distance is Violating metal can have a cut layer placed on it. (S250)

In S250, in the outermost areas such as comparisons 1 and 2, a cut layer may or may not be placed because it is not known how other cells will be attached, but in the present invention, for design stability and automation, in this case Place the cut layer assuming the worst case scenario. Therefore, as shown in (d) of FIG. 6, the cut layer is performed twice in the lower cell area.

Since this process in FIG. 6 is performed one by one at each wiring interval, it is repeated until the inspection of all wiring is completed. (S260) Therefore, when the cut layer arrangement for the lower cell area is completed as shown in FIG. 6, the cut layer arrangement for the upper cell area is performed according to FIG. 7.

The basic process for placing the cut layer in the upper cell area is the same as in Figure 6, but assuming that lower cells are included and that the cut layer placement in the lower cell area has already been completed, the cut layer for the upper cells is Only placement is done. That is, in Figure 7, the separation distance between all metals is not compared, but only the lower cell-PIN, upper cell-PIN, upper cell-metal, and outer shell of the cell are compared.

Specifically, as shown in (a) of FIG. 7, the objects of comparison in the upper cell area are the pins of the lower cell (pins 3 to 7), the metal of the upper cell (metal 8 and metal 9), A total of 10 targets are selected for comparison, including the pins of the upper cells (fill 10) and the outer regions (numbers 1 and 2).

Afterwards, as shown in (b) of FIG. 7, the spacing between metals is compared and the number of comparisons is 11 (from 7 comparisons to 17 comparisons). (The number of comparisons 1 to 6 is the number of comparisons made in the lower area and has already been completed in Figure 6)

However, since the cut layer is not placed in the pin area and the outer area of the cell, only one cut layer placement step is required, as shown in (c) of FIG. 7. Therefore, ultimately, according to the present invention, 17 comparisons and 3 placement processes are performed. Below, these features will be described in comparison with the prior art.

Figures 8 to 11 are diagrams comparing the number of times required to be compared to place a cut layer according to the prior art and the number of times the cut layer is placed. Figure 8 shows the number of times a cut layer is placed based on one area according to the prior art. Figure 9 is a diagram showing the number of comparisons and the number of cut layer arrangements for arranging cut layers based on four areas according to the prior art. Figure 10 is a diagram showing the number of comparisons and the number of cut layer arrangements for arranging cut layers based on one area according to the present invention, and Figure 11 is a diagram showing the number of comparisons for arranging cut layers based on four areas according to the present invention. This is a diagram showing the number of comparisons and the number of cut layer placements.

Referring to FIG. 8, in the case of the prior art, since the spacing between metals had to be compared one by one, a total of 13 comparisons had to be made as shown in (a) of FIG. 8, and accordingly, (b) of FIG. 8 ), it can be seen that the cut layers were placed in five areas where the minimum distance between metals is small.

And since the general design layout has the characteristic of expanding the same area, as shown in Figure 9, when there are four areas in Figure 8, comparing the number of comparisons in the total area and the number of placements, the number of comparisons is In the case of , a total of 62 comparisons are made, including 13 in each area and 10 comparisons between areas. And in the case of the number of cut layer placements, the 5 in each area are multiplied by 4 and performed 20 times in total.

On the other hand, looking at the number of times the cut layer area is compared and arranged according to the present invention, if the number of comparisons in the lower cell area is first determined, as shown in (a) of Figure 10, the total number of comparisons in the lower cell area is 6 times. It's rough.

Afterwards, as shown in the figure, since five identical subcells are sequentially connected in parallel in the subcell area, no further comparisons are made within the internal area of one subcell itself (the subcell that was first compared (since the information can be used as is), compare the separation distances between lower cells. Based on the drawing, a total of 6 comparisons are made (red numbers 7 to 12), so the total number of comparisons in the area where the subcell is placed is 12.

As for the placement of the cut layer in the subcell area, in the case of comparisons 5 and 6, the separation distance is longer than the preset distance at which the cut layer must be placed (in this case, it is referred to as the second separation distance), and the separation distance between the metals is Because the distance is sufficiently secured, no cut layers are placed, and comparisons 3 and 4 are pin areas, so no cut layers are placed.

In the outermost areas such as comparisons 1 and 2, a cut layer may or may not be placed because it is not known how other cells will be attached, but in the present invention, for design stability and automation, in this case, the worst case situation Place the cut layer assuming that. Therefore, as shown in (a) of FIG. 10, the cut layer is performed twice in the lower cell area.

And when the number of comparisons and the arrangement of the cut layer in the lower cell area are completed, comparisons in the upper cell area are performed a total of 5 times (numbers 13 to 17 in red), as shown in (b) of FIG. 10. Concluding the comparison in the cell area, in the case of cut layers, comparisons 13, 15, 16, and 17 have a separation distance longer than the preset distance at which the cut layer must be placed, so the cut layer is not placed. As in comparison number 14, a cut layer is placed in an area where the separation distance between metals is smaller than the preset distance (in this case, it refers to the first separation distance).

Therefore, the total number of comparisons is 17, with 6 in the lower cell area and 11 in the upper cell area, and the cut layer is executed a total of 3 times.

And, as in Figure 11, when a total of 4 cells in Figure 8 are attached (the cells in Figure 8 are referred to as mid-unit cells), the total number of comparisons only needs to compare the distances of the pins in Figure 10 (already in the middle unit). Since the cut layer has been completed for the cells, you can proceed with comparisons 18 to 23. Therefore, the total number of comparisons is 23, and in the case of the cut layer, the cut layer has already been completed inside the cells of the middle unit, and the cells only need to be placed by judging the spacing between the pins in FIG. 10. The comparison area in FIG. 11 All separation distances in are greater than the separation distance at which a cut layer must be placed, so there is no need to place a cut layer. Therefore, the total number of cut layer placements is 3.

Therefore, when comprehensively comparing the results according to FIG. 9 according to the prior art and the results according to FIG. 11 according to the present invention, the advantage of the present invention is that the number of comparisons and placement numbers for arranging the cut layer is reduced compared to the prior art in the same environment. This exists. Therefore, there is an advantage of being able to place cut layers more efficiently and quickly than the prior art, and because this method can be implemented with a program algorithm, there is an advantage of being able to automatically design semiconductor circuits with a computer, unlike the prior art. do.

Figure 12 is a diagram schematically showing a semiconductor integrated circuit manufacturing system according to an embodiment of the present invention.

Referring to FIG. 12, the semiconductor integrated circuit manufacturing system 100 according to an embodiment of the present invention includes a schematic circuit generation unit 110, a layout generation unit 120, a mask manufacturing unit 130, and a semiconductor integrated circuit formation. It may include unit 140. The schematic circuit generation unit 110, the layout generation unit 120, the mask manufacturing unit 130, and the semiconductor integrated circuit forming unit 140 may each be independent devices.

The schematic circuit creation unit 110 may generate a schematic circuit. The schematic circuit generated by the schematic circuit creation unit 110 may be transmitted to the layout creation unit 120.

The layout creation unit 120 includes a design area separation tool (1210), a layout design tool (1220), a layout decomposition tool (1230), and a design rule check tool (design rule check). tool, 1240).

The layout created by the layout creation unit 120 may be transmitted to the mask manufacturing unit 130.

The mask manufacturing unit 130 may manufacture a mask using the generated layout. The mask manufacturing unit 130 may perform OPC of the generated layout. The mask manufacturing unit 130 can manufacture a mask for each color of the generated layout. The mask manufactured by the mask manufacturing unit 130 may be delivered to the semiconductor integrated circuit forming unit 140.

The semiconductor integrated circuit forming unit 140 may form a semiconductor integrated circuit on a wafer through a photo-lithography process using the fabricated mask.

13 is a diagram schematically showing a semiconductor module including a semiconductor integrated circuit manufactured using a design method according to an embodiment of the present invention.

The semiconductor module 200 may include a controller 210 and a memory 220. For example, the semiconductor module 200 may be a memory stick card, smart media card (SM), secure digital card (SD), or minisecuredigital card. : It may be a memory card such as a mini SD) and a multimedia card (MMC).

The controller 210 may be electrically connected to the memory 220. The memory 220 may exchange electrical signals with the controller 210. For example, the memory 220 may transmit data according to a signal from the controller 210.

The controller 210 and the memory 22000 may include a semiconductor integrated circuit manufactured using a design method according to an embodiment of the present invention. Accordingly, the production efficiency of the semiconductor module 200 according to an embodiment of the present invention can be improved.

Figure 14 is a diagram showing an electronic system including a semiconductor integrated circuit manufactured using a design method according to an embodiment of the present invention.

The electronic system 300 may include a processor 310, a memory device 320, a storage device 330, a power supply 340, and an input/output device 350. The electronic system 300 may further include ports capable of communicating with electronic devices such as a video card, sound card, memory card, USB device, etc.

The processor 310 may be a microprocessor or a central processing unit (CPU). The processor 310 connects the memory device 320, the storage device 330, and the input/output device 350 through a bus 2600 such as an address bus, a control bus, and a data bus. ) can communicate with. The processor 310 may be connected to an expansion bus, such as a Peripheral Component Interconnect (PCI) bus.

The memory device 320 may store data necessary for the operation of the semiconductor integrated circuit manufacturing system 100. For example, the memory device 320 may include at least one of DRAM, mobile DRAM, SRAM, PRAM, FRAM, RRAM, and MRAM. You can.

The storage device 330 may include an external storage device such as a solid state drive, hard disk drive, and CD-ROM. The power supply 340 may supply the operating voltage necessary for the operation of the corresponding electronic system 300. The input/output device 350 may include input means such as a keyboard, keypad, mouse, etc. The input/output device 350 may include output means such as a printer, display, etc.

The processor 310, memory device 320, storage device 330, power supply 340, and input/output device 350 may include a semiconductor integrated circuit manufactured using a design method according to an embodiment of the present invention. there is. Accordingly, the production efficiency of the semiconductor module 200 according to an embodiment of the present invention can be improved.

So far, we have looked at the semiconductor circuit design method and device according to the present invention through the drawings.

The semiconductor integrated circuit design method according to one embodiment automatically calculates the point where the cut layer is needed and then places the cut layer, unlike the existing conventional technology in which the ray user directly finds and places the point where the cut layer is needed. The time and cost required to deploy can be reduced, and thus there is an advantage in that the entire semiconductor process can be carried out more efficiently.

The device described above may be implemented with hardware components, software components, and/or a combination of hardware components and software components. For example, devices and components described in embodiments may include, for example, a processor, a controller, an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field programmable array (FPA), It may be implemented using one or more general-purpose or special-purpose computers, such as a programmable logic unit (PLU), microprocessor, or any other device capable of executing and responding to instructions. A processing device may perform an operating system (OS) and one or more software applications that run on the operating system. Additionally, a processing device may access, store, manipulate, process, and generate data in response to the execution of software. For ease of understanding, a single processing device may be described as being used; however, those skilled in the art will understand that a processing device includes multiple processing elements and/or multiple types of processing elements. It can be seen that it may include. For example, a processing device may include multiple processors or one processor and one controller. Additionally, other processing configurations, such as parallel processors, are possible.

Software may include a computer program, code, instructions, or a combination of one or more of these, which may configure a processing unit to operate as desired, or may be processed independently or collectively. You can command the device. Software and/or data may be used on any type of machine, component, physical device, virtual equipment, computer storage medium or device to be interpreted by or to provide instructions or data to a processing device. It can be embodied in . Software may be distributed over networked computer systems and stored or executed in a distributed manner. Software and data may be stored on one or more computer-readable recording media.

As described above, although the embodiments have been described with limited examples and drawings, various modifications and variations can be made by those skilled in the art from the above description. For example, the described techniques are performed in a different order than the described method, and/or components of the described system, structure, device, circuit, etc. are combined or combined in a different form than the described method, or other components are used. Alternatively, appropriate results may be achieved even if substituted or substituted by an equivalent. Therefore, other implementations, other embodiments, and equivalents of the claims also fall within the scope of the claims described below.

100: Semiconductor circuit design device
110: Schematic circuit creation unit
120: Layout creation unit
130: Mask manufacturing unit
140: Semiconductor integrated circuit forming unit

Claims (8)

Preparation of design area containing standard cells;
A cell area division step of dividing the design area into an upper cell area and a lower cell area;
A lower cut layer arrangement step of arranging a cut layer between the lower metals based on the positions and separation distances of the lower metals in the lower cell area;
Characterized in that it includes; an upper cut layer placement step of arranging a cut layer between metals in the upper cell area based on the placement position of the cut layer placed in the lower cell area,
Semiconductor integrated circuit design method. According to clause 1,
The sub-cut layer placement step is,
When the first separation distance between the outer line of the lower cell area and the upper lower metals is smaller than a preset distance, comprising arranging a cut layer at the first distance,
Semiconductor integrated circuit design method. According to clause 2,
The sub-cut layer placement step is,
When the first separation distance between the outer line of the lower cell area and the upper lower metals is greater than a preset distance, not arranging a cut layer at the first distance, According to clause 3,
The sub-cut layer placement step is,
Characterized in that it includes the step of not placing a cut layer in the PIN area in the lower cell area,
Semiconductor integrated circuit design method. According to clause 4,
The sub-cut layer placement step is,
When a plurality of sub-cell areas exist within the standard cell, arranging the cut layer of the sub-cell area in which the sub-cut layer is placed first, and arranging the cut layer in the same manner to other sub-cell areas, comprising: Characterized by,
Semiconductor integrated circuit design method. According to clause 5,
The upper cut layer placement step is,
When the second separation distance between the outer line between the upper metals of the upper cell area and the upper metals is smaller than a preset distance, the step of placing a cut layer at the second separation distance. ,
Semiconductor integrated circuit design method. According to clause 6,
The upper cut layer placement step is,
When the second separation distance between the outer line between the upper metals of the upper cell area and the upper metals is greater than a preset distance, not arranging the cut layer at the second separation distance. doing,
Semiconductor integrated circuit design method. The design area including the standard cell is divided into an upper cell area and a lower cell area, a cut layer is placed between the lower metals based on the position and separation distance of the lower metals in the lower cell area, and the lower cell area is divided into a lower cell area. a layout creation unit that arranges a cut layer between metals in the upper cell area based on the arrangement position of the cut layer arranged in the area; and
A semiconductor circuit design device comprising a mask manufacturing unit that creates a mask based on the layout generated from the layout.