JP2008171399A - Semiconductor device design method, semiconductor device design system, and computer program - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To extract parasitic capacitance and parasitic resistance of a layout of a reduced process product without newly designing the layout data of the reduced process product. <P>SOLUTION: In the extraction of a parasitic parameter of the reduced process product, the layout data of an existing product are prepared at first and the layout data are taken into a layout edition tool 55 (S101). Then, a mask region to be excluded from parasitic parameter extraction is specified (S102) for the layout data of the existing product. When the specification of the mask region is completed, wiring conversion processing is executed in response to a user's instruction (S103 to S108). In the processing, a wiring portion in an actual wiring layer present in the mask region is converted into a wiring portion in a virtual wiring layer. Then LPE processing for the converted layout is executed to extract the parasitic parameter of the whole layout or a specific part (S109). <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device design method, a semiconductor device design system and a computer program, and more particularly to a method, system and computer program suitable for layout design and verification of a reduced process product.

  In designing a semiconductor device using a computer (CAD system), a logic design for designing a gate-level logic circuit is performed, and then a layout design is performed based on a netlist (information indicating the connection relationship of logic elements). Is called. When the layout is determined, various verifications are performed as to whether the layout satisfies a design rule and whether a device having the layout operates normally. As one of the processes performed in the verification process, LPE (Layout Parameter Extraction) is known (see, for example, Patent Document 1).

  In the LPE processing, extraction of parasitic resistance and parasitic capacitance (hereinafter referred to as “parasitic parameter”) related to the wiring in the obtained layout is performed. Such a parasitic parameter is a parameter that can be determined only after the layout is obtained, and is not included in the above-described netlist. Therefore, the extracted parasitic parameters are added to the above-described net list, and as a result, a net list to which the parasitic parameters are added (hereinafter referred to as “net list with parasitic parameters”) is created. In other words, a netlist with parasitic parameters can be obtained by inputting the netlist and layout data to a tool for executing LPE (LPE tool).

  Thereafter, delay verification and timing verification are performed on the device under design using the obtained netlist with parasitic parameters. If the result of the verification is “fail”, the layout design process is executed again. Then, the LPE process is executed again and the verification is executed again. The above process is repeated until the layout "passes" verification. When the result of the verification is “pass”, final layout data is determined.

There are various other techniques related to layout design. For example, Patent Document 2 discloses a method of reducing LSI design time and design cost in designing an LSI in which circuits having different signal amplitudes are mounted in the same chip. In this method, LEF information is converted from a real wiring layer or a terminal layer of a chip and each function block into an independently defined virtual wiring layer, and automatic wiring is performed in the virtual wiring layer based on the converted information and circuit connection information. The number of automatic wiring is reduced by converting the automatic wiring information into an actual wiring layer or a terminal layer.
JP 2006-209702 A JP-A-11-265941

  In semiconductor devices, it is common to design a reduced process product of an existing product. In this case, it is only necessary to design the layout of the portion that needs to be modified while following the layout of the existing product, so that efficient layout design can be performed.

  However, the LPE process for the layout of the reduced process product can be performed only after the layout data of the reduced process product is newly created. As described above, LPE is a process for extracting a parasitic parameter, and the parasitic parameter is a parameter that can be determined only after a layout is obtained. Therefore, even when designing a reduced process product based on the layout of an existing product. However, it is not possible to extract the parasitic capacitance and the parasitic resistance for performing the delay verification / timing verification only after designing the target layout data. In other words, in the conventional design method, the parasitic parameters already required in the layout of existing products are not utilized, and it takes time to pass verification from layout design due to an increase in the number of design iterations, which is inefficient. It was designed.

  Therefore, an object of the present invention is to efficiently design using a layout of an existing product without designing a new layout of the reduced process product when designing a reduced process product of the existing product. The object is to provide a method for designing a semiconductor device.

  The object of the present invention is to provide a mask region setting step for setting a mask region on a layout of a semiconductor device, a parasitic parameter changing step for setting a parasitic parameter of a wiring portion in the mask region to zero, and specifying the entire layout or layout. And a parasitic parameter extracting step of extracting a parasitic parameter of the part. This is achieved by a method for designing a semiconductor device.

  According to the present invention, when extracting the parasitic parameters of the layout of the reduced process product using the layout data of the existing product, the mask area is designated on the layout screen, and the parasitic parameter of the wiring portion in the mask area is set to zero. Thus, the parasitic parameters of the layout of the reduced process product can be extracted without newly designing the layout of the reduced process product. Therefore, the time required for layout design and verification can be shortened.

  In the present invention, the parasitic parameter changing step includes a virtual wiring layer generating step for generating a virtual wiring layer corresponding to the actual wiring layer of the semiconductor device, a parasitic parameter defining step for defining the parasitic parameter of the virtual wiring layer as zero, It is preferable to include a wiring layer conversion step for converting a wiring portion in the mask region of the wiring of the wiring layer into a wiring portion of the virtual wiring layer. In this case, the parasitic parameter changing step includes a wiring length correction step for extending the wiring portion of the virtual wiring layer by a predetermined length, an end of the wiring portion of the virtual wiring layer, and an end of the cut wiring of the actual wiring layer. It is preferable to further include a wiring regeneration step for making continuous wiring by connecting the parts with virtual contact plugs and a definition step for defining the parasitic parameters of the virtual contact plugs as zero.

  Normally, since the parasitic parameters are defined for each wiring layer, different parasitic parameters cannot be defined for different planar regions in the same wiring layer. However, by defining a new virtual wiring layer separately from the actual wiring layer, and setting the parasitic capacitance and parasitic resistance of the virtual wiring layer to zero, the parasitic capacitance of the wiring portion in a specific area of the actual wiring layer and Parasitic resistance can be handled as zero.

  In the present invention, it is preferable that the virtual wiring layer generation step generates a plurality of virtual wiring layers corresponding to each real wiring layer when there are a plurality of real wiring layers. According to this, handling of the wiring part before and after conversion can be easily understood.

  The object of the present invention is also provided with a layout editing tool for editing layout data of a semiconductor device, and a parasitic parameter extracting tool for extracting parasitic parameters of the entire layout of the semiconductor device or a specific part of the layout. A semiconductor device design system comprising: a mask region setting unit that sets a mask region on a layout of a semiconductor device; and a parasitic parameter changing unit that sets a parasitic parameter of a wiring portion in the mask region to zero. Is also achieved.

  The above object of the present invention is also to provide a computer with a mask region setting step for setting a mask region on the layout of the semiconductor device, a parasitic parameter changing step for setting the parasitic parameter of the wiring portion in the mask region to zero, and the entire layout. Alternatively, it is also achieved by a computer program for executing a parasitic parameter extracting step for extracting a parasitic parameter of a specific part of the layout.

  As described above, according to the present invention, when extracting the parasitic parameters of the layout of the reduced process product using the layout data of the existing product, the layout data in which the wiring length of the signal line and the power line is shortened is newly designed. And parasitic parameters can be obtained. Therefore, an efficient layout design can be realized.

  Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

  FIG. 1 is a schematic diagram for explaining a method for designing a semiconductor device according to a preferred embodiment of the present invention, and shows a planar layout of the semiconductor device.

  As shown in FIG. 1A, a layout 20 of a semiconductor device of a reduced process product (for example, 0.10 μm process) is designed based on a layout 10 of a semiconductor device of an existing product (for example, 0.13 μm process). Think. In the layouts 10 and 20 of the respective semiconductor devices shown in FIG. 1A, functional blocks and wirings for electrically connecting the functional blocks are arranged on the semiconductor substrate 11. Examples of the wiring include a signal line, a power supply line, and a ground line. As for wiring, a multilayer wiring structure in which metal wirings are stacked in multiple layers is adopted. In the present embodiment, a region 12 provided along the longitudinal direction of the semiconductor substrate 11 is a bus wiring region, and a region 13 is a pad arrangement region. A region 14 indicated by diagonal lines indicates a reduced portion due to a layout change.

  In the design of such a reduced process product, when extracting the parasitic capacitance and the parasitic resistance of the entire layout or a specific portion of the reduced process product, as shown in FIG. , And a mask region 15 is set on the layout 10 and the parasitic capacitance and parasitic resistance of the wiring in the mask region 15 are regarded as zero, thereby realizing a layout equivalent to a reduced process product.

  FIG. 2 is a schematic diagram for explaining a method of regarding the parasitic capacitance and the parasitic resistance of the wiring in the mask region 15 as zero.

  As shown in FIG. 2, in this method, a virtual wiring layer 32 is prepared separately from the actual metal wiring layer (real wiring layer) 31. At this time, both the dielectric constant ε and resistivity ρ of the wiring in the virtual wiring layer 32 are defined as zero. Thereafter, in the metal wiring 33 of the actual wiring layer 31, the wiring part 33a in the mask region 15 is converted into the wiring part 33b of the virtual wiring layer 32, and both ends of the wiring part 33b are stretched by a predetermined length L. . Further, both ends of the wiring portion 33b are connected to the ends of the cut metal wiring 33 of the actual wiring layer 31 via the virtual contact plugs 35 of the minimum size, so that the metal wiring 33 of the actual wiring layer 31 is a virtual wiring. It is converted into wiring via the layer 32.

  Usually, on the LPE tool, the parasitic parameter is defined for each wiring layer, and the wiring parasitic parameter has the same value everywhere in the same layer. In other words, different parasitic parameters cannot be defined for different planar regions in the same wiring layer. However, by newly defining a virtual wiring layer separately from the actual wiring layer and setting the parasitic capacitance and parasitic resistance of the virtual wiring layer to zero, wiring in a specific region (mask region 15) of the actual wiring layer is set. The parasitic capacitance and parasitic resistance of the part can be handled as zero.

  FIG. 3 is a schematic diagram for explaining the case of a multilayer wiring structure.

  As shown in FIG. 3, when there are a plurality of real wiring layers, the same number of virtual wiring layers are prepared. For example, when the actual wiring layer is composed of the first to third wiring layers 31A, 31B, and 31C, the first to third virtual wiring layers 32A, 32B, and 32C are prepared, and the first wiring layer 31A The wiring portion 33a is converted to the wiring portion 33b of the first virtual wiring layer 32A, the wiring portion 33a of the second wiring layer 31B is converted to the wiring portion 33b of the second virtual wiring layer 32B, and the third wiring layer The wiring portion 33a of 31C is converted into the wiring portion 33b of the third virtual wiring layer 32C. Therefore, the handling of the wiring part before and after the conversion can be easily understood.

  FIG. 4 is a schematic diagram for explaining a case where wirings in different actual wiring layers intersect.

  As shown in FIGS. 4A and 4B, there is a particular problem even when the wiring in the first wiring layer 31A and the wiring in the second wiring layer 31B intersect in the mask region 15. The wiring portion 33a of the first wiring layer 31A is converted into the wiring portion 33b of the first virtual wiring layer 33A, and the wiring portion of the second wiring layer 31B becomes the wiring portion 33b of the second virtual wiring layer 33B. The converted relationship where the wiring portions 33a and 33a intersect, that is, the positional relationship in the actual wiring layer is also maintained in the virtual wiring layer after conversion.

  Next, a system for specifically realizing the above design method will be described in detail.

  FIG. 5 is a block diagram showing a configuration of a semiconductor device design system according to the present invention.

  As shown in FIG. 5, the semiconductor device design system 50 is realized by a computer system (CAD; Computer Aided Design), and includes a storage device 51, an arithmetic processing device 52, an input device 53, a display device 54, a layout. An editing tool 55, a parameter extraction tool (LPE tool) 56, and a layout verification tool 57 are provided.

  The storage device 51 is realized by, for example, a hard disk device, and is configured to store an RC library 61, a net list 62, layout data 63, a net list with parasitic parameters 64, and wiring length data 65. The RC library 61 is a library that is referred to at the time of the LPE process, and shows the wiring parasitic parameters (RC parameters). The net list 62 is data indicating a connection relationship of logic elements in the semiconductor device under design. The layout data 63 is data indicating the layout of the semiconductor device under design. The layout data 63 is created by a layout editing tool (not shown) and stored in the storage device 51. The net list with parasitic parameters 64 is a net list to which a parasitic RC obtained by an LPE process described later is added. The wiring length data 65 is data indicating the wiring length of each wiring in the layout.

  The arithmetic processing unit 52 can access the storage device 51 and executes various processes in accordance with instructions from the layout editing tool 55, the LPE tool 56, and the layout verification tool 57. Examples of the input device 53 include a keyboard and a mouse. A user (designer) can input various data and commands using the input device 53 while referring to the information displayed on the display device 54.

  The layout editing tool 55, the LPE tool 56, and the layout verification tool 57 are computer programs (software products) executed by the arithmetic processing unit 52.

  The layout editing tool 55 has a function of creating and editing layout data, and can enlarge and move the screen, add and copy, delete, move, and change the shape of the figure. The method of inputting data to the layout editing tool 55 can be roughly divided into two methods. One is a case where an output result of an automatic layout tool (not shown) is input. The layout data is taken into the layout editing tool 55 via a network or a magnetic medium. At this time, it is necessary to convert the data into a data format that can be accepted by the layout editing tool 55 in advance. Another data input method is manual input. The designer inputs the coordinate point sequence of the figure with a mouse or the like while looking at the display. The edited layout data is stored in the storage device 51. The layout editing tool 55 can also specify a mask area. By specifying the mask area, the virtual wiring layer corresponding to the actual wiring layer can be automatically set, and the wiring portion can be converted.

  The LPE tool 56 has a function of constructing the RC library 61 and a function of executing LPE processing on the layout data 63 stored in the storage device 51. The layout verification tool 57 has a function of performing operation verification (delay verification, timing verification) of the designed circuit. When a design error is found using the layout verification tool 57, the error portion is corrected using the layout editing tool 55.

  FIG. 6 is a flowchart showing the parasitic parameter extraction operation by the semiconductor device design system 50.

  As shown in FIG. 6, in extracting parasitic parameters of a reduced process product, layout data (see FIG. 1A) of an existing product is first prepared, and this layout data is taken into the layout editing tool 55 (S101). The captured layout data is displayed on the screen of the display device 54.

  Next, a mask region to be excluded from parasitic parameter extraction is specified for the layout data of the existing product (S102). In this case, upon receiving an instruction from the user, the normal layout editing mode is switched to the mask area designation mode, and the mask area can be designated. The mask area designation operation is the same as a normal layout editing operation, and can be performed by operating a pointer on the screen to select and determine a desired range on the layout.

  When the specification of the mask area is completed, a wiring conversion process is executed in response to an instruction from the user (S103 to S108). By this processing, the wiring portion of the actual wiring layer existing in the mask region is converted into the wiring portion in the virtual wiring layer. The wiring conversion is as described with reference to FIG. That is, a virtual wiring layer corresponding to the actual wiring layer is generated (S103), and the parasitic capacitance and parasitic resistance of the virtual wiring layer are set to zero (S104). Next, after the wiring portion of the actual wiring layer in the designated mask region is converted to the wiring portion in the virtual wiring layer (S105), wiring length correction is performed to extend both ends of this wiring portion (S106). Further, a virtual contact plug of the minimum size that connects both ends of the wiring portion and the end of the cut wiring of the actual wiring layer is generated (S107), and the parasitic capacitance and parasitic resistance of the virtual contact plug are set to zero (S108). ). Through the above wiring conversion process, the wiring in the actual wiring layer is converted into the wiring via the virtual wiring layer.

  After that, by executing the LPE process on the converted layout, parasitic parameters of the entire layout or a specific portion are extracted (S109). The parasitic parameters obtained in this way are used to create a netlist with parasitic parameters, and are used for verification by the layout verification tool 57.

  As described above, according to the present embodiment, when designing the circuit layout of the reduced process using the circuit layout of the existing product, the parasitic capacitance of the wiring and the wiring capacitance are separated from the actual wiring layer of the existing product layout. By preparing a virtual wiring layer in which both parasitic resistances are defined as zero, specifying a mask area on the circuit layout of the existing product, and moving the wiring part in this mask area to the corresponding virtual wiring layer, The parasitic capacitance and resistance of the entire reduced process product layout or a specific part can be determined very easily. Therefore, the time required from the layout design to passing the verification can be greatly shortened, and the development period can be shortened by reducing the number of design iterations.

  The present invention is not limited to the above embodiments, and various modifications can be made without departing from the spirit of the present invention, and these are also included in the scope of the present invention. Needless to say.

  For example, in the above embodiment, the parasitic capacitance and the parasitic resistance are extracted as the parasitic parameters of the wiring and are excluded from the extraction target by setting the mask region. However, the present invention is limited to such a case. Instead of this, either one of parasitic capacitance and parasitic resistance may be targeted.

FIG. 1 is a schematic diagram for explaining a method for designing a semiconductor device according to a preferred embodiment of the present invention, and shows a planar layout of the semiconductor device. FIG. 2 is a schematic diagram for explaining a method of regarding the parasitic capacitance and the parasitic resistance of the wiring in the mask region 15 as zero. FIG. 3 is a schematic diagram for explaining the case of a multilayer wiring structure. FIG. 4 is a schematic diagram for explaining a case where wirings in different actual wiring layers intersect. FIG. 5 is a block diagram schematically showing the configuration of the semiconductor device design system according to the present invention. FIG. 6 is a flowchart showing the parasitic parameter extraction operation by the semiconductor device design system 50.

Explanation of symbols

DESCRIPTION OF SYMBOLS 10 Layout of semiconductor device of existing product 11 Semiconductor substrate 12 Bus wiring region 13 Pad layout region 14 Reduced portion 15 by layout change Mask region 20 Layout of semiconductor device 31 of reduced process product Actual wiring layer 31A First wiring layer 31B Second Wiring layer 31C third wiring layer 32 virtual wiring layer 32A first virtual wiring layer 32B second virtual wiring layer 32C third virtual wiring layer 33 metal wiring 33a wiring portion 33b wiring portion 33c wiring portion 35 virtual contact plug 50 Semiconductor Device Design System 51 Storage Device 52 Arithmetic Processing Device 53 Input Device 54 Display Device 55 Layout Editing Tool 56 LPE Tool 57 Layout Verification Tool 61 RC Library 62 Net List 63 Layout Data 64 Parasitic Parameter Net List 65 and Wiring Length Device Data

Claims (7)

A mask region setting step for setting a mask region on the layout of the semiconductor device;
A parasitic parameter changing step for setting the parasitic parameter of the wiring portion in the mask region to zero; and
And a parasitic parameter extracting step of extracting a parasitic parameter of the entire layout or a specific portion of the layout. The parasitic parameter changing step includes:
A virtual wiring layer generation step of generating a virtual wiring layer corresponding to the real wiring layer of the semiconductor device;
A parasitic parameter defining step for defining the parasitic parameter of the virtual wiring layer as zero;
2. The method of designing a semiconductor device according to claim 1, further comprising: a wiring layer conversion step of converting a wiring portion in the mask region of the wiring of the real wiring layer into a wiring portion of the virtual wiring layer. . The parasitic parameter changing step includes:
A wiring length correcting step for extending the wiring portion of the virtual wiring layer by a predetermined length;
A wiring regeneration step for making continuous wiring by connecting the end of the wiring portion of the virtual wiring layer and the end of the cut wiring of the real wiring layer with a virtual contact plug;
The method of designing a semiconductor device according to claim 2, further comprising a defining step of defining a parasitic parameter of the virtual contact plug as zero. The virtual wiring layer generation step includes
4. The method of designing a semiconductor device according to claim 2, wherein when there are a plurality of real wiring layers, a plurality of virtual wiring layers corresponding to each real wiring layer are generated.   5. The method of designing a semiconductor device according to claim 1, wherein the parasitic parameter is a parasitic capacitance, a parasitic resistance, or both. A layout editing tool for editing the layout data of the semiconductor device;
A parasitic parameter extraction tool for extracting a parasitic parameter of the entire layout of the semiconductor device or a specific part of the layout,
The layout editing tool is
A mask region setting unit for setting a mask region on the layout of the semiconductor device;
A semiconductor device design system comprising: a parasitic parameter changing unit that sets a parasitic parameter of a wiring portion in the mask region to zero. On the computer,
A mask region setting step for setting a mask region on the layout of the semiconductor device;
A parasitic parameter changing step for setting the parasitic parameter of the wiring portion in the mask region to zero; and
A computer program for executing a parasitic parameter extracting step of extracting parasitic parameters of the entire layout or a specific portion of the layout.

Images