JP2009003723A - Layout design method of semiconductor integrated circuit, automatic layout design device for semiconductor integrated circuit, layout design assistance system of semiconductor integrated circuit, photomask, photomask manufacturing method, semiconductor integrated circuit, semiconductor integrated circuit manufacturing method, control program, and readable storage medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To perform a freeze-silicon ECO so as to satisfy timing restrictions in the logic change of mask layout. <P>SOLUTION: A direction range of a spare cell to be replaced is detected by a spare cell direction range detection block 22, and a distance range satisfying timing restrictions is detected within the direction range by a timing restriction-satisfying range detection block 23. When no spare cell exists within the distance range satisfying the timing restrictions, an instance closest to a spare cell or a connection object is detected among used instances of the same kind as spare cells by a used replacement cell instance detection block 24, and both terminals of the detected instance are disconnected by a used replacement instance replacing block 25, and the instance is used instead of a spare cell. Disconnected terminal parts (unused circuit parts) are to be replaced to set a connection object again by a reference terminal coordinate resetting block 26, and each process is repeated one or a plurality of times. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  In the layout design of a large-scale semiconductor integrated circuit (LSI) or the like, the present invention is a method of performing placement and routing processing only on a place where logic has been changed (hereinafter referred to as ECO). Replacement redundant cells (hereinafter referred to as spare cells) to be used at the time of change are arranged in advance, and the mask layer in the manufacturing process is changed for the wiring layer and contact layer using the arrangement elements (hereinafter referred to as instances). In the ECO method (hereinafter referred to as “freeze silicon ECO”) in which the logic is changed, the timing constraint is satisfied when the timing constraint cannot be satisfied by the static timing analysis executed in the design apparatus. Layout design method for semiconductor integrated circuit that performs freeze silicon ECO Semiconductor integrated circuit layout design assisting system used in the design method, semiconductor integrated circuit automatic layout designing apparatus equipped with the layout design assisting system, photomask having a mask pattern generated using the automatic layout designing apparatus, Photomask manufacturing method for manufacturing this photomask, semiconductor integrated circuit manufactured using photomask, semiconductor integrated circuit manufacturing method for manufacturing semiconductor integrated circuit using photomask, and layout design method for semiconductor integrated circuit The present invention relates to a control program for causing a computer to execute each of the steps and a computer-readable readable storage medium storing the control program.

  In freeze silicon ECO used for layout design of this type of semiconductor integrated circuit (hereinafter referred to as LSI), as disclosed in Patent Document 1, for example, a spare cell (referred to as a circuit changing logic element in Patent Document 1). In general, timing constraints are not considered for its use.

  For example, in Patent Document 1, as shown in FIG. 15, in addition to the logic element 101 used for the actual logic operation, a circuit changing logic element 102 is arranged in each standard cell column, and the contact is made. Although a method of connecting each terminal to the power supply line 104 using the unit 103 is described, a method of selecting a spare cell and timing constraints when using the spare cell are not described.

  For example, in Patent Document 2, as shown in FIG. 16, a spare cell (referred to as a dummy element in Patent Document 2) is combined with a logic circuit using existing logic elements 111, 112, 113, and 114. ) A method of distributing spare cells by arranging 112a and 114a is described. In this method, it is possible to increase the possibility that a spare cell exists in a range that satisfies the timing constraint when performing the logic change, but the logic change that does not satisfy the timing constraint is still performed. There is no guarantee that there is nothing at all, and there is no description regarding a method of selecting a spare cell and timing constraints as in the case of Patent Document 1.

  At present, the software called “Astr” by Synopsys, one of the CAD tools that realizes the freeze silicon ECO function, has a logically changed input netlist (text data describing the connection relationship between elements). Is read, a difference between a netlist of the current layout as shown in FIG. 5 described later and an input netlist of freeze silicon ECO as shown in FIG. 6 described later is detected.

  As shown in FIGS. 5 and 7 to be described later, in the first column X1, the input of the NOR cell 201 is connected to the nets n1 and n2, and the output is connected to the net n3. In the second column X2, the input of the NAND cell 202 is connected to the nets n3 and n4, and the output is connected to the net n5. Further, in the third column X3, the input of the INV cell 203 is connected to the net n6, and the output thereof is connected to the net n7. Further, in the fourth column X4, the input of the NAND cell 204 is connected to the nets n8 and n9, and the output thereof is connected to the net n10. Further, in the fifth column X5, the input of the INV cell 205 is connected to the net n10, and its output is connected to the net n11. Further, in the sixth column X6, the input of the INV cell 208 is connected to the net n12, and its output is connected to the net n13. Further, in the seventh column X7, the input of the NAND cell 206 is connected to the nets n11 and n13, and the output thereof is connected to the net n14. Further, in the eighth column X8, the input of the NOR cell 209 is connected to the nets n15 and n16, and the output thereof is connected to the net n17. Further, in the ninth column X9, the input of the INV cell 210 is connected to the net n17, and its output is connected to the net n18. Further, in the 10th column X10, the input of the NOR cell 207 is connected to the nets n14 and n18, and the output thereof is connected to the net n19.

  Therefore, the output terminal 201b of the NOR cell 201 in the first column in FIG. 5 and the input terminal 202a of the NAND cell 202 in the second row are connected via the net n3, and the output terminals 204b and 5 of the NAND cell 204 in the fourth column are connected. The input terminal 205a of the INV cell 205 in the column is connected via the net n10, the output terminal 208b of the INV cell 208 in the sixth column and the input terminal 206a of the NAND cell 206 in the seventh column are connected via the net n13. , The output terminal 209b of the NOR cell 209 in the eighth column and the input terminal 210a of the INV cell 210 in the ninth column are connected via the net n17, and the output terminal 210b of the INV cell 210 in the ninth column and the NOR in the tenth column. It can be seen that the input terminal 207a of the cell 207 is connected via the net n18.

  On the other hand, in FIG. 6, X11 is inserted between the first column X1 and the second column X2, the input of the INV cell 211 of X11 is connected to the net n3, and the output is connected to the net nx3. Yes. The input of the NAND cell 202 of X2 is connected to the net nx3. Therefore, the output terminal 201b of the NOR cell 201 in the first column X1 and the input terminal 211a of the INV cell 211 in the second row X11 are connected via the net n3, and the output terminals 211b and 3 of the INV cell 211 in the second column X11 are connected. It can be seen that the input terminal 202a of the NAND cell 202 in the column X2 is connected via the net nx3.

  In short, the freeze silicon ECO function that changes the logic by changing only the layers after the metal in the automatic layout tool of each CAD vendor company targets only spare cells that are redundantly arranged in advance for replacement when the logic is changed. To do. For example, as shown in FIG. 17, when a cell to be used is not nearby among the arranged spare cells, it is inevitably necessary to use a far spare cell and can satisfy the timing constraint related to the clock signal. There are cases where this is impossible.

  In FIG. 7, in order to change the detected instance (corresponding to the instance of X11 in FIG. 6), an instance of a spare cell that is closest to the detected instance is used. However, even if the resulting layout does not satisfy the timing constraints, no special processing is performed to satisfy the timing constraints.

  If the timing constraint cannot be satisfied in the layout after the freeze silicon ECO is performed, the designer can manually change the input net list of the freeze silicon ECO to create an instance of a spare cell having a higher capacity. The timing constraints are adjusted using the logic, or the logic is rearranged so that only instances of spare cells existing nearby are used. However, regardless of which method is used, a great deal of labor is required manually. In this case, the number of elements used increases and the power consumption also increases, and further, it may lead to an increase in design period and human error due to complicated work performed manually. Furthermore, it is conceivable to change the layers other than the metal wiring layer and the contact layer without performing the freeze silicon ECO function. In that case, in the process of manufacturing the layers other than the metal wiring layer and the contact layer, a mask is used. Extra cost to recreate.

Furthermore, when using the spare cell instances to satisfy the timing constraint with a high probability by the effect more than that obtained by Patent Document 2, more spare cell instances are arranged on the layout in advance than in the prior art. A solution is also conceivable. However, at present, the ratio of the instance of the spare cell to the instance of the used cell is based on experience that it is within the range in which the instance of the spare cell can be arranged without increasing the chip area as compared with the case where only the instance of the used cell is arranged. The number of spare cell instances is more than the present, that is, the chip area is increased. An increase in chip area leads to a decrease in the number of chips formed on the wafer, leading to an increase in cost per chip.
Japanese Patent Laid-Open No. 2-7542 JP 2003-132110 A

  However, the above prior art has the following problems.

  As described above, in the prior art, the timing constraints are not satisfied when performing freeze silicon ECO as disclosed in Patent Document 1 or Patent Document 2 or as a software function that has already been commercialized. In addition, a layout that does not satisfy the timing constraint is output as it is. For this reason, the freeze silicon ECO is re-executed by manually changing the input net list of the freeze silicon ECO. Therefore, in these conventional techniques, there is a concern that power consumption increases, the design period becomes longer, and that artificial design work mistakes are induced.

  Further, when the layers other than the metal wiring layer and the contact layer are changed without performing the freeze silicon ECO function, there is a problem that the mask cost increases.

  Furthermore, in the case where more spare cell instances as disclosed in Patent Document 1 and Patent Document 2 are arranged than in the current situation, about 10% of the number of cells actually used in the circuit is arranged as spare cells. However, since the chip area increases, the cost of the chip increases, and there is a possibility that the timing constraint is not satisfied when the freeze silicon ECO function is performed.

  The present invention solves the above-mentioned conventional problem. Even in the arrangement of spare cells as in the prior art, the input netlist in freeze silicon ECO is automatically changed so as to satisfy the timing constraint, and the netlist is changed. Layout design method for semiconductor integrated circuit capable of performing freeze silicon ECO using semiconductor, automatic layout design apparatus for semiconductor integrated circuit using the same, layout design assisting system for semiconductor integrated circuit used therefor, and automatic layout design apparatus Photomask manufactured using the photomask, method for manufacturing photomask using the automatic layout design apparatus, semiconductor integrated circuit manufactured using the photomask, method for manufacturing semiconductor integrated circuit using the photomask, and semiconductor Implementation of integrated circuit layout design method on a computer And to provide a computer readable readable storage medium in which a control program and the control program is recorded for causing.

  According to the layout design method for a semiconductor integrated circuit of the present invention, the logic is changed by changing the mask layer in the manufacturing process for the wiring layer and the contact layer after the automatic layout design of the semiconductor integrated circuit. In the layout design method in which redundant cells to be used at the time of change are arranged in advance and the redundant cells can be connected to the connection target, when the layout design auxiliary computer system performs logic change on the mask pattern after the automatic layout design In addition, when the timing constraint cannot be satisfied by the redundant cell, the connection target or the redundancy is selected from the already used cells of the same type as the redundant cell in the position range that satisfies the timing constraint. Detected used cell that is used in place of the redundant cell by detecting the used cell closest to the cell As the new connection target, the process of connecting the new connection target or the used cell closest to the redundant cell is repeated until the redundant cell appears in a position range that satisfies the timing constraint. The layout design assisting step using the redundant cell is provided, and the above object is achieved.

  Preferably, in the layout design assisting step in the semiconductor integrated circuit layout design method of the present invention, the spare cell detection means includes a spare cell detection step for detecting a redundant cell to be connected to the connection target, and a spare cell direction range detection means. A spare cell direction range detection step for detecting a direction range including the direction of the redundant cell from the position to be connected, and a timing constraint satisfaction range detection means further relate to the clock signal in the detected direction range. A timing constraint satisfaction range detection step for detecting a distance range that satisfies a timing constraint and an already used replacement cell instance detection means are incorporated in a circuit when the redundant cell does not exist in the detected distance range. Already existing within the distance range from the same type of cells as the redundant cell. A used replacement cell instance detection step for detecting a cell closest to the target or the redundant cell; a used instance replacement step in which a used instance replacement unit separates the detected cell and connects to the connection target; The propagation means has a replacement propagation step that repeats each step one or more times until the redundancy cell is finally replaced so as to satisfy the timing constraint relating to the clock signal.

  Still preferably, in a layout design method for a semiconductor integrated circuit according to the present invention, the spare cell detection step detects a redundant cell existing at a location where the straight line distance from the connection target is the shortest.

  Further preferably, the spare cell detection step in the layout design method of the semiconductor integrated circuit according to the present invention is performed by using an automatic layout tool for changing a mask layer in a manufacturing process for a wiring layer and a contact layer to change the connection target using the automatic layout tool. Detect redundant cells to be connected.

  Still preferably, in a layout design method for a semiconductor integrated circuit according to the present invention, the spare cell direction range detecting step detects the direction range as a positional relationship between the connection target and the redundant cell.

  Further preferably, in the layout design method for a semiconductor integrated circuit according to the present invention, the spare cell direction range detection step may be performed on the netlist or circuit diagram information when detecting the positional relationship between the connection target and the redundant cell. The relationship between the redundant cell terminal and the connection target terminal is detected.

  Further preferably, in the semiconductor integrated circuit layout design method of the present invention, the spare cell direction range detection step includes, as the radius, a straight line connecting the terminal coordinates of the redundant cell and the terminal coordinates of the connection target to be connected thereto. Is calculated from the respective coordinates.

  Further preferably, in a layout design method for a semiconductor integrated circuit according to the present invention, a radius that is a straight line connecting the redundant cell and the connection target with a predetermined position of the connection target as a center, and a direction from the connection target to the redundancy cell. From the calculated angles, specifying a predetermined range of angles in the positive direction and the negative direction, respectively, and using the total as the central angle, the redundant cell side as the arc side, and the directional range as the radius It is calculated as a sector area.

  Further preferably, the spare cell direction range detection step in the layout design method of the semiconductor integrated circuit according to the present invention comprises the direction from the connection target to the redundant cell, the terminal coordinates of the redundant cell, and the connection to be connected thereto. The direction of the redundant cell is calculated as an angle from the target terminal coordinates using a trigonometric function.

  Further preferably, in the layout design method for a semiconductor integrated circuit according to the present invention, the spare cell direction range detection step may be performed by setting angles within a range of 0 degrees or more and 180 degrees or less as angles of the predetermined range in the positive direction and the negative direction, respectively. specify.

  Further preferably, the spare cell direction range detection step in the layout design method of the semiconductor integrated circuit of the present invention, when detecting the fan-shaped region by graphic calculation processing, a straight line of a linear equation passing through the center coordinates of the connection target, A region having a distance from the central coordinate smaller than the radius is detected from the central angle region sandwiched between straight lines of other linear equations passing through the central coordinate.

  Further preferably, in the layout design method for a semiconductor integrated circuit according to the present invention, the timing constraint satisfaction range detecting step relates to a clock signal by calculating a resistance and a capacitance from the width and length of the wiring connected to the connection target. A distance range from the connection target that satisfies the timing constraint is calculated, and a distance range that satisfies the timing constraint is detected in the detected direction range.

  Further preferably, in the layout design method for a semiconductor integrated circuit according to the present invention, the timing constraint satisfaction range detection step performs static timing analysis on the original circuit diagram to thereby detect the wiring connected to the connection target. Using the delay value calculated from the resistance and capacitance per length, calculate the margin from the setup time and hold time of the current timing, and calculate the wiring length within the range satisfying the timing constraint calculated from the margin Is calculated by a Manhattan distance in which the sum of absolute values of differences between the coordinates of the connection target and the redundant cell is a distance between two points, and then a linear distance between the two points of the start point and the end point of each coordinate is calculated. The range within the sector area is detected using the calculated linear distance as the distance from the center.

  Further preferably, in the layout design method for a semiconductor integrated circuit according to the present invention, the used replacement cell instance detection step is a cell of the same type as the redundant cell that exists in the distance range detected in the timing constraint satisfaction range detection step. Are detected, and a straight line distance from the terminal coordinates of the connection target is calculated for each terminal coordinate, and the shortest or longest terminal coordinate of the same type cell is detected in each straight line distance.

  Further preferably, in the layout design method for a semiconductor integrated circuit according to the present invention, in the used replacement cell instance detection step, a cell of the same type as the redundant cell is already used in the distance range detected in the timing constraint satisfaction range detection step. If there is no existing state, the used replacement cell instance detection process is canceled as an error process.

  Further preferably, in the layout design method for a semiconductor integrated circuit according to the present invention, in the used replacement cell instance detection step, a terminal of a cell of the same type as the redundant cell is located in the distance range detected in the timing constraint satisfaction range detection step. If it does not exist in the already used state, the distance range is expanded by changing the angle designated as the angle of the predetermined range in the positive direction and the negative direction to a larger value.

  Further preferably, in the layout design method for a semiconductor integrated circuit according to the present invention, the used replacement cell instance detection step may detect the spare cell direction range when the angles specified in the positive direction and the negative direction are 90 degrees or less, respectively. If the angle is 85 degrees or less, the step is designated by 5 degrees, and if the angle is greater than 85 degrees and 90 degrees or less, 90 degrees is designated.

  Further preferably, in the layout design method for a semiconductor integrated circuit according to the present invention, the used replacement cell instance detection step is used as error processing when the angles specified in the positive direction and the negative direction are each greater than 90 degrees. The replacement cell instance detection process is canceled.

  Further preferably, in the layout design method for a semiconductor integrated circuit according to the present invention, the used instance replacement step includes both terminals of the cell detected in the used replacement cell instance detection step (for example, an input / output terminal of an inverter or a two-input gate). The two input terminals or the two input terminals and the output terminals of the two input gates), and the terminal of the disconnected cell and the connection target terminal are connected by wiring. Change the netlist used for automatic placement and routing.

  Further preferably, when the used instance replacement step in the semiconductor integrated circuit layout design method of the present invention includes an instance that is not logically changed next as an instance of the cell detected in the used replacement cell instance detection step, The netlist used for the automatic placement and routing process is changed so that the output terminal of the instance immediately before the next instance whose logic is not changed is connected to the input terminal of the next instance whose logic is not changed.

  Further preferably, in the case where the used instance replacement step in the semiconductor integrated circuit layout design method of the present invention includes an instance that is logically changed next as an instance of the cell detected in the used replacement cell instance detection step. Then, the output terminal of the instance whose logic is changed next is reset as the output terminal of the instance immediately before the location where the current logic change is applied, and each processing from the spare cell detection step to the used instance replacement step is performed. I do.

  Still preferably, in a layout design method for a semiconductor integrated circuit according to the present invention, the replacement propagation step is replaced by the used instance replacement step as a reference coordinate for obtaining a direction in the processing by the spare cell direction range detection step. The position coordinates of the instance are set.

  Further preferably, the replacement propagation step in the semiconductor integrated circuit layout design method of the present invention resets the instance separated in the used instance replacement step as a new connection target in the spare cell direction range detection step, Until the redundant cell is detected in the timing constraint satisfaction range detection step, the process of each step from the spare cell direction range detection step to the used instance replacement step is repeated one or more times.

  Further preferably, in the layout design method for a semiconductor integrated circuit according to the present invention, the replacement propagation step uses the terminal coordinates of the instance immediately before being disconnected in the used instance replacement step as a new connection target in the spare cell direction range detection step. Reset, and repeat the processing of each step from the spare cell direction range detection step to the used instance replacement step one or more times until the redundant cell instance is detected in the timing constraint satisfaction range detection step. .

  Still preferably, in a layout design method for a semiconductor integrated circuit according to the present invention, in the replacement propagation step, the coordinates of the circuit portion that has been replaced by the used instance replacement step are used as a new connection target in the spare cell direction range detection step. And the process of each step from the spare cell direction range detection step to the used instance replacement step is repeated one or more times until the redundant cell instance is detected in the timing constraint satisfaction range detection step. Do.

  The automatic layout design apparatus for a semiconductor integrated circuit according to the present invention performs a logic change by changing a mask layer in a manufacturing process for a wiring layer and a contact layer after an automatic layout design of a semiconductor integrated circuit. In an automatic layout design apparatus for a semiconductor integrated circuit that preliminarily arranges redundant cells to be used at the time of logic change and controls connection of the redundant cells to a connection target, when performing logic change on a mask pattern after automatic layout design, When the timing constraint cannot be satisfied by the redundant cell, the connection target or the redundant cell is selected from the used cells of the same type as the redundant cell in the position range that satisfies the timing constraint. The closest used cell is detected, and the detected used cell used in place of the redundant cell is set as a new connection target. The process of connecting the newly connected cell or the used cell closest to the redundant cell is repeated until the redundant cell appears in a position range that satisfies the timing constraint, and finally the redundant cell is It has a layout design auxiliary computer system to be used, whereby the above object is achieved.

  Preferably, the layout design auxiliary computer system in the semiconductor integrated circuit automatic layout design apparatus of the present invention comprises a spare cell detection means for detecting a redundant cell to be connected to the connection target, and the redundant cell from the position of the connection target. Spare cell direction range detection means for detecting a direction range including the direction of the signal, and a timing constraint satisfaction range detection means for detecting a distance range that satisfies a timing constraint related to the clock signal in the detected direction range. And when the redundant cell does not exist in the detected distance range, the connection target within the distance range or the cell from the same type of cells as the redundant cell already included in the circuit is included in the circuit. Used replacement cell instance detection means for detecting the closest cell from the redundant cell and the connection by disconnecting the detected cell It has a previously used instance substitution means connected to the elephants, and substituted propagation means for repeated one or more times each process until the replacement eventually the redundant cells to satisfy the timing constraints related to the clock signal.

  Further preferably, the spare cell detection means in the automatic layout design apparatus for a semiconductor integrated circuit according to the present invention detects a redundant cell existing at a location where the straight line distance from the connection target is the shortest.

  Further preferably, the spare cell detection means in the automatic layout design apparatus for a semiconductor integrated circuit according to the present invention uses the automatic layout tool for changing the mask layer in the manufacturing process for the wiring layer and the contact layer to change the connection target. A redundant cell to be connected to is detected.

  Further preferably, the spare cell direction range detecting means in the semiconductor integrated circuit automatic layout designing apparatus of the present invention detects the direction range as a positional relationship between the connection object and the redundant cell.

  Further preferably, the spare cell direction range detection means in the automatic layout design apparatus for a semiconductor integrated circuit according to the present invention, when detecting the positional relationship between the connection object and the redundant cell, on the netlist or circuit diagram information, The relationship between the redundant cell terminal and the connection target terminal is detected.

  Further preferably, in the automatic layout design apparatus for a semiconductor integrated circuit according to the present invention, the radius of a straight line connecting the redundant cell and the connection target with the position of the connection target as a center, and the redundancy cell from the connection target. The direction is calculated as an angle, and a predetermined range of angles is designated in the positive direction and the negative direction from the calculated angle, the sum thereof is defined as the central angle, the redundant cell side is defined as the arc side, and the direction range is defined as the radius. It is calculated as a sector area having

  Further preferably, the spare cell direction range detecting means in the semiconductor integrated circuit automatic layout designing apparatus of the present invention is configured such that the radius is a length of a straight line connecting the terminal coordinates of the redundant cell and the terminal coordinates of the connection target. Calculate from the coordinates.

  Further preferably, the spare cell direction range detection means in the semiconductor integrated circuit automatic layout design apparatus of the present invention determines the direction from the connection target to the redundant cell from the terminal coordinates of the redundant cell and the terminal coordinates of the connection target. The direction of the redundant cell is calculated as an angle using a trigonometric function.

  Further preferably, the spare cell direction range detecting means in the semiconductor integrated circuit automatic layout design apparatus of the present invention is configured to set angles within a range of 0 degrees or more and 180 degrees or less as the predetermined range angles in the positive direction and the negative direction, respectively. Specify each.

  Further preferably, the spare cell direction range detection means in the automatic layout design apparatus for a semiconductor integrated circuit according to the present invention, when detecting the fan-shaped area by graphic operation processing, a straight line of a linear equation passing through the center coordinates of the connection target, Then, a region having a distance from the central coordinate smaller than the radius value is detected from the central angle region sandwiched between straight lines of other linear equations passing through the central coordinate.

  Further preferably, the timing constraint satisfaction range detecting means in the semiconductor integrated circuit automatic layout designing apparatus of the present invention calculates the resistance and the capacitance from the width and length of the wiring connected to the connection target, and generates the clock signal. A distance range from the connection target that satisfies the related timing constraint is calculated, and a distance range that satisfies the timing constraint is detected in the detected direction range.

  Further preferably, the timing constraint satisfaction range detection means in the semiconductor integrated circuit automatic layout design apparatus according to the present invention is a wiring connected to the connection target by performing a static timing analysis on the original circuit diagram. Using the delay value calculated from the resistance and capacitance per length, calculate the margin from the setup time and hold time of the current timing, and the wiring length within the range satisfying the timing constraint calculated from the margin After calculating the Manhattan distance using the sum of the absolute values of the differences between the coordinates of the connection target and the redundant cell as the distance between the two points, the linear distance between the two points of the start point and the end point of each coordinate is calculated. Then, the range within the sector area is detected using the calculated straight line distance as the distance from the center.

  Further preferably, the used replacement cell instance detection means in the automatic layout design apparatus for a semiconductor integrated circuit according to the present invention is a cell of the same type as the redundant cell, present in the distance range detected by the timing constraint satisfaction range detection means. Are detected, and a straight line distance from the terminal coordinates of the connection target is calculated for each terminal coordinate, and the shortest or longest terminal coordinate of the same type cell is detected in each straight line distance.

  Further preferably, in the automatic layout design apparatus for a semiconductor integrated circuit according to the present invention, the used replacement cell instance detection means is already used by the same type of cell as the redundant cell in the distance range detected by the timing constraint satisfaction range detection means. If there is no existing state, the used replacement cell instance detection process is canceled as an error process.

  Further preferably, in the automatic layout design apparatus for a semiconductor integrated circuit according to the present invention, the already used replacement cell instance detection means has a cell of the same type as the redundant cell already in the distance range detected by the timing constraint satisfaction range detection means. If it does not exist in the used state, the angle designated as the angle of the predetermined range in the positive direction and the negative direction is changed to a larger value to widen the distance range.

  Furthermore, it is preferable that the used replacement cell instance detection means in the automatic layout design apparatus for a semiconductor integrated circuit according to the present invention has the spare cell direction range when the angles specified in the positive direction and the negative direction are 90 degrees or less, respectively. If the angle is 85 degrees or less, the detection means is designated by adding 5 degrees, and if the angle is greater than 85 degrees and 90 degrees or less, the detection means is designated 90 degrees.

  Further preferably, the used replacement cell instance detection means in the automatic layout design apparatus for a semiconductor integrated circuit according to the present invention preferably performs error processing as error processing when the angles specified in the positive direction and the negative direction are each greater than 90 degrees. Cancel the used replacement cell instance detection process.

  Further preferably, the used instance replacement means in the semiconductor integrated circuit automatic layout design apparatus of the present invention is configured so that both terminals of the cells detected by the used replacement cell instance detection means (for example, input / output terminals of an inverter and two inputs The wiring to the two input terminals of the gate or the two input terminals and the output terminal of the two-input gate) is separated, and the terminal of the separated cell and the connection target terminal are connected by the wiring. The net list used for the automatic placement and routing process is changed.

  Further preferably, when the used instance replacement means in the automatic layout design apparatus for a semiconductor integrated circuit according to the present invention includes an instance that is not logically changed next as an instance of the cell detected by the used replacement cell instance detection means. The netlist used for the automatic placement and routing process is changed so that the output terminal of the instance immediately before the next instance whose logic is not changed is connected to the input terminal of the next instance whose logic is not changed.

  Further preferably, the used instance replacement means in the semiconductor integrated circuit automatic layout design apparatus of the present invention includes an instance that is logically changed next as an instance of a cell detected by the used replacement cell instance detection means. Resets the output terminal of the instance whose logic has been changed next as the output terminal of the instance immediately before the location where the current logic change is made, and from each of the spare cell detection means to the already used instance replacement means Process.

  Further preferably, the replacement propagation means in the automatic layout design apparatus for a semiconductor integrated circuit according to the present invention is replaced by the used instance replacement means as coordinates serving as a reference for obtaining a direction in the processing by the spare cell direction range detection means. The position coordinates of the instance to be set are set.

  Further preferably, the replacement propagation means in the semiconductor integrated circuit automatic layout design apparatus of the present invention resets the instance separated by the used instance replacement means as a new connection target in the spare cell direction range detection means. Each process from the spare cell direction range detection means to the already used instance replacement means is repeated one or more times until the redundant cell is detected by the timing constraint satisfaction range detection means.

  Further preferably, the replacement propagation means in the automatic layout design apparatus for a semiconductor integrated circuit according to the present invention is configured such that the terminal coordinates of the instance immediately before being disconnected by the already-used instance replacement means are set as new connection targets in the spare cell direction range detection means. And the processing from the spare cell direction range detection means to the used instance replacement means is repeated one or more times until the timing constraint satisfaction range detection means detects the redundant cell instance.

  Further preferably, the replacement propagation means in the automatic layout design apparatus for a semiconductor integrated circuit according to the present invention is configured such that the coordinates of the vacant circuit portion replaced by the used instance replacement means are newly connected in the spare cell direction range detection means. The target is reset, and each process from the spare cell direction range detection unit to the used instance replacement unit is repeated one or more times until the timing constraint satisfaction range detection unit detects the redundant cell instance. .

  Further preferably, in the automatic layout design apparatus for a semiconductor integrated circuit according to the present invention, an arithmetic processing device on which the layout design auxiliary computer system is mounted, and a display unit capable of displaying a screen related to arithmetic processing of the arithmetic processing device, And an operation input unit for issuing an operation input command to the arithmetic processing of the arithmetic processing unit.

  Further preferably, in the automatic layout design apparatus for a semiconductor integrated circuit according to the present invention, the wiring layer and the contact layer are manufactured so as to be finally replaced with the redundant cell under a condition satisfying a timing constraint relating to a clock signal. Only the mask layer is changed, and the logic change process is performed so as to satisfy the timing constraint relating to the clock signal.

  Further preferably, in the automatic layout design apparatus for a semiconductor integrated circuit according to the present invention, a mask pattern stored in a mask pattern database and a net list which is text data describing a connection relation between cells are input. Circuit diagram information or netlist (conceptual circuit diagram, circuit diagram is reflected in actual processing) in which redundant cells used for logic change when designing the layout of the cells and the wiring between each cell The automatic placement and routing processing unit for generating the net list as circuit diagram information), the net list storage unit storing the net list and the input parameters to the spare cell direction range detecting means can be operated and input from the outside, Interface unit capable of outputting mask pattern data from the mask pattern database to the outside Static timing analysis is performed using circuit diagram information or a net list (conceptually a circuit diagram, or a net list as circuit diagram information reflecting the circuit diagram in actual processing) from the automatic placement and routing processing unit. A static timing analysis processing unit that executes the delay value from the resistance and capacitance per length of the wiring connected to the connection target and supplies the delay value to the timing constraint satisfaction range detection unit.

A semiconductor integrated circuit layout design assistance system according to the present invention comprises a computer system, and spare cell detection means for detecting a redundant cell to be connected to the connection target,
Spare cell direction range detecting means for detecting a direction range including the direction of the redundant cell from the connection target position, and a distance range satisfying a timing constraint related to a clock signal in the detected direction range A timing constraint satisfaction range detecting means for detecting the redundant cell, and when the redundant cell does not exist in the detected distance range, the redundant cell already included in the circuit and the same type as the redundant cell, A used replacement cell instance detection means for detecting the connection target within the distance range or a cell closest to the redundant cell; a used instance replacement means for disconnecting the detected cell and connecting to the connection target; and a clock signal In order to satisfy the timing constraints related to the above, a replacement transmission that repeats each process one or more times until the redundant cell is finally replaced. Are those having the unit, the objects can be achieved.

  The photomask of the present invention is produced based on mask pattern information designed by using the automatic layout design apparatus for semiconductor integrated circuits of the present invention, thereby achieving the above object.

  The photomask manufacturing method of the present invention is a method of designing a photomask pattern by the automatic layout design apparatus for a semiconductor integrated circuit according to the present invention, and manufacturing the photomask by patterning with this design information. The objective is achieved.

  The semiconductor integrated circuit of the present invention is manufactured using the photomask of the present invention, and thereby the above-described object is achieved.

  The method for manufacturing a semiconductor integrated circuit according to the present invention includes a photomask pattern designed by the automatic layout design apparatus for a semiconductor integrated circuit according to the present invention, and a resist pattern patterned by this design information is used to provide the semiconductor integrated circuit on or on the semiconductor substrate. A semiconductor integrated circuit is formed on the formed semiconductor layer, and thereby the above object is achieved.

  The control program according to the present invention records each processing procedure for causing a computer to execute each step of the layout design method for a semiconductor integrated circuit according to the present invention, thereby achieving the above object.

  The readable storage medium of the present invention is a computer-readable storage medium storing the control program of the present invention, thereby achieving the above object.

  The operation of the present invention will be described below with the above configuration.

  In the present invention, when the logic change is performed by the freeze silicon ECO function using the redundant cell (spare cell), the timing constraint cannot be satisfied when the spare cell to be replaced is used. In the range that can satisfy the condition, disconnect the connection cell or the cell closest to the spare cell from the same type of used cells as the replacement target spare cell, and replace it with the replacement target spare cell. Create a netlist to connect. By repeating this process until the spare cells appear in a range that can satisfy the timing constraints, a netlist is created in which used cells of the same type as the spare cells are sequentially transplanted into a “ball-throw” type. It becomes possible to do. By inputting the net list and performing the freeze silicon ECO function, all timing constraints can be satisfied.

  As described above, according to the present invention, when the timing constraint is not satisfied in the freeze silicon ECO function, the enormous effort like the prior art that requires manual change of the net list is unnecessary. In addition, it is possible to satisfy the timing constraint with the freeze silicon ECO with a high probability without modifying layers other than the wiring layer and the contact layer, or arranging in advance more spare cell instances than the current level. Freeze silicon ECO can be performed to automatically satisfy timing constraints, so it is effective to increase the design period and mask cost in the logic change, cause human error, and increase the chip area of the initial design. Can be prevented. Therefore, it is possible to manufacture a semiconductor device with few operational errors efficiently and an electronic device on which the semiconductor device is mounted at low cost, and can greatly contribute to the spread of this freeze silicon ECO.

  DESCRIPTION OF EMBODIMENTS Embodiments of an automatic layout design apparatus for a semiconductor integrated circuit on which a layout design assistance system unit of the present invention is mounted will be described in detail below with reference to the drawings.

  FIG. 1 is a block diagram illustrating an exemplary functional configuration of an automatic layout design apparatus for a semiconductor integrated circuit according to an embodiment of the present invention.

  In FIG. 1, an automatic layout design apparatus 1 for a semiconductor integrated circuit according to the present embodiment finally replaces a redundant cell (spare cell) under a condition that satisfies the timing constraint related to a clock signal, and a wiring layer and a contact layer It is possible to display an arithmetic processing unit 2 that can perform logic change processing so as to satisfy a timing constraint related to a clock signal by changing only the mask layer in the manufacturing process, and a screen related to the arithmetic processing of the arithmetic processing unit 2 And a keyboard 4 and a mouse 5 as operation input units for issuing various operation input commands to the arithmetic processing of the arithmetic processing unit 2.

  The arithmetic processing unit 2 includes a mask pattern database 11, an automatic placement and routing processing unit 12, a net list storage unit 13, an interface unit 14, a static timing analysis processing unit 15, and a layout design auxiliary computer system. The design auxiliary system unit 20 is mounted.

  The automatic placement and routing processing unit 12 is a processing unit of existing automatic placement and routing software in which the freeze silicon ECO function is implemented, and the connection relationship between the mask pattern stored in the mask pattern database 11 and the elements (between cells). The netlist of the netlist storage unit 13 which is text data in which is described is input, and the layout of the arrangement of elements (cells) and the wiring between elements (between cells) is designed. Further, in the automatic placement and routing processing unit 12, a spare cell to be replaced at the time of logic change is determined from the difference between the input net list from the net list storage unit 13 and the mask pattern from the mask pattern database 11, and a spare cell detection block described later. 21 is a circuit diagram information or net list (conceptually a circuit diagram, and a net list as circuit diagram information reflecting the circuit diagram in actual processing) in which spare cells used when changing logic are arranged. Generated.

  In the interface unit 14, input parameters to the net list storage unit 13 and a spare cell direction range detection block 22 described later are input from the outside via a keyboard 4 and a mouse 5 as input operation means, and the mask pattern in the mask pattern database 11 is input. Data can be output to the outside.

  The static timing analysis unit 15 is a processing unit of existing static timing analysis software linked with the automatic placement and routing processing unit 12, and circuit diagram information or netlist (conceptually) from the automatic placement and routing processing unit 12. Is a circuit diagram, and in actual processing, a net list as circuit diagram information reflecting the circuit diagram) and input data such as timing constraints input from the interface unit 14 are used to perform static timing analysis. As a result of the static timing analysis, the resistance and capacitance per length of the wiring connected to the connection target location are obtained, and the delay value is calculated by this, and the timing constraint satisfaction range detection block 23 described later receives the delay value. A delay value is provided.

  The layout design assisting system unit 20 sets the timing constraint when the timing constraint cannot be satisfied by the spare cell (redundant cell) when the logic change is performed on the mask pattern after the automatic layout design by the freeze silicon ECO function. In the position range that satisfies the condition, the existing cell of the same type closest to the connection target or spare cell is detected from the instances of the same type of used cell as the spare cell to be replaced, and this is used instead of the spare cell instance. By using this unused circuit part as a new connection target for the unused circuit part, the processing using the same type of used cell that is closest to the connection target or spare cell is placed in a position range that satisfies the timing constraints. Repeat until a redundant cell appears, and a redundant cell appears Using redundant cells to the last empty circuit portion at point. All timing constraints can be satisfied by performing the freeze silicon ECO function using the netlist obtained by this processing.

  The layout design assisting system unit 20 includes a spare cell detection block 21 as a spare cell detection unit, a spare cell direction range detection block 22 as a spare cell direction range detection unit, and a timing constraint satisfaction range detection unit according to a control program described later. Timing constraint satisfaction range detection block 23, used replacement cell instance detection block 24 as used replacement cell instance detection means, used replacement instance replacement block 25 as used replacement instance replacement means, and replacement propagation means Each function with the reference terminal coordinate resetting block 26 is executed.

  In the spare cell detection block 21, an instance of a spare cell (redundant cell) determined from the difference between the input net list in the net list storage unit 13 and the mask pattern data in the mask pattern database 11 is detected by the automatic placement and routing processing unit 12. . In this case, the spare cell detection block 21 uses the automatic layout tool that changes the mask layer in the manufacturing process for the wiring layer and the contact layer, and uses the automatic layout tool to change the spare cell that is present at the closest linear distance from the connection target. Detect.

  In the spare cell direction range detection block 22, a range in the direction including the direction to the spare cell instance is detected from an appropriate position from the connection target connected to the terminal of the spare cell instance detected by the spare cell detection block 21. In this process, an angle θ1 within a predetermined range input from the interface unit 14 is used as a parameter.

  When detecting the positional relationship between the connection target and the spare cell, the spare cell direction range detection block 22 detects the positional relationship between the input terminal coordinates of the spare cell and the output terminal coordinates of the connection target on the mask pattern database 11. Centered on the predetermined position of the connection target, the straight line connecting the spare cell and the connection target is used as the radius, the direction of the spare cell from the connection target is calculated as the angle, and the positive angle and the negative direction from the calculated angle respectively. The direction range is calculated as a sector region having a radius value with the angle θ1 of the predetermined range designated externally or internally and the total as the central angle, the spare cell side as the arc side. As the radius, the length of a straight line connecting the input terminal coordinates of the spare cell and the output terminal coordinates of the connection target to be connected thereto is calculated from the respective coordinates. Further, the direction from the connection target to the spare cell can be calculated from the spare cell input terminal coordinates and the connection target output terminal coordinates to be connected to the spare cell direction as an angle using a trigonometric function.

  The timing constraint satisfaction range detection block 23 relates to the clock signal from the mask pattern database 11 using the direction range detected by the spare cell direction range detection block 22 and the static timing analysis result by the static timing analysis processing unit 15. A distance range is detected that satisfies the timing constraints. That is, the timing constraint satisfaction range detection block 23 uses the result of the static timing analysis to estimate the resistance and capacitance from the width and length of the wiring connected to the connection target, thereby satisfying the timing constraint related to the clock signal. A distance range from the connection target is calculated, and a distance range that satisfies the timing constraint is detected in the detected direction range. Further, the timing constraint satisfaction range detection block 23 performs a static timing analysis on the original circuit diagram, thereby calculating a delay value calculated from the resistance and capacitance per length of the wiring connected to the connection target. Is used to determine the margin from the setup time and hold time of the current timing, and the wiring length within the range that satisfies the timing constraint calculated from this margin is the absolute difference between the coordinates of the connection target and the spare cell. After calculating the Manhattan distance with the sum of the values as the distance between the two points, calculate the straight line distance between the start point and the end point of each coordinate, and use the calculated straight line distance as the distance from the center of the connection target. Detect internal range.

  In the used replacement cell instance detection block 24, the replacement target is detected in the mask pattern data of the mask pattern database 11 using the distance range detected by the timing constraint satisfaction range detection block 23 and the position of the spare cell instance. The At this time, if a spare cell exists within the distance range detected by the timing constraint satisfaction range detection block 23, an instance of the spare cell is detected. In this case, since a spare cell is used and no used cell is used in place of the spare cell, the replacement process with the used cell by the next used instance replacement block 25 is not necessary. 25, the spare cell is connected to the connection target (or the unused circuit portion as a new connection target) instead of the used cell. Further, in the used replacement cell instance detection block 24, if there is no spare cell within the distance range detected by the timing constraint satisfaction range detection block 23, the mask pattern data in the mask pattern database 11 is used in the circuit. Among the instances of the same type of cells as the spare cells that are incorporated, instances of the same type of cells that are present at the closest location to the connection target or spare cell within the satisfaction range of the timing constraints are detected. In other words, the used replacement cell instance detection block 24 detects all cells of the same type as the spare cell that exist in the satisfaction range (distance range) of the timing constraint, and sets each input terminal coordinate to the output terminal coordinate to be connected. The straight line distance is calculated, and the terminal coordinates of the same type of cell that is the shortest or longest among the straight line distances are detected. In addition, the used replacement cell instance detection block 24 performs error processing for this used replacement cell when a cell of the same type as the spare cell has not already been used in the timing constraint satisfaction range (distance range). Cancel instance detection processing. In addition, within the satisfaction range of the timing constraints, a spare cell that is present in the closest location from the spare cell and in the location closest to the connection target (or the location farthest from the spare cell) is detected. It is preferable that the process until the connection is finally completed using the spare cell is simplified rather than detecting the same type of cells.

  The used instance replacement block 25 uses the result detected by the used replacement cell instance detection block 24 so that the wiring to both terminals of the detected cell instance is disconnected and used as a spare cell. Further, the net list of the net list storage unit 13 used for the automatic placement and routing process is changed by connecting the input terminal of the detected cell and the output terminal to be connected by wiring. As will be described in detail later, the logic after the detected instance of the cell (for example, when the detected cell is, for example, two inverters, one of which is an inverter and the other is a plurality of instances such as a NAND gate). If it is a change target, the process is taken over by the spare cell detection block 21. Further, when the logic after the detected instance of the cell is not the target of the logic change, the process is taken over by the reference terminal coordinate resetting block 26.

  In the reference terminal coordinate reset block 26, the instance replaced by the used instance replacement block 25 is used as a reference coordinate (output coordinate of connection target; center coordinate) for obtaining a direction in the processing by the spare cell direction range detection block 22. The output terminal coordinates of the same type of cell as the spare cell are set. That is, the reference terminal coordinate resetting block 26 resets the instance (the same type of cell as the spare cell) separated by the used instance replacement block 25 as a connection target in the spare cell direction range detection block 22, and satisfies the timing constraint. Each process from the spare cell direction range detection block 22 to the used instance replacement block 25 may be repeated one or more times until a spare cell is detected by the range detection block 22. Alternatively, the reference terminal coordinate reset block 26 resets the output terminal coordinates of the instance immediately before being disconnected by the used instance replacement block 25 as a new connection target in the spare cell direction range detection block 22 and detects the timing constraint satisfaction range detection. Each process from the spare cell direction range detection block 22 to the used instance replacement block 25 may be repeated one or more times until a spare cell instance is detected in the block 22. Alternatively, the reference terminal coordinate reset block 26 resets the coordinates of the circuit portion that has been replaced by the used instance replacement block 25 as a new connection target in the spare cell direction range detection block 22 and detects the timing constraint satisfaction range detection. Each process from the spare cell direction range detection block 22 to the used instance replacement block 25 may be repeated one or more times until a spare cell instance is detected in the block 22.

  In addition to the above description of FIG. 1, the principle of the present invention will be briefly described with reference to FIG.

  As shown in FIG. 2, in the case of a logic change, if the closest spare cell that you want to use additionally for the connection target is found and there is a timing problem when using it, the timing constraint on the clock signal To the extent that there is no problem, the closest cell (inverter INV in this case) that has already been incorporated and used in the circuit is used instead of the spare cell. Look for a cell to be used in place of the spare cell in the direction of the first spare cell found within the range where the timing is not delayed, and if there is a cell already used in the circuit, use that cell further. The freeze silicon ECO method is used in which the process of going is repeated, cells are replaced in a ball-throw type, and the cells are sequentially transplanted, and finally the spare cell detected first is used.

  As a result, if the use is made only from spare cells that are arranged in advance as shown in FIG. 17 of the prior art, there is a possibility that there is a possibility that the spare cells to be used exist far away, and there may be a timing problem. Since cells that are already incorporated in the circuit existing in the direction of the spare cell (the same type of cells as the spare cell) are used as long as the timing constraints are not violated as in the invention, it is not necessary to arrange more spare cells than necessary. In addition, the layout freeze silicon ECO function can reduce or prevent violations of timing constraints related to the clock signal.

  FIG. 3 is a block diagram showing a hardware configuration example of a main part of the automatic layout design apparatus for the semiconductor integrated circuit of FIG.

  The automatic layout design apparatus 1 for a semiconductor integrated circuit according to the present embodiment is configured by a computer system, and issues a CPU (Central Processing Unit) 2A as a control means for performing overall control and an input command to the CPU 2A. Keyboard 4, mouse 5, touch panel and pen input device, as well as an operation input unit such as an input device that receives and inputs via a communication network (for example, the Internet or an intranet), and an initial screen for each process on the display screen, A display unit 3 as a display unit such as a CRT or a liquid crystal display device for displaying a selection scene, a control result screen and an operation input screen by the CPU 2A, a plasma display device, an electroluminescence display device, a control program and its data, etc. Stored computer readable And ROM6 of the read recording medium, such as is read control program and its data at startup, and a RAM7 as a storage unit acting as a work memory for reading and storing data for each control by CPU 2A.

  The ROM 6 as a readable recording medium may be configured by a hard disk, a portable optical disk, a magneto-optical disk, a magnetic disk, an IC memory, or a combination thereof. The control program and its data are stored in the ROM 6, and the control program and its data are downloaded to the ROM 6 from another readable recording medium or via a wireless, wired or Internet, or intranet. Also good. Note that the mask pattern database 11 and the net list storage unit 13 may be configured as the same storage unit integrally with the RAM 5 or may be configured separately.

  Next, the processing procedure of the layout design method for the semiconductor integrated circuit according to the present embodiment will be described in detail with reference to FIGS.

  FIG. 4 is a flowchart for explaining a processing procedure example in the layout design method of the semiconductor integrated circuit according to the present embodiment. FIG. 5 is a layout netlist, and FIG. 6 is a logic-changed netlist input to the automatic placement and routing processing unit 12 of FIG. 1 in order to execute the freeze silicon ECO function. FIG. 7 is a circuit diagram showing a simplified mask layout in logical form before freeze silicon ECO processing. FIG. 8 is a circuit diagram showing the processing by the spare cell direction range detection block 22 in FIG. 1 in a simplified logical form. FIG. 9 shows the process by the timing constraint satisfaction range detection block 23 in FIG. 1 in a logical form. FIG. FIG. 10 is a circuit diagram showing the processing by the used instance replacement block 25 of FIG. 1 in a simplified logical form. FIG. 11 shows an automatic placement and routing processing unit changed by the used instance replacement block 25 of FIG. 12 is a net list that is input to 12. FIG. 12 is a circuit diagram showing the result of repeating each process once or a plurality of times by the reference terminal coordinate resetting block 26 of FIG. 1 in a logical format, and FIG. FIG. 4 is a diagram showing a net list that is changed by an instance replacement block 25 and input to the automatic placement and routing processing unit 12.

  In FIG. 7, the used instance 201 of the NOR cell is described in the first column of FIG. 5, the used instance 202 of the NAND cell is described in the second column of FIG. 5, and the used instance 201 of the NOR cell The output terminal 201b is connected to the input terminal 202a of the used instance 202 of the NAND cell. Further, the used instance 203 of the INV cell is described in the third column in FIG. The used instance 204 of the NAND cell is described in the fourth column of FIG. 5, the used instance 205 of the INV cell is described in the fifth column of FIG. 5, and the used instance 208 of the INV cell is displayed in the sixth column of FIG. The used instance 206 of the NAND cell is described in the seventh column of FIG. 5, the used instance 209 of the NOR cell is described in the eighth column of FIG. 5, and the used instance 210 of the INV cell is shown in FIG. The used instance 207 of the NOR cell is described in the 10th column of FIG. 211 is an instance of an INV cell as a spare cell.

  The output terminal 204b of the used instance 204 of the NAND cell is connected to the input terminal 205a of the used instance 205 of the INV cell. The output terminal 205b of the used instance 205 of the INV cell is connected to one input terminal 206a of the used instance 206 of the NAND cell. The output terminal 208b of the used instance 208 of the INV cell is connected to the other input terminal 206a of the used instance 206 of the NAND cell. Further, the output terminal 209b of the used instance 209 of the NOR cell is connected to the input terminal 210a of the used instance 210 of the INV cell. The output terminal 210b of the used instance 210 of the INV cell is connected to the other input terminal 207a of the used instance 207 of the NOR cell.

  In this embodiment, in order to perform freeze silicon ECO when a logic change is made after layout design, first, in step S1, the spare cell detection block 21 performs an instance of a spare cell to be replaced in the same manner as normal freeze silicon ECO. Is discovered. As a search algorithm used at that time, a technology installed in software having a freeze silicon ECO function that has already been commercialized can be used. Alternatively, an instance of a spare cell that is present at a place where the straight line distance is the shortest from an instance placed immediately before the place where the logic change is applied is detected.

  Next, in step S2, the spare cell direction range detection block 22 starts from the appropriate position (output terminal 201b) of the connection target (used instance 201 of the NOR cell) connected to the input terminal 211a of the instance 211 of the replacement target spare cell. A range of directions including the direction to the spare cell instance 211 is detected. In this process, first, the positional relationship between the input terminal 211a of the instance 211 of the replacement target spare cell and an appropriate position from the instance 201 to be connected (here, the output terminal 201b may be the input terminal 201). Is detected from the mask pattern data in the mask pattern database 11 and the input terminal coordinates of the instance 211 of the replacement target spare cell and the output terminal coordinates of the instance immediately before the location where the logical change is added (the connection target instance 201). Are detected. The output terminal 201b of the instance immediately before the location where the logic change is applied (the connection target instance 201) is the center (center coordinate), and the input terminal 211a of the spare cell instance 211 is immediately before the location where the logic change is applied. The distance of the straight line L connecting the output terminal 201b of the instance (connection target instance 201) is set as the radius, and the spare cell is connected to the spare cell from the output terminal 201b of the instance (connection target instance 201) immediately before the place where the logical change is applied. The direction of the instance 211 toward the input terminal 211a is calculated as an angle. A predetermined range of angles θ1 is specified in the positive direction and the negative direction from the calculated angles, and the sum of them is set as the central angle 2θ1, and the spare cell direction range is defined as an arc on the input terminal 211a side of the instance 211 of the spare cell. It is calculated as a sector area A1 having the radius.

  For example, when the logic change as shown in FIG. 6 is applied to the netlist of the layout shown in FIG. 5, as shown in FIG. 7, the output terminal 201b of the instance 201 to be connected and the input terminal of the instance 202 When an instance of the INV cell is added as a new logic to the 202a by the spare cell instance 211, the coordinates of the position of the output terminal 201b are detected. As shown in FIG. 8, the position on the side to which the input terminal 211a of the spare cell instance 211 is connected is the target position, and the coordinates of the output terminal 201b of the instance 201 immediately before the place where the logic change is applied are the origin (center coordinates). ), And the radius of the straight line L connecting the input terminal 211a of the instance 211 of the spare cell and the output terminal 201b of the instance 201 immediately before the location where the logic change is applied is defined as the radius, and the output terminal 201b of the instance 201 The direction from the center coordinates to the coordinates of the input terminal 211a of the spare cell instance 211 is obtained as an angle on orthogonal coordinates using a trigonometric function from the relationship between the two points. Further, as an input parameter, the angle θ1 is 0 degree or more and 180 degrees or less (usually 0 degree or more and 90 degrees or less but including the reverse direction as a center distribution with respect to the straight line between the two points, and the reverse direction is also included. Specified angle within a range of, for example, 40 degrees, and the obtained angle of the straight line L is, for example, 300 degrees, the specified angle 40 for each of the positive and negative directions. The degrees are added and subtracted, and the sum is taken as the central angle. In this example, the central angle is 80 degrees from 260 degrees to 340 degrees. The position on the side connected from the coordinates of the output terminal 201b of the instance 201 immediately before the location to which the logic change is applied, with the coordinate of the output terminal 201b of the instance 201 immediately before the location to which the logic change is applied as the center point A sector area A1 having the radius of the linear distance of coordinates 211a as a radius is obtained by graphic calculation. In the graphic calculation for obtaining the sector area A1, the central angle 2θ1 sandwiched between the straight line of the linear equation passing through the central coordinates (the output terminal 201b of the instance 201 to be connected) and the straight line of another linear equation passing through the same central coordinates. Among these areas, those having a distance from the center coordinate smaller than the radius value are detected.

  Furthermore, in step S3, the timing constraint satisfaction range detection block 23 detects a distance range that satisfies the timing constraint related to the clock signal in the spare cell direction range (fan area A1) obtained in step 2. Is done. For example, as shown in FIG. 9, the wiring length is calculated by a Manhattan distance in which the sum of absolute values of the difference in coordinates between the output terminal 201b of the instance 201 and the input terminal 211a of the instance 211 of the spare cell is a distance between two points. After that, the distance of the straight line L between the start point and the end point is calculated and set as the radius. A distance range that satisfies the timing constraint is obtained by graphic calculation as a sector region A2 centered on the output terminal 201b at an appropriate position on the connected side inside the sector region A1. At this time, in the timing constraint satisfaction range detection block 24, the static timing analysis processing unit 15 converts the original circuit diagram or netlist (conceptually, a circuit diagram, and a netlist reflecting the circuit diagram in actual processing). Using the delay value calculated from the resistance and capacitance per length of the wiring connected to the connection target location (output terminal 201b), which is obtained as a result of executing the static timing analysis on the current timing, A margin from the setup time and hold time is determined. The wiring length within the range satisfying the timing constraint calculated from the margin is calculated by the Manhattan distance, the distance of the straight line L between the start point and the end point is calculated, and the straight line distance is calculated from the center coordinate. By detecting the range within the sector area A1 as the distance, the sector area A2 that is the timing constraint satisfaction range (the distance range) is obtained.

  Further, in step S4, the timing constraint satisfaction range detection block 23 determines whether or not the input terminal 211a of the spare cell instance 211 exists within the range obtained in step S3. For example, in the example of FIG. 9, the input terminal 211a of the spare cell instance 211 does not exist in the sector area A2 that is the distance range. As a result of this determination, if the input terminal 211a of the spare cell instance 211 exists in the sector area A2 that is the distance range obtained in step S3 (in the case of YES), the process proceeds to step S8, and the spare cell instance 211 is reached. If the input terminal 211a does not exist within the fan-shaped area that is the distance range obtained in step S3 (in the case of NO), the process proceeds to step S5.

  Next, in step S5, whether or not an input terminal of an instance of the same type of cell as the spare cell instance 211 exists in the used state within the range obtained in step S3 by the used replacement cell instance detection block 24. Judgment is made. For example, in the example of FIG. 9, the instance 203 and the instance 205 exist in the sector area A2 that is the distance range. As a result of this determination, when the input terminals of the instances of the same type of cells as the spare cells (instance 203 and instance 205 in the example of FIG. 9) exist in the sector area A2 obtained in step S3 in the already used state (in the case of YES) ), The process proceeds to step S6, and the input terminal of the same type of cell as the spare cell (in the example of FIG. 9, instance 203 and instance 205) exists in the sector area A2 obtained in step S3 in the already used state. If not (NO), the process is canceled as an error. When processing is stopped as an error, a layout that does not satisfy the timing constraint is output. In that case, there is a possibility that an error does not occur by changing θ1 to a larger value and re-executing the process. It is necessary to manually change the input netlist to use or to give up freeze silicon ECO and modify layers other than the metal wiring layer and the contact layer.

  Further, in step S5, the spare cell detected by the used replacement cell instance detection block 24 (cell selection is performed in the used replacement cell instance detection block 24 and disconnection replacement is performed in the used instance replacement block 25). Of the input terminals of the same type of cell as the instance 211, the input terminal 205a of the instance 205 closest to the input terminal 211a of the spare cell instance 211 is selected. At this time, the straight line distance of the straight line L between the input terminal coordinates of all the instances detected by the used replacement cell instance detection block 24 in step S5 and the input terminal coordinates of the instance 211 of the replacement target spare cell is calculated. The input terminal coordinates of the instance existing at the shortest distance are detected, and the instance having the input terminal is selected. In the example of FIG. 9, the instance 205 corresponds. If the input terminal of the same type of cell as the spare cell instance 211 that is closest to the output terminal 201b of the instance 201 to be connected is selected, the instance 203 corresponds to the example of FIG.

  Further, in step S6, the instance 205 detected in step S5 is disconnected by the used instance replacement block 25 and connected to the connection target instance 201 instead of the spare cell instance 211. Further, for example, an instance connected to the output terminal 205b of the instance 205 disconnected in step S6 is included separately. If this instance is an instance whose logic has not been changed, an input terminal of the instance whose logic has not been changed is The net list in the net list storage unit 13 is changed so that the output terminal 205b of the instance 205 immediately before the instance whose logic has not been changed is connected.

  For example, when the instance 205 shown in FIG. 9 is selected in step S5, all the connections to the input / output terminals of the instance 205 are disconnected as shown in FIG. Since another instance connected to the output terminal 205b is included, and this another instance is an instance that is not logically changed next, the output of the instance 205 immediately before the next instance that is not logically changed Since the terminal 205b and the input terminal of another instance thereof are connected, a net list as shown in FIG. 11 is created. In FIG. 11, the input and output of the INV cell in the fifth column X5 are changed from n10 and n11 shown in the sixth column X5 in FIG. 6 to n3 and nx3. Further, the input and output of the INV cell in the sixth column X11 are changed from n3 and nx3 shown in the second column X11 of FIG. 6 to n10 and n11 shown in the sixth column X5 of FIG.

  On the other hand, the changed logic is a composite logic of a plurality of instances, which includes another instance 206 connected to the output terminal 205b of the instance 205 disconnected in step S6, and this other instance is the next logically changed instance. In this case, since it is necessary to perform the same processing as above for the location, the output terminal of the instance whose logic is changed is the output of the instance 205 immediately before the location where the current logic change is applied. The terminal 205b is reset, and the process returns to step S1.

  After that, in step S7, the reference terminal coordinate reset block 26 determines that the appropriate position from the input terminal 205a of the instance 205 disconnected in step S6 is the appropriate position to be connected in the spare cell direction range detection processing in step 2 ( The center coordinates are reset, and the process returns to step S2. For example, as shown in FIG. 10, like the output terminal 204b and the input terminal 206a, a terminal that has been cut and floated in step S6 (a circuit portion that is vacant by using the same type of cell instead of a spare cell, or From the wiring part), the position of the output terminal 204b is reset as the output terminal of the instance immediately before the location where the logic change is applied. After the process of step S7 is completed, the process after the timing constraint satisfaction range detection process is performed until an instance of a spare cell to be replaced is detected by the timing constraint satisfaction range detection process by moving to the process of step S2. Will be repeated.

  Further, in step S8, for example, a net list as shown in FIG. 13 is created so that the terminal of the spare cell instance confirmed in step S4 is connected to the connection target. The data is output to the storage unit 14. In FIG. 13, the input of the NAND cell in the second column X2 is changed from n3 shown in the second column X2 in FIG. 5 to nnx3. Further, the inputs and outputs of the INV cells in the fifth column X5 are changed from n10 and n11 shown in the fifth column X5 in FIG. 5 to n3 and nx3. Further, n17 and n18 which are inputs and outputs of the INV cell in the ninth column X9 are changed to n10 and n11 shown in the fifth column X5 in FIG. Further, an INV cell having an input connected to the net n17 and an output connected to the net n18 is inserted as X11 between the ninth and tenth columns. By performing freeze silicon ECO using such a netlist, logic changes can be made to satisfy all timing constraints.

  FIG. 14 is a flowchart for explaining another processing procedure example in the layout design method of the semiconductor integrated circuit according to the present embodiment.

  Except for step S5 and step S9, the operation is the same as in the case of the flowchart shown in FIG.

  As shown in FIG. 14, in step S5, an input terminal of an instance of a cell of the same type as the spare cell instance 211 falls within the range determined by the used replacement cell instance detection block 25 in step S3. A determination is made whether or not it exists. For example, in the example of FIG. 9, the instance 203 and the instance 205 correspond. As a result of this determination, if the input terminal of an instance of the same type of cell as the spare cell is in the used state and is within the range obtained in step S3 (in the case of YES), the process proceeds to step S6. If the input terminal of the instance of the same type of cell does not exist within the range determined in step S3 in the used state (NO), the process proceeds to step S9.

  Next, in step S9, it is determined whether or not the designated θ1 is 90 degrees or less, and if θ1 is 90 degrees or less, the process proceeds to the spare cell direction range detection process in step S2 and the designated θ1. If it is 85 degrees or less, it is set by adding 5 degrees to θ1, and if θ1 is greater than 85 degrees and 90 degrees or less, θ1 is set to 90 degrees. If the designated θ1 is greater than 90 degrees (YES) in step S9, the process is canceled as an error. When processing is stopped as an error, a layout that does not satisfy the timing constraint is output. In this case, as in the prior art, it is necessary to manually change the input netlist so as to use a cell with high capability, or to give up freeze silicon ECO and modify layers other than the metal wiring layer and the contact layer. .

  As described above, according to the present embodiment, when a logical change is performed on the mask pattern after layout design by freeze silicon ECO, the spare cell direction range detection block 22 detects the direction range of the spare cell to be replaced, and the direction Within the range, the timing constraint satisfaction range detection block 23 detects a distance range that satisfies the timing constraint. When there is no spare cell within the distance range that satisfies this timing constraint, among the already used instances of the same type, the instance that is present at the closest location to the spare cell or the connection target in the used replacement cell instance detection block 24 Then, the detected replacement instance replacement block 25 disconnects both terminals of the detected instance and uses them instead of the spare cell. In the reference terminal coordinate resetting block 26, the connection target is reset with the disconnected terminal portion (vacant circuit portion) as the replacement target, and each process is repeated one or more times, and finally the conditions satisfying the timing constraints are satisfied. Replace up to spare cell.

  This makes it possible to automatically replace a spare cell instance that can be finally replaced under conditions that satisfy all timing constraints related to the clock signal, without manual intervention, unless an error occurs. The logic change can be made so as to satisfy the timing constraint related to the clock signal by the freeze silicon ECO that changes the mask layer in the manufacturing process for the wiring layer and the contact layer.

  Furthermore, by using a photomask having a mask pattern generated by using the layout design assisting system of the present embodiment, the freeze silicon ECO can satisfy the timing constraint related to the clock signal without increasing the circuit area. A semiconductor integrated circuit in which the logic is changed can be manufactured.

  As described in the above embodiment, when a logical change is performed on a mask pattern after automatic layout design, if the timing constraint cannot be satisfied by a spare cell, the position range satisfies the timing constraint. Detect a used cell closest to the connection target or spare cell from existing cells of the same type as a spare cell, and use the detected used cell used instead of the spare cell as a new connection target. If the layout design auxiliary system unit 20 using the spare cell is finally provided by repeatedly performing the process of connecting the used cell closest to the spare cell until the spare cell appears in a position range that satisfies the timing constraint, the conventional technology Even in spare cell arrangements such as Automatically to change the input netlist in Zushirikon ECO, can achieve the object of the present invention capable of performing freeze silicon ECO using the net list.

  As mentioned above, although this invention has been illustrated using preferable embodiment of this invention, this invention should not be limited and limited to this embodiment. It is understood that the scope of the present invention should be construed only by the claims. It is understood that those skilled in the art can implement an equivalent range from the description of specific preferred embodiments of the present invention based on the description of the present invention and common general technical knowledge. Patents, patent applications, and documents cited herein should be incorporated by reference in their entirety, as if the contents themselves were specifically described herein. Understood.

  In the layout design of a large-scale semiconductor integrated circuit (LSI) or the like, the present invention is a method of performing placement and routing processing only on a place where logic has been changed (hereinafter referred to as ECO). Replacement redundant cells (hereinafter referred to as spare cells) to be used at the time of change are arranged in advance, and the mask layer in the manufacturing process is changed for the wiring layer and contact layer using the arrangement elements (hereinafter referred to as instances). In the ECO method (hereinafter referred to as “freeze silicon ECO”) in which the logic is changed, the timing constraint is satisfied when the timing constraint cannot be satisfied by the static timing analysis executed in the design apparatus. Layout design method for semiconductor integrated circuit that performs freeze silicon ECO Semiconductor integrated circuit layout design assisting system used in the design method, semiconductor integrated circuit automatic layout designing apparatus equipped with the layout design assisting system, photomask having a mask pattern generated using the automatic layout designing apparatus, Photomask manufacturing method for manufacturing this photomask, semiconductor integrated circuit manufactured using photomask, semiconductor integrated circuit manufacturing method for manufacturing semiconductor integrated circuit using photomask, and layout design method for semiconductor integrated circuit In the field of a control program for causing a computer to execute each step of the above and a computer-readable readable storage medium storing the control program, if the timing constraint is not satisfied in the freeze silicon ECO function, Enormous labor as in the prior art that needs to be bets change is not required. In addition, it is possible to satisfy the timing constraint with the freeze silicon ECO with a high probability without modifying layers other than the wiring layer and the contact layer, or arranging in advance more spare cell instances than the current level. Freeze silicon ECO can be performed to automatically satisfy timing constraints, so it is effective to increase the design period and mask cost in the logic change, cause human error, and increase the chip area of the initial design. Can be prevented. Therefore, it is possible to manufacture a semiconductor device with few operational errors efficiently and an electronic device on which the semiconductor device is mounted at low cost, and can greatly contribute to the spread of this freeze silicon ECO.

It is a block diagram which shows the principal part function structural example of the automatic layout design apparatus of the semiconductor integrated circuit which concerns on embodiment of this invention. It is a schematic diagram showing a circuit configuration example for simply explaining the principle of the present invention. FIG. 2 is a block diagram illustrating a hardware configuration example of a main part of the automatic layout design apparatus for the semiconductor integrated circuit of FIG. 1. 5 is a flowchart for explaining an example of a processing procedure in a layout design method for a semiconductor integrated circuit according to an embodiment of the present invention. FIG. 5 is a diagram showing a netlist example of a layout before logical change in the semiconductor integrated circuit layout design method of FIG. 4. FIG. 6 is a diagram showing an example of a netlist whose logic is changed and inputted to an automatic placement and routing processing unit in order to perform freeze silicon ECO in the layout design method of the semiconductor integrated circuit of FIG. 4. FIG. 5 is a circuit diagram schematically showing a mask layout before freeze silicon ECO processing in a logical format in the layout design method for the semiconductor integrated circuit of FIG. 4. FIG. 5 is a circuit diagram showing, in logical form, simplified processing by a spare cell direction range detection block in the layout design method for the semiconductor integrated circuit of FIG. 4. FIG. 5 is a circuit diagram schematically showing processing by a timing constraint satisfaction range detection block in a logical format in the semiconductor integrated circuit layout design method of FIG. 4. FIG. 5 is a circuit diagram showing, in a logical form, simplified processing by an used instance replacement block in the semiconductor integrated circuit layout design method of FIG. FIG. 5 is a diagram showing an example of a netlist input to an automatic placement and routing processing unit changed by an already used instance replacement block in the semiconductor integrated circuit layout design method of FIG. 4. FIG. 5 is a circuit diagram schematically showing, in logical form, a result of repeating each process one or more times by a replacement propagation means in the layout design method for the semiconductor integrated circuit of FIG. 4. FIG. 5 is a diagram illustrating an example of a net list input to an automatic placement and routing processing unit changed by a replacement propagation unit in the semiconductor integrated circuit layout design method of FIG. 4. It is a flowchart for demonstrating the other process sequence example in the layout design method of the semiconductor integrated circuit which concerns on embodiment of this invention. FIG. 10 is a diagram for explaining a conventional layout design method for a semiconductor integrated circuit disclosed in Patent Document 1; FIG. 10 is a diagram for explaining a conventional layout design method for a semiconductor integrated circuit disclosed in Patent Document 2. It is a schematic diagram which shows the example of a circuit structure for demonstrating briefly the principle in the case of a prior art.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Automatic layout design apparatus 2 Arithmetic processing apparatus 20 Layout design auxiliary system part (layout design auxiliary computer system)
21 Spare cell detection block (spare cell detection means)
22 Spare cell direction range detection block (spare cell direction range detection means)
23 Timing constraint satisfaction range detection block (timing constraint satisfaction range detection means)
24 Used replacement cell instance detection block (used replacement cell instance detection means)
25 Used replacement instance replacement block (used replacement instance replacement means)
26 Reference terminal coordinate reset block (reference terminal coordinate reset means; replacement propagation means)
3 Display 4 Keyboard 5 Mouse 6 ROM (Readable Recording Medium)
7 RAM
DESCRIPTION OF SYMBOLS 11 Mask pattern database 12 Automatic placement and routing processing unit 13 Netlist storage unit 14 Interface unit 15 Static timing analysis processing unit 201 Used instance of NOR cell 202 Used instance of NAND cell 203 Used instance of INV cell 204 NAND cell Used instance 205 used instance of INV cell 206 used instance of NAND cell 207 used instance of NOR cell 208 used instance of INV cell 209 used instance of NOR cell 210 used instance of INV cell 211 spare cell of INV cell Instances (redundant cells)
A1 Direction range including instance direction of spare cell A2 Distance range satisfying timing constraint θ1 Angle set to specific range of direction including instance direction of spare cell

Claims (60)

After the automatic layout design of the semiconductor integrated circuit, in order to change the logic by changing the mask layer in the manufacturing process for the wiring layer and the contact layer, redundant cells used for the logic change are arranged in advance during the cell layout design, In the layout design method that enables the redundant cell to be connected to the connection target,
When the layout design auxiliary computer system makes a logical change to the mask pattern after the automatic layout design, if the timing constraint cannot be satisfied by the redundant cell, the position range is set to satisfy the timing constraint. Among the used cells of the same type as the redundant cell, the connection target or the used cell closest to the redundant cell is detected, and the detected used cell used instead of the redundant cell is newly connected The process of connecting the newly connected cell or the used cell closest to the redundant cell is repeated until the redundant cell appears in a position range that satisfies the timing constraint, and finally the redundant cell A layout design method for a semiconductor integrated circuit having a layout design auxiliary step using The layout design auxiliary step includes
Spare cell detection means detects a redundant cell to be connected to the connection target, a spare cell detection step;
Spare cell direction range detection means detects a direction range including the direction of the redundant cell from the position to be connected, a spare cell direction range detection step;
A timing constraint satisfaction range detection step in which the timing constraint satisfaction range detection means detects a distance range that satisfies a timing constraint related to the clock signal in the detected direction range; and
When the used replacement cell instance detection means does not have the redundant cell in the detected distance range, the distance range is selected from the same type of cells as the redundant cell already incorporated in the circuit. A used replacement cell instance detection step of detecting a cell closest to the connection target or the redundant cell in
A used instance replacement means for disconnecting the detected cell and connecting to the connection target;
2. The semiconductor according to claim 1, wherein the replacement propagation means includes a replacement propagation step in which each step is repeatedly performed one or more times until the redundant cell is finally replaced so as to satisfy a timing constraint relating to the clock signal. Integrated circuit layout design method.   The layout design method for a semiconductor integrated circuit according to claim 2, wherein the spare cell detecting step detects a redundant cell existing at a location where the straight line distance from the connection target is the shortest.   4. The spare cell detection step detects redundant cells to be connected to the connection target using an automatic layout tool that changes a mask layer in a manufacturing process for a wiring layer and a contact layer to change logic. The layout design method of the semiconductor integrated circuit as described.   3. The layout design method for a semiconductor integrated circuit according to claim 2, wherein the spare cell direction range detection step detects the direction range as a positional relationship between the connection target and the redundant cell.   In the spare cell direction range detection step, when detecting the positional relationship between the connection target and the redundant cell, the relationship between the terminal of the redundant cell and the terminal of the connection target on the circuit diagram information or the netlist The layout design method for a semiconductor integrated circuit according to claim 5, wherein the method is detected.   Centering on a predetermined position of the connection target, a straight line connecting the redundant cell and the connection target is used as a radius, and the direction of the redundant cell from the connection target is calculated as an angle. The angle of a predetermined range is specified for each direction, the sum is used as a central angle, the redundant cell side is calculated as an arc side, and the direction range is calculated as a sector area having the radius. A layout design method for a semiconductor integrated circuit according to any one of the above.   8. The spare cell direction range detection step calculates, as the radius, the length of a straight line connecting the terminal coordinates of the redundant cell and the terminal coordinates of the connection target to be connected to the radius from the coordinates. Layout design method for semiconductor integrated circuit.   In the spare cell direction range detection step, the direction from the connection target to the redundant cell is determined using a trigonometric function from the terminal coordinates of the redundant cell and the terminal coordinates of the connection target to be connected to the redundant cell. The layout design method for a semiconductor integrated circuit according to claim 7, wherein the direction is calculated as an angle.   8. The layout design method for a semiconductor integrated circuit according to claim 7, wherein in the spare cell direction range detection step, an angle within a range of 0 degrees or more and 180 degrees or less is specified as an angle of the predetermined range in the positive direction and the negative direction, respectively. .   The spare cell direction range detection step is sandwiched between a straight line of a linear equation passing through the central coordinates of the connection target and a straight line of another linear equation passing through the central coordinates when detecting the sector area by graphic calculation processing. 8. The layout design method for a semiconductor integrated circuit according to claim 7, wherein an area having a distance from the center coordinate smaller than the radius value is detected from the area of the center angle.   The timing constraint satisfaction range detection step calculates a distance range from the connection target that satisfies a timing constraint related to a clock signal by calculating a resistance and a capacitance from the width and length of the wiring connected to the connection target. 3. The layout design method for a semiconductor integrated circuit according to claim 2, wherein a distance range that satisfies a timing constraint is detected in the detected direction range.   The timing constraint satisfaction range detection step uses a delay value calculated from resistance and capacitance per length of wiring connected to the connection target by performing static timing analysis on the original circuit diagram. Then, the margin from the setup time and hold time of the current timing is determined, and the wiring length within the range satisfying the timing constraint calculated from the margin is determined by the difference between the coordinates of the connection target and the redundant cell. After calculating the Manhattan distance with the sum of absolute values as the distance between the two points, the linear distance between the two starting and ending points of each coordinate is calculated, and the calculated linear distance is the distance from the center. 3. The layout design method for a semiconductor integrated circuit according to claim 2, wherein a range inside the region is detected.   The used replacement cell instance detection step detects all cells of the same type as the redundant cell that exist in the distance range detected by the timing constraint satisfaction range detection step, and the connection target terminal for each terminal coordinate 3. The layout design method for a semiconductor integrated circuit according to claim 2, wherein a straight line distance to the coordinates is calculated, and a terminal coordinate of the cell of the same type that is the shortest or longest in each straight line distance is detected.   The used replacement cell instance detection step is an error process that is performed when the same type of cells as the redundant cells are not already used in the distance range detected by the timing constraint satisfaction range detection step. The layout design method for a semiconductor integrated circuit according to claim 2, wherein the used replacement cell instance detection process is stopped.   The used replacement cell instance detecting step is performed when the terminal of the same type of cell as the redundant cell is not already used in the distance range detected by the timing constraint satisfaction range detecting step. 3. The layout design method for a semiconductor integrated circuit according to claim 2, wherein an angle designated as an angle in a predetermined direction in the direction and the negative direction is changed to a larger value to widen the distance range.   The used replacement cell instance detection step is 5 if the angle specified in the positive direction and the negative direction is 90 degrees or less, and the angle is 85 degrees or less with respect to the spare cell direction range detection step. 17. The method of designing a layout of a semiconductor integrated circuit according to claim 16, wherein if the angle is greater than 85 degrees and not greater than 90 degrees, the angle is specified as 90 degrees.   18. The used replacement cell instance detection step performs the stop processing of the used replacement cell instance detection process as an error process when the angles specified in the positive direction and the negative direction are each greater than 90 degrees. The layout design method of the semiconductor integrated circuit as described.   In the used instance replacement step, the wiring to both terminals of the cell detected in the used replacement cell instance detection step is disconnected, and the terminal of the disconnected cell and the connection target terminal are connected by wiring. 3. The layout design method for a semiconductor integrated circuit according to claim 2, wherein a net list used for automatic placement and routing processing is changed.   In the case where the used instance replacement step includes an instance that is not logically changed next as an instance of the cell detected in the used replacement cell instance detecting step, an output terminal of an instance immediately before the next instance that is not logically changed; 3. The layout design method for a semiconductor integrated circuit according to claim 2, wherein a net list used for automatic placement and routing processing is changed so that an input terminal of an instance that is not logically changed next is connected.   In the case where the used instance replacement step includes an instance that is logically changed next as an instance of the cell detected in the used replacement cell instance detection step, the output terminal of the next logically changed instance is 3. The layout design method for a semiconductor integrated circuit according to claim 2, wherein the processing is performed again from the spare cell detection step to the used instance replacement step by resetting as an output terminal of the instance immediately before the location where the logic change is applied. .   3. The semiconductor according to claim 2, wherein in the replacement propagation step, a position coordinate of an instance replaced by the used instance replacement step is set as a reference coordinate for obtaining a direction in the processing by the spare cell direction range detection step. Integrated circuit layout design method.   In the replacement propagation step, the instance disconnected in the used instance replacement step is reset as a new connection target in the spare cell direction range detection step, and the redundant cell is detected in the timing constraint satisfaction range detection step. 23. The layout design method for a semiconductor integrated circuit according to claim 22, wherein the processing of each step from the spare cell direction range detection step to the used instance replacement step is repeated once or a plurality of times.   The replacement propagation step resets the terminal coordinates of the instance immediately before being disconnected in the used instance replacement step as a new connection target in the spare cell direction range detection step, and the redundant cell in the timing constraint satisfaction range detection step 23. The layout design method for a semiconductor integrated circuit according to claim 22, wherein the processing of each step from the spare cell direction range detection step to the used instance replacement step is repeated one or more times until an instance is detected.   The replacement propagation step re-sets the coordinates of the circuit part that has been replaced by the used instance replacement step as a new connection target in the spare cell direction range detection step, and the redundancy restriction is detected in the timing constraint satisfaction range detection step. 23. The layout design method for a semiconductor integrated circuit according to claim 22, wherein the processing of each step from the spare cell direction range detection step to the used instance replacement step is repeated one or more times until a cell instance is detected. After the automatic layout design of the semiconductor integrated circuit, in order to change the logic by changing the mask layer in the manufacturing process for the wiring layer and the contact layer, redundant cells used for the logic change are arranged in advance during the cell layout design, In an automatic layout design apparatus for a semiconductor integrated circuit that controls connection of the redundant cell to a connection target,
When a logical change is made to the mask pattern after the automatic layout design, if the timing constraint cannot be satisfied by the redundant cell, it is the same as the redundant cell in the position range that satisfies the timing constraint. From the types of used cells, the connection target or the used cell closest to the redundant cell is detected, and the detected used cell used in place of the redundant cell is used as a new connection target. Alternatively, the layout design auxiliary computer system using the redundant cell at the end is performed by repeatedly performing the process of connecting the used cell closest to the redundant cell until the redundant cell appears in a position range that satisfies the timing constraint. An automatic layout design apparatus for semiconductor integrated circuits. The layout design auxiliary computer system includes:
Spare cell detection means for detecting redundant cells to be connected to the connection target;
Spare cell direction range detecting means for detecting a direction range including the direction of the redundant cell from the position to be connected;
Timing constraint satisfaction range detection means for detecting a distance range that satisfies the timing constraint related to the clock signal in the detected direction range; and
When the redundant cell does not exist in the detected distance range, the connection target or the redundant cell within the distance range is selected from the same type of cells as the redundant cell that are already included in the circuit. Used replacement cell instance detection means for detecting the closest cell from
Used instance replacement means for disconnecting the detected cell and connecting to the connection target;
27. An automatic layout of a semiconductor integrated circuit according to claim 26, further comprising replacement propagation means for repeatedly performing each processing one or more times until the redundant cell is finally replaced so as to satisfy the timing constraint relating to the clock signal. Design equipment.   28. The automatic layout design apparatus for a semiconductor integrated circuit according to claim 27, wherein the spare cell detecting means detects a redundant cell existing at a location where a linear distance from the connection target is the shortest.   The spare cell detection means detects a redundant cell to be connected to the connection target using an automatic layout tool that changes a mask layer in a manufacturing process for a wiring layer and a contact layer to change a logic. The automatic layout design apparatus of the semiconductor integrated circuit as described.   28. The automatic layout design apparatus for a semiconductor integrated circuit according to claim 27, wherein the spare cell direction range detecting means detects the direction range as a positional relationship between the connection target and the redundant cell.   When the spare cell direction range detection means detects the positional relationship between the connection target and the redundant cell, the relationship between the terminal of the redundant cell and the terminal of the connection target on the circuit diagram information or netlist 32. The automatic layout design apparatus for a semiconductor integrated circuit according to claim 30, wherein the automatic layout design apparatus detects the signal.   Centering on the position of the connection target, a straight line connecting the redundant cell and the connection target is used as a radius, and the direction of the redundant cell from the connection target is calculated as an angle. From the calculated angle, a positive direction and a negative direction are calculated. 32. Any one of claims 26, 30 and 31, wherein an angle within a predetermined range is specified for each direction, the sum of the angles is set as a central angle, the redundant cell side is set as an arc side, and the direction range is calculated as a sector area having the radius. An automatic layout design apparatus for a semiconductor integrated circuit according to claim 1.   33. The automatic layout of a semiconductor integrated circuit according to claim 32, wherein the spare cell direction range detecting means calculates, as the radius, the length of a straight line connecting the terminal coordinates of the redundant cell and the terminal coordinates of the connection target from the respective coordinates. Design equipment.   The spare cell direction range detecting means calculates a direction from the connection target to the redundant cell, and uses a trigonometric function from the terminal coordinates of the redundant cell and the terminal coordinates of the connection target as an angle. Item 33. An automatic layout design apparatus for a semiconductor integrated circuit according to Item 32.   33. The automatic layout design of a semiconductor integrated circuit according to claim 32, wherein the spare cell direction range detection means designates an angle within a range of 0 degrees or more and 180 degrees or less as an angle of the predetermined range in the positive direction and the negative direction, respectively. apparatus.   The spare cell direction range detection means is sandwiched between a straight line of a linear equation passing through the central coordinates of the connection target and a straight line of another linear equation passing through the central coordinates when detecting the sector area by graphic calculation processing. 33. The automatic layout design apparatus for a semiconductor integrated circuit according to claim 32, wherein an area having a distance from the center coordinate smaller than the value of the radius is detected from the area of the center angle.   The timing constraint satisfaction range detection means calculates resistance and capacitance from the width and length of the wiring connected to the connection target, and calculates a distance range from the connection target that satisfies the timing constraint related to the clock signal. 28. The automatic layout design apparatus for a semiconductor integrated circuit according to claim 27, wherein a distance range that satisfies a timing constraint is detected in the detected direction range.   The timing constraint satisfaction range detecting means uses a delay value calculated from resistance and capacitance per length of wiring connected to the connection target by performing static timing analysis on the original circuit diagram. Then, the margin from the setup time and hold time of the current timing is determined, and the wiring length within the range satisfying the timing constraint calculated from the margin is determined by the difference between the coordinates of the connection target and the redundant cell. After calculating the Manhattan distance with the sum of absolute values as the distance between the two points, the linear distance between the two starting and ending points of each coordinate is calculated, and the calculated linear distance is the distance from the center. 28. The automatic layout design apparatus for a semiconductor integrated circuit according to claim 27, wherein a range inside the area is detected.   The used replacement cell instance detection means detects all cells of the same type as the redundant cell that exist in the distance range detected by the timing constraint satisfaction range detection means, and the terminal coordinates of the connection target for each terminal coordinate 28. The automatic layout design apparatus for a semiconductor integrated circuit according to claim 27, wherein the straight line distance is calculated to detect the terminal coordinates of the cell of the same type that is the shortest or longest in each straight line distance.   The used replacement cell instance detection means is used as error processing when a cell of the same type as the redundant cell does not exist in the distance range detected by the timing constraint satisfaction range detection means. 28. The automatic layout design apparatus for a semiconductor integrated circuit according to claim 27, wherein the replacement cell instance detection process is stopped.   When the used replacement cell instance detection means does not exist in the distance range detected by the timing constraint satisfaction range detection means in a state where a cell of the same type as the redundant cell has already been used, the positive direction and 28. The automatic layout design apparatus for a semiconductor integrated circuit according to claim 27, wherein an angle designated as an angle within a predetermined range in the negative direction is changed to a larger value to widen the distance range.   The used replacement cell instance detection means is 5 if the angle specified in the positive direction and the negative direction is 90 degrees or less, and the angle is 85 degrees or less with respect to the spare cell direction range detection means. 42. The automatic layout design apparatus for a semiconductor integrated circuit according to claim 41, wherein if the angle is greater than 85 degrees and not greater than 90 degrees, 90 degrees is designated.   43. The used replacement cell instance detection means cancels the used replacement cell instance detection process as an error process when the angles specified in the positive direction and the negative direction are each greater than 90 degrees. The automatic layout design apparatus of the semiconductor integrated circuit as described.   The used instance replacement means disconnects the wiring to both terminals of the cell detected by the used replacement cell instance detection means, and connects the terminal of the disconnected cell and the terminal to be connected by wiring. 28. The automatic layout design apparatus for a semiconductor integrated circuit according to claim 27, wherein the net list used for the automatic placement and routing process is changed.   When the used instance replacement means includes an instance that is not logically changed next as an instance of the cell detected by the used replacement cell instance detection means, an output terminal of an instance immediately before the next instance that is not logically changed; 28. The automatic layout design apparatus for a semiconductor integrated circuit according to claim 27, wherein a net list used for automatic placement and routing processing is changed so that an input terminal of an instance that is not logically changed next is connected.   When the used instance replacement means includes an instance that is logically changed next as an instance of the cell detected by the used replacement cell instance detection means, the output terminal of the next logically changed instance is 28. The automatic layout design of a semiconductor integrated circuit according to claim 27, wherein the processing is performed again from the spare cell detection means to the used instance replacement means by resetting it as the output terminal of the instance immediately before the place where the logic change is applied. apparatus.   28. The semiconductor according to claim 27, wherein the replacement propagation means sets a position coordinate of an instance to be replaced by the used instance replacement means as a reference coordinate for obtaining a direction during processing by the spare cell direction range detection means. Integrated circuit automatic layout design equipment.   The replacement propagation unit resets the instance separated by the used instance replacement unit as a new connection target in the spare cell direction range detection unit, and the redundant cell is detected by the timing constraint satisfaction range detection unit. 48. The automatic layout design apparatus for a semiconductor integrated circuit according to claim 47, wherein each process from the spare cell direction range detection means to the used instance replacement means is repeated one or more times.   The replacement propagation means resets the terminal coordinates of the instance immediately before being disconnected by the used instance replacement means as a new connection target in the spare cell direction range detection means, and the timing constraint satisfaction range detection means detects the redundant cell. 48. The automatic layout design apparatus for a semiconductor integrated circuit according to claim 47, wherein each process from the spare cell direction range detection means to the used instance replacement means is repeated one or more times until an instance is detected.   The replacement propagation unit resets the coordinates of the circuit portion that has been replaced by the used instance replacement unit as a new connection target in the spare cell direction range detection unit, and the timing constraint satisfaction range detection unit detects the redundancy. 48. The automatic layout design apparatus for a semiconductor integrated circuit according to claim 47, wherein each process from the spare cell direction range detection means to the used instance replacement means is repeated one or more times until a cell instance is detected.   An arithmetic processing device equipped with the layout design auxiliary computer system, a display unit capable of displaying a screen related to the arithmetic processing of the arithmetic processing device, and an operation input command for the arithmetic processing of the arithmetic processing device 28. The automatic layout design apparatus for a semiconductor integrated circuit according to claim 26, further comprising an operation input unit.   Only the mask layer in the manufacturing process is changed in the wiring layer and the contact layer to satisfy the timing constraint related to the clock signal so that the redundant cell is finally replaced under the condition that satisfies the timing constraint related to the clock signal. 28. The automatic layout design apparatus for a semiconductor integrated circuit according to claim 26, wherein the logic change processing is performed as described above. The mask pattern stored in the mask pattern database and the netlist, which is text data describing the connection relationship between cells, are input, and the logic changes when designing the layout of cells and the wiring between cells An automatic placement and routing processing unit for generating circuit diagram information or a netlist in which redundant cells are sometimes used; and
An interface unit capable of operating and inputting externally input parameters to the netlist storage unit storing the netlist and the spare cell direction range detecting means, and outputting mask pattern data from the mask pattern database to the outside;
Static timing analysis is performed using circuit diagram information or a net list from the automatic placement and routing processing unit, and a delay value is calculated from the resistance and capacitance per length of the wiring connected to the connection target, and the timing constraint 28. The automatic layout design apparatus for a semiconductor integrated circuit according to claim 27, further comprising a static timing analysis processing unit that supplies the satisfaction range detection means. It consists of a computer system,
Spare cell detection means for detecting redundant cells to be connected to the connection target;
Spare cell direction range detecting means for detecting a direction range including the direction of the redundant cell from the position to be connected;
Timing constraint satisfaction range detection means for detecting a distance range that satisfies the timing constraint related to the clock signal in the detected direction range; and
When the redundant cell does not exist in the detected distance range, the connection target or the redundant cell within the distance range is selected from the same type of cells as the redundant cell that are already included in the circuit. Used replacement cell instance detection means for detecting the closest cell from
Used instance replacement means for disconnecting the detected cell and connecting to the connection target;
A layout design assisting system for a semiconductor integrated circuit, comprising replacement propagation means for repeatedly performing each process one or more times until the redundant cell is finally replaced so as to satisfy the timing constraint relating to the clock signal.   54. A photomask manufactured based on mask pattern information designed using the automatic layout design apparatus for a semiconductor integrated circuit according to claim 26.   54. A photomask manufacturing method in which a photomask pattern is designed by the automatic layout design apparatus for a semiconductor integrated circuit according to claim 26, and the photomask is manufactured by patterning using the design information.   56. A semiconductor integrated circuit manufactured using the photomask according to claim 55.   54. A semiconductor layer provided on or on a semiconductor substrate by using the resist pattern patterned by the photomask pattern designed by the automatic layout design apparatus for a semiconductor integrated circuit according to claim 26 and patterned by the design information. A method for manufacturing a semiconductor integrated circuit, wherein a semiconductor integrated circuit is formed thereon.   A control program in which each processing procedure for causing a computer to execute each step of the semiconductor integrated circuit layout design method according to any one of claims 1 to 25 is recorded.   60. A computer readable storage medium storing the control program according to claim 59.

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