CN106815380B - Method and system for extracting parasitic resistance - Google Patents
Method and system for extracting parasitic resistance Download PDFInfo
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- CN106815380B CN106815380B CN201510849739.4A CN201510849739A CN106815380B CN 106815380 B CN106815380 B CN 106815380B CN 201510849739 A CN201510849739 A CN 201510849739A CN 106815380 B CN106815380 B CN 106815380B
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/20—Design optimisation, verification or simulation
- G06F30/23—Design optimisation, verification or simulation using finite element methods [FEM] or finite difference methods [FDM]
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/392—Floor-planning or layout, e.g. partitioning or placement
Abstract
The invention provides a method for extracting parasitic resistance, which comprises the following steps: simulating integrated circuit layout data; acquiring integrated circuit layout simulation data; and extracting parasitic resistance of the integrated circuit layout simulation data according to the integrated circuit process parameters. The invention also provides a system for extracting the parasitic resistance. The scheme of the invention can effectively solve the problem of inaccuracy in extracting the parasitic resistance caused by the geometric figure deviation between actual manufacturing and integrated circuit design in the manufacturing process of the integrated circuit, and improve the accuracy of extracting the parasitic resistance.
Description
Technical Field
The invention belongs to the field of integrated circuit design, and particularly relates to a method and a system for extracting parasitic resistance.
Background
With the development of technology, circuit optimization becomes an important stage in the design flow of integrated circuits. The purpose of circuit optimization is to improve the electrical performance of the circuit, and the final actual electrical performance of the circuit depends on not only the device parameter values of the circuit, but also the parasitic effects of the devices, the parasitic effects between the devices, the parasitic effects of the wires, the parasitic effects between the wires, and the parasitic effects between the wires and the devices, wherein the parasitic effects between adjacent wires are particularly critical. Theoretically, in order to obtain accurate circuit optimization results, the parasitic effects between the device interconnections on the designed circuit, including the parasitic resistances between the interconnection lines, need to be considered accurately.
The premise of the traditional method for extracting the parasitic resistance is that the deviation between a geometric figure actually manufactured in the manufacturing process of an integrated circuit and a geometric figure in layout data obtained by designing the integrated circuit on an X-Y plane is very small and can be ignored, and the deviation in a Z direction is very small and can be ignored. Therefore, as shown in fig. 1, a conventional method for extracting parasitic resistance is to extract parasitic resistance from design data of an integrated circuit layout by a parasitic resistance extraction engine according to integrated circuit process parameters to form a parasitic resistance netlist.
With the continuous progress of the integrated circuit technology, the feature size of the integrated circuit technology is continuously reduced, the spacing between the interconnection lines is also continuously reduced, because of the inconsistency of optical effect caused by the difference of adjacent patterns, the edge roughness caused by the difference of etching directionality, the metal chemical-mechanical-grinding (polishing) inconsistency caused by the difference of metal pattern density, etc., the deviation between the geometric figure actually manufactured in the integrated circuit manufacturing process and the geometric figure in the layout data obtained by the integrated circuit design is large, the deviation is not only expressed as the geometric figure difference on an X-Y plane (parallel to a silicon wafer plane) but also expressed as the geometric figure difference on a Z direction (perpendicular to the silicon wafer plane), and the influence of the change of parasitic resistance on the circuit function and performance is obvious, cannot be ignored. The premise assumption of the traditional method for extracting the parasitic resistance is no longer true, so that the traditional method for extracting the parasitic resistance is no longer suitable for extracting the parasitic resistance of the integrated circuit layout under the advanced integrated circuit process, and is particularly not suitable for extracting the parasitic resistance of the high-speed and high-frequency integrated circuit layout under the advanced integrated circuit process. Therefore, a new method for extracting the parasitic resistance between the metal interconnection lines of the integrated circuit layout with high precision is needed.
Disclosure of Invention
The invention provides a method and a system for extracting parasitic resistance, which solve the problem of inaccurate extraction of parasitic resistance caused by geometric figure deviation between actual manufacturing and integrated circuit design in the manufacturing process of an integrated circuit,
in order to achieve the purpose, the invention provides the following technical scheme:
a method of extracting parasitic resistance, comprising the steps of:
simulating integrated circuit layout data;
acquiring integrated circuit layout simulation data;
and extracting parasitic resistance of the integrated circuit layout simulation data according to the integrated circuit process parameters.
Preferably, the integrated circuit layout data includes: data of the geometry on the X-Y plane on each physical layer and data of the geometry in the Z direction on each physical layer.
Preferably, the simulating the integrated circuit layout data includes:
photoetching and simulating the layout data on each physical layer of the integrated circuit on an X-Y plane to obtain a geometric shape curve of each geometric figure on the X-Y plane; and/or
And performing chemical-mechanical-grinding polishing simulation on the integrated circuit layout data in the Z direction to obtain a geometric shape curved surface of each geometric figure in the Z direction.
Preferably, the simulating the integrated circuit layout data includes:
and performing chemical-mechanical-grinding polishing simulation on the dielectric layers in the Z direction to obtain the geometric shape curved surfaces of the dielectric layers in the Z direction.
Preferably, the simulating the integrated circuit layout data includes:
the integrated circuit layout data is simulated in the order of the process steps employed for fabrication.
Preferably, the simulating the integrated circuit layout data further includes:
before the photoetching simulation is carried out, double photoetching layout decomposition or multiple photoetching layout decomposition is carried out on the integrated circuit layout data to obtain the decomposed integrated circuit layout data.
Preferably, the simulating the integrated circuit layout data further includes:
before the photoetching simulation is carried out, optical proximity effect correction is carried out on the integrated circuit layout data.
Preferably, the integrated circuit process parameters include: the resistivity of the physical connecting line layer, the thickness of the physical connecting line layer and the thickness of the dielectric layer;
the parasitic resistance extraction of the integrated circuit layout simulation data comprises the following steps:
constructing a solid geometric figure of a connecting line section on the same connecting line layer;
and calculating the parasitic resistance of the connecting line segment by using a finite element method or a boundary element method for the solid geometric figure.
Preferably, the building of the solid geometry of the connecting line segments on the same connecting line layer comprises: and constructing front, back, left and right surface morphologies, an upper surface morphology and a lower surface morphology by using the integrated circuit layout and simulation data of the connecting line segments on the same connecting line layer.
Preferably, the surface topography of the three-dimensional geometric figure for constructing the connecting line segments on the same connecting line layer comprises the following steps: on the basis of integrated circuit layout and simulation data of a connecting line segment on the same connecting line layer, front, back, left and right surface morphologies are constructed by using a geometric figure of the physical connecting line segment on an X-Y plane, or front, back, left and right surface morphologies are constructed by using a geometric figure morphology curve of the physical connecting line segment on the X-Y plane, or front, back, left and right surface morphologies are constructed by using a morphology curve of the geometric figure of the physical connecting line segment on the X-Y plane on a bottom surface and a morphology curve of a top surface.
Preferably, the step of constructing the lower surface topography of the solid geometry of the connecting line segments on the same connecting line layer comprises: on the basis of integrated circuit layout and simulation data of a connecting line segment on the same connecting line layer, a horizontal bottom surface is constructed to serve as a lower surface, or a morphological curved surface in the Z direction corresponding to the upper surface of a dielectric layer below a region where the connecting line segment layout graph is located is utilized as the lower surface.
Preferably, the constructing of the upper surface appearance of the solid geometry of the connecting line segments on the same connecting line layer comprises: on the basis of integrated circuit layout and simulation data of a connecting line segment on the same connecting line layer, a horizontal upper surface is created at a position above a horizontal lower surface and at a distance of the thickness value of the connecting line layer, or a shape curved surface of a layout graph of the connecting line segment in the Z direction is used as the upper surface.
The present invention also provides a system for extracting parasitic resistance, comprising:
the simulation module is used for simulating the integrated circuit layout data to obtain the integrated circuit layout simulation data;
and the extraction module is used for extracting the parasitic resistance of the integrated circuit layout simulation data according to the integrated circuit process parameters.
Preferably, the simulation module includes:
the first simulation unit is used for carrying out photoetching simulation on the integrated circuit layout data on an X-Y plane so as to obtain the geometric appearance on the X-Y plane; and/or
And the second simulation unit is used for carrying out chemical-mechanical-polishing simulation on the integrated circuit layout data in the Z direction so as to obtain the geometric appearance in the Z direction.
Preferably, the simulation module further includes: and the third simulation unit is used for performing chemical-mechanical-polishing simulation on the integrated circuit layout data in the Z direction to obtain the geometric morphology of each dielectric layer in the Z direction.
Preferably, the simulation module further includes:
and the layout decomposition module is used for firstly carrying out double photoetching layout decomposition or multi-photoetching layout decomposition on the integrated circuit layout data before carrying out the photoetching simulation so as to obtain the decomposed integrated circuit layout data.
Preferably, the simulation module further includes:
and the correction module is used for correcting the integrated circuit layout data by the optical proximity effect before the photoetching simulation is carried out.
Preferably, the integrated circuit process parameters include: the resistivity of the physical connecting line layer, the thickness of the physical connecting line layer and the thickness of the dielectric layer;
the extraction module comprises:
and the solid geometric figure construction module is used for constructing the front, back, left and right surface appearances, the upper surface appearance and the lower surface appearance of the solid geometric figure by utilizing the integrated circuit layout and the simulation data of the connecting line segments on the same connecting line layer.
And the resistance calculation module is used for calculating the parasitic resistance of the connecting line segment by using a finite element or boundary element method for the solid geometric figure.
Preferably, the solid geometry construction module includes:
the front, back, left and right surface appearance building module is used for building the front, back, left and right surface appearances by utilizing the geometric figures of the physical connecting line on the X-Y plane or the geometric figure appearance curves of the physical connecting line on the X-Y plane or the front, back, left and right surface appearances by utilizing the appearance curves of the geometric figures of the physical connecting line on the X-Y plane on the bottom surface and the appearance curves of the top surface on the basis of the integrated circuit layout and the simulation data of the connecting line segment on the same connecting line layer.
And the lower surface construction module is used for constructing a horizontal bottom surface as a lower surface on the basis of the integrated circuit layout and simulation data of the connecting line segment on the same connecting line layer, or utilizing a morphological curved surface in the Z direction corresponding to the upper surface of the dielectric layer below the region where the layout graph of the connecting line segment is positioned as the lower surface.
And the upper surface construction module is used for creating a horizontal upper surface at a position which is above the horizontal lower surface and has a distance of the thickness value of the connecting line layer on the basis of the integrated circuit layout and the simulation data of the connecting line segments on the same connecting line layer, or using the topographic curved surface of the layout graph of the connecting line segments in the Z direction as the upper surface.
Therefore, the method and the system for extracting the parasitic resistance provided by the invention have the advantages that the integrated circuit layout data is simulated firstly, then the parasitic resistance is extracted, the problem of inaccuracy of the extracted parasitic resistance caused by the geometric figure deviation of actual manufacturing and integrated circuit design in the manufacturing process of the integrated circuit can be effectively solved, and the accuracy of parasitic resistance extraction is improved. The method and the system are also suitable for extracting the parasitic resistance of the high-speed and high-frequency integrated circuit layout under the advanced integrated circuit process.
Drawings
In order to more clearly describe the specific embodiments of the present invention, the drawings to be used in the embodiments will be briefly described below.
FIG. 1: is a schematic diagram of a method for extracting parasitic resistance in the prior art;
FIG. 2: the invention provides a flow chart of a method for extracting parasitic resistance;
FIG. 3: a schematic diagram of a method for extracting a parasitic resistance according to a first embodiment of the present invention;
FIG. 4: a schematic diagram of a method for extracting a parasitic resistance according to a second embodiment of the present invention;
FIG. 5: a schematic diagram of a method for extracting a parasitic resistance according to a third embodiment of the present invention;
FIG. 6: a schematic diagram of a method for extracting a parasitic resistance according to a fourth embodiment of the present invention;
FIG. 7: the invention provides a system structure schematic diagram for extracting parasitic resistance.
Detailed Description
In order to make the technical field of the invention better understand the scheme of the embodiment of the invention, the embodiment of the invention is further described in detail with reference to the drawings and the implementation mode.
In the manufacturing process of an integrated circuit under an advanced integrated circuit process, the deviation between the actually manufactured geometric figure and the geometric figure in layout data obtained by design directly influences the accuracy of extracting the parasitic resistance, and possibly causes the inaccuracy of a performance result of circuit optimization.
Fig. 2 is a flow chart of a method for extracting parasitic resistance according to the present invention. The method comprises the following steps:
s1: simulating integrated circuit layout data;
s2: acquiring integrated circuit layout simulation data;
s3: and extracting parasitic resistance of the integrated circuit layout simulation data according to the integrated circuit process parameters.
Further, the integrated circuit layout data includes: data of the geometry on the X-Y plane on each physical layer and data of the geometry in the Z direction on each physical layer.
Specifically, the integrated circuit layout data also includes: the geometric figure shape curve data of each physical layer circuit layout geometric figure on an X-Y plane and the geometric figure shape curved surface data of each physical layer layout geometric figure on each layer circuit layout Z direction. The data may include: dielectric layer thickness, interconnect line length, etc.
Fig. 3 is a schematic diagram of a method for extracting parasitic resistance according to a first embodiment of the present invention. The method for simulating the integrated circuit layout data comprises the following steps: photoetching simulation is carried out on the integrated circuit layout data on an X-Y plane to obtain geometric shape curves of all geometric figures on the X-Y plane; and/or performing chemical-mechanical-grinding and polishing simulation on the integrated circuit layout data in the Z direction to obtain a geometric shape curved surface of each geometric figure in the Z direction.
Further, the simulating the integrated circuit layout data includes: and performing chemical-mechanical-grinding polishing simulation on the dielectric layers in the Z direction to obtain the geometric shape curved surfaces of the dielectric layers in the Z direction.
Further, the simulating the integrated circuit layout data includes: the integrated circuit layout data is simulated in the order of the process steps employed for fabrication.
In practical application, the integrated circuit layout data is simulated by various simulation methods. The embodiment adopts the following steps: photoetching simulation is carried out on an X-Y plane to obtain a geometric shape curve of each geometric figure on the X-Y plane, so that data such as the length of an interconnection line, the width of the interconnection line and the like are obtained; and performing chemical-mechanical-grinding polishing simulation in the Z direction to obtain a geometric shape curve of each geometric figure in the Z direction, and obtaining data such as interconnection line thickness distribution from the geometric shape curve on the X-Y plane and the geometric shape curve in the Z direction. Meanwhile, the simulation may be: the photoetching simulation is only carried out on the X-Y plane, the chemical-mechanical-grinding polishing simulation is only carried out on the Z direction, and the photoetching simulation and the chemical-mechanical-grinding polishing simulation in the Z direction are sequentially carried out on the X-Y plane.
Fig. 4 is a schematic diagram of a method for extracting parasitic resistance according to a second embodiment of the present invention. The method for simulating the integrated circuit layout data further comprises the following steps: before the photoetching simulation is carried out, double photoetching layout decomposition or multiple photoetching layout decomposition is carried out on the integrated circuit layout data to obtain the decomposed integrated circuit layout data.
Specifically, in order to perform lithography simulation on the integrated circuit layout data more accurately, performing double lithography layout decomposition or multiple lithography layout decomposition on the integrated circuit layout data is a good approach, and other methods may be adopted. And photoetching simulation can be carried out on the X-Y plane on the decomposed layout data, and photoetching simulation and chemical-mechanical-grinding polishing simulation in the Z direction can also be carried out on the X-Y plane in sequence.
Fig. 5 and 6 are schematic diagrams of methods for extracting parasitic resistance according to the third and fourth embodiments of the present invention. The method for simulating the integrated circuit layout data further comprises the following steps: before the photoetching simulation is carried out, optical proximity effect correction is carried out on the integrated circuit layout data.
Specifically, the accuracy of performing lithography simulation is further improved, which may be performing lithography simulation on an X-Y plane after performing optical proximity effect correction on the integrated circuit layout data or sequentially performing lithography simulation on the X-Y plane and chemical-mechanical-grinding polishing simulation in the Z direction; or the integrated circuit layout data is firstly subjected to layout decomposition of double photoetching or layout decomposition of multiple photoetching, the decomposed layout data is corrected by an optical proximity effect, and finally photoetching simulation is carried out on an X-Y plane or photoetching simulation and chemical-mechanical-grinding polishing simulation are carried out on the X-Y plane in sequence.
Further, the integrated circuit process parameters include: the resistivity of the physical connecting line layer, the thickness of the medium layer and the like; the extracting parasitic resistance of the integrated circuit layout simulation data according to the integrated circuit process parameters comprises the following steps:
constructing a solid geometric figure of a connecting line section on the same connecting line layer;
and calculating the parasitic resistance of the connecting line segment by using a finite element method or a boundary element method for the solid geometric figure.
The method for constructing the solid geometric figure of the connecting line segments on the same connecting line layer comprises the following steps: and constructing front, back, left and right surface morphologies, an upper surface morphology and a lower surface morphology by using the integrated circuit layout and simulation data of the connecting line segments on the same connecting line layer.
The front, back, left and right surface appearances of the solid geometric figure of the connecting line segments on the same connecting line layer are constructed by the following steps: on the basis of integrated circuit layout and simulation data of a connecting line segment on the same connecting line layer, front, back, left and right surface morphologies are constructed by using a geometric figure of the physical connecting line segment on an X-Y plane, or front, back, left and right surface morphologies are constructed by using a geometric figure morphology curve of the physical connecting line segment on the X-Y plane, or front, back, left and right surface morphologies are constructed by using a morphology curve of the geometric figure of the physical connecting line segment on the X-Y plane on a bottom surface and a morphology curve of a top surface.
The lower surface morphology of the solid geometric figure of the connecting line segments on the same connecting line layer is constructed by the following steps: on the basis of integrated circuit layout and simulation data of a connecting line segment on the same connecting line layer, a horizontal bottom surface is constructed to serve as a lower surface, or a morphological curved surface in the Z direction corresponding to the upper surface of a dielectric layer below a region where the connecting line segment layout graph is located is utilized as the lower surface.
Constructing the upper surface appearance of the solid geometric figure of the connecting line segments on the same connecting line layer comprises the following steps: on the basis of integrated circuit layout and simulation data of a connecting line segment on the same connecting line layer, a horizontal upper surface is created at a position above a horizontal lower surface and at a distance of the thickness value of the connecting line layer, or a shape curved surface of a layout graph of the connecting line segment in the Z direction is used as the upper surface.
Specifically, the parasitic resistance extraction may be based on the basic formula R ═ Rs × L/W, where R is the parasitic resistance value, Rs is the sheet resistance, L is the bulk length, W is the bulk width, and Rs ═ ρ/t, where ρ is the bulk resistivity, and t is the bulk thickness.
Therefore, the invention provides a method for extracting parasitic resistance, which adopts the simulation of integrated circuit layout data to obtain more accurate geometric figure appearance curves on an X-Y plane and geometric figure curved surface data of the geometric figures in a Z direction, and then extracts the parasitic resistance, thereby effectively solving the problem of inaccurate extraction of the parasitic resistance caused by geometric figure deviation between actual manufacturing and integrated circuit design in the manufacturing process of the integrated circuit and improving the accuracy of parasitic resistance extraction.
The invention also provides a system for extracting parasitic resistance, as shown in fig. 7, which is a schematic structural diagram of the system for extracting parasitic resistance provided by the invention. The system comprises: the simulation module is used for simulating the integrated circuit layout data to obtain the integrated circuit layout simulation data; and the extraction module is used for extracting the parasitic resistance of the integrated circuit layout simulation data according to the integrated circuit process parameters.
In practical application, the extraction module may adopt a parasitic resistance extraction engine, and the parasitic resistance extraction engine extracts a parasitic resistance according to the integrated circuit process parameters to generate a parasitic resistance netlist. Of course, other methods of reporting parasitic resistance may be used, depending on the particular operating requirements.
The simulation module comprises: the first simulation unit and/or the second simulation unit. The first simulation unit is used for carrying out photoetching simulation on the integrated circuit layout data on an X-Y plane to obtain a shape curve geometric figure of the geometric figure on the X-Y plane; and the second simulation unit is used for performing chemical-mechanical-grinding and polishing simulation on the integrated circuit layout data in the Z direction to obtain a geometric shape curved surface figure of the geometric figure in the Z direction.
Further, the simulation module further comprises: and the third simulation unit is used for performing chemical-mechanical-polishing simulation on the integrated circuit layout data in the Z direction to obtain the geometric morphology of each dielectric layer in the Z direction.
In another embodiment of the system of the present invention, the simulation module may further comprise: and the layout decomposition module is used for firstly carrying out double photoetching layout decomposition or multi-photoetching layout decomposition on the integrated circuit layout data before carrying out the photoetching simulation so as to obtain the decomposed integrated circuit layout data.
Because the feature size of the integrated circuit process is continuously reduced, the spacing between the interconnection lines is also continuously reduced, in order to improve the accuracy of the lithography simulation, in the embodiment, the layout decomposition module is used for firstly carrying out the layout decomposition of the double lithography or the layout decomposition of the multiple lithography on the integrated circuit layout data, so that the decomposed layout data is more suitable for the process requirement of the lithography simulation, and the accuracy of the lithography simulation is improved. In practical application, the simulation module may further include a first simulation unit and a layout decomposition module, may also include a first simulation unit, a second simulation unit and a layout decomposition module, and may also include a first simulation unit, a second simulation unit, a third simulation unit and a layout decomposition module. Mainly selected by a specific selection process.
In another embodiment of the system of the present invention, the simulation module may further include: and the correction module is used for correcting the integrated circuit layout data by the optical proximity effect before the photoetching simulation is carried out.
Since layout data may be inaccurate due to the inconsistency of the optical proximity effect caused by the difference of the adjacent patterns in the integrated circuit, the layout data of the integrated circuit is corrected by the correction module, so that the consistency of the optical proximity effect is maintained, and the accuracy of the layout data is improved.
In practical application, the simulation module may also include a first simulation unit and a modification module, or include a first simulation unit, a second simulation unit, a third simulation unit and a modification module, or include a first simulation unit, a layout decomposition module and a modification module, or include a first simulation unit, a second simulation unit, a layout decomposition module and a modification module, or certainly include a first simulation unit, a second simulation unit, a third simulation unit, a layout decomposition module and a modification module.
Further, the integrated circuit process parameters include: physical link layer resistivity, physical link layer thickness, and dielectric layer thickness.
The extraction module comprises: the device comprises a solid geometric figure construction module and a resistance calculation module. The solid geometric figure construction module is used for constructing the front, back, left and right surface appearances, the upper surface appearance and the lower surface appearance of the solid geometric figure by utilizing the integrated circuit layout and the simulation data of the connecting line segments on the same connecting line layer. And the resistance calculation module is used for calculating the parasitic resistance of the connecting line segment by using a finite element or boundary element method for the solid geometric figure.
Further, the solid geometry construction module comprises: the device comprises a front surface, a rear surface, a left surface, a right surface, a surface appearance building module, a lower surface building module and an upper surface building module.
The front, back, left and right surface appearance construction module is used for constructing front, back, left and right surface appearances by using the geometric figures of the physical connecting line on the X-Y plane or the geometric figure appearance curves of the physical connecting line on the X-Y plane or the surface appearances of the front, back, left and right surfaces by using the appearance curves of the geometric figures of the physical connecting line on the X-Y plane on the bottom surface and the appearance curves of the top surface on the basis of the integrated circuit layout and the simulation data of the connecting line segment on the same connecting line layer.
The lower surface construction module is used for constructing a horizontal bottom surface as a lower surface on the basis of integrated circuit layout and simulation data of a connecting line segment on the same connecting line layer, or utilizing a morphological curved surface in the Z direction corresponding to the upper surface of a dielectric layer below the region where the layout graph of the connecting line segment is positioned as the lower surface.
And the upper surface construction module is used for creating a horizontal upper surface at a position which is above the horizontal lower surface and has a distance of the thickness value of the connecting line layer on the basis of the integrated circuit layout and simulation data of the connecting line segments on the same connecting line layer, or using the shape curved surface of the connecting line segment layout graph in the Z direction as the upper surface.
Therefore, the system for extracting the parasitic resistance provided by the invention adopts the simulation module and the extraction module to extract the parasitic resistance from the integrated circuit layout data according to the integrated circuit process parameters, can effectively solve the problem of inaccurate extraction of the parasitic resistance caused by geometric figure deviation between actual manufacturing and integrated circuit design in the manufacturing process of the integrated circuit, and improves the accuracy of parasitic resistance extraction.
The construction, features and functions of the present invention have been described in detail with reference to the embodiments shown in the drawings, but the present invention is not limited to the embodiments shown in the drawings, and all equivalent embodiments modified or modified by the spirit and scope of the present invention should be protected without departing from the spirit of the present invention.
Claims (16)
1. A method of extracting parasitic resistance, comprising the steps of:
simulating integrated circuit layout data;
acquiring integrated circuit layout simulation data;
extracting parasitic resistance of the integrated circuit layout simulation data according to integrated circuit process parameters;
the integrated circuit process parameters comprise: the resistivity of the physical connecting line layer, the thickness of the physical connecting line layer and the thickness of the dielectric layer;
the parasitic resistance extraction of the integrated circuit layout simulation data comprises the following steps:
constructing a solid geometric figure of a connecting line section on the same connecting line layer;
calculating the parasitic resistance of the connecting line segment by using a finite element method or a boundary element method for the solid geometric figure;
the method for constructing the solid geometric figure of the connecting line segments on the same connecting line layer comprises the following steps: and constructing front, back, left and right surface morphologies, an upper surface morphology and a lower surface morphology by using the integrated circuit layout and simulation data of the connecting line segments on the same connecting line layer.
2. The method of claim 1, wherein the integrated circuit layout data comprises: data of the geometry on the X-Y plane on each physical layer and data of the geometry in the Z direction on each physical layer.
3. The method of extracting parasitic resistance of claim 1, wherein said simulating integrated circuit layout data comprises:
photoetching and simulating the layout data on each physical layer of the integrated circuit on an X-Y plane to obtain a geometric shape curve of each geometric figure on the X-Y plane; and/or
And performing chemical-mechanical-grinding polishing simulation on the integrated circuit layout data in the Z direction to obtain a geometric shape curved surface of each geometric figure in the Z direction.
4. The method of claim 3, wherein the simulating integrated circuit layout data further comprises:
and performing chemical-mechanical-grinding polishing simulation on the dielectric layers in the Z direction to obtain the geometric shape curved surfaces of the dielectric layers in the Z direction.
5. The method for extracting parasitic resistance of claim 3 or 4, wherein the simulating integrated circuit layout data further comprises:
the integrated circuit layout data is simulated in the order of the process steps employed for fabrication.
6. The method of claim 3, wherein the simulating integrated circuit layout data further comprises:
before the photoetching simulation is carried out, double photoetching layout decomposition or multiple photoetching layout decomposition is carried out on the integrated circuit layout data to obtain the decomposed integrated circuit layout data.
7. The method of claim 3 or 6, wherein the simulating the integrated circuit layout data further comprises:
before the photoetching simulation is carried out, optical proximity effect correction is carried out on the integrated circuit layout data.
8. The method for extracting parasitic resistance as claimed in claim 7, wherein constructing the surface topography of the solid geometry of the connecting line segments on the same connecting line layer comprises: on the basis of integrated circuit layout and simulation data of a connecting line segment on the same connecting line layer, front, back, left and right surface morphologies are constructed by using a geometric figure of the physical connecting line segment on an X-Y plane, or front, back, left and right surface morphologies are constructed by using a geometric figure morphology curve of the physical connecting line segment on the X-Y plane, or front, back, left and right surface morphologies are constructed by using a morphology curve of the geometric figure of the physical connecting line segment on the X-Y plane on a bottom surface and a morphology curve of a top surface.
9. The method of claim 7, wherein constructing the lower surface topography of the solid geometry of the line segments on the same line level comprises: on the basis of integrated circuit layout and simulation data of a connecting line segment on the same connecting line layer, a horizontal bottom surface is constructed to serve as a lower surface, or a morphological curved surface in the Z direction corresponding to the upper surface of a dielectric layer below a region where the connecting line segment layout graph is located is utilized as the lower surface.
10. The method of claim 7, wherein constructing the upper surface topography of the solid geometry of the line segments on the same line level comprises: on the basis of integrated circuit layout and simulation data of a connecting line segment on the same connecting line layer, a horizontal upper surface is created at a position above a horizontal lower surface and at a distance of the thickness value of the connecting line layer, or a shape curved surface of a layout graph of the connecting line segment in the Z direction is used as the upper surface.
11. A system for extracting parasitic resistance, comprising:
the simulation module is used for simulating the integrated circuit layout data to obtain the integrated circuit layout simulation data;
the extraction module is used for extracting parasitic resistance of the integrated circuit layout simulation data according to integrated circuit process parameters;
the integrated circuit process parameters comprise: the resistivity of the physical connecting line layer, the thickness of the physical connecting line layer and the thickness of the dielectric layer;
the extraction module comprises:
the solid geometric figure construction module is used for constructing front, back, left and right surface appearances, upper surface appearances and lower surface appearances of the solid geometric figure by utilizing the integrated circuit layout and simulation data of the connecting line segments on the same connecting line layer;
and the resistance calculation module is used for calculating the parasitic resistance of the connecting line segment by using a finite element or boundary element method for the solid geometric figure.
12. The system for extracting parasitic resistance of claim 11, wherein the simulation module comprises:
the first simulation unit is used for carrying out photoetching simulation on the integrated circuit layout data on an X-Y plane so as to obtain the geometric appearance of each geometric figure on the X-Y plane; and/or
And the second simulation unit is used for performing chemical-mechanical-polishing simulation on the integrated circuit layout data in the Z direction to obtain the geometric appearance of each geometric figure in the Z direction.
13. The system for extracting parasitic resistance of claim 12, wherein said simulation module further comprises:
and the third simulation unit is used for performing chemical-mechanical-polishing simulation on the integrated circuit layout data in the Z direction to obtain the geometric morphology of each dielectric layer in the Z direction.
14. The system for extracting parasitic resistance of claim 12, wherein said simulation module further comprises:
and the layout decomposition module is used for firstly carrying out double photoetching layout decomposition or multi-photoetching layout decomposition on the integrated circuit layout data before carrying out the photoetching simulation so as to obtain the decomposed integrated circuit layout data.
15. The system for extracting parasitic resistance according to claim 12 or 14, wherein the simulation module further comprises:
and the correction module is used for correcting the integrated circuit layout data by the optical proximity effect before the photoetching simulation is carried out.
16. The system for extracting parasitic resistance of claim 11, wherein the solid geometry construction module comprises:
the front, back, left and right surface appearance building module is used for building the front, back, left and right surface appearances by utilizing the geometric figures of the physical connecting line on the X-Y plane on the basis of the integrated circuit layout and the simulation data of the connecting line segment on the same connecting line layer, or building the front, back, left and right surface appearances by utilizing the geometric figure appearance curves of the physical connecting line on the X-Y plane, or building the front, back, left and right surface appearances by utilizing the appearance curves of the geometric figures of the physical connecting line on the X-Y plane on the bottom surface and the appearance curves of the top surface;
the lower surface construction module is used for constructing a horizontal bottom surface as a lower surface on the basis of integrated circuit layout and simulation data of a connecting line segment on the same connecting line layer, or utilizing a morphological curved surface in the Z direction corresponding to the upper surface of a dielectric layer below a region where the layout graph of the connecting line segment is positioned as the lower surface;
and the upper surface construction module is used for creating a horizontal upper surface at a position which is above the horizontal lower surface and has a distance of the thickness value of the connecting line layer on the basis of the integrated circuit layout and the simulation data of the connecting line segments on the same connecting line layer, or using the topographic curved surface of the layout graph of the connecting line segments in the Z direction as the upper surface.
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| CN110674612B (en) * | 2019-09-25 | 2023-03-24 | 华东师范大学 | Modeling method for parasitic capacitance and resistance of integrated circuit process back-end interconnection |
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