CN102508974B - Integrated circuit analyzing method for changing interconnection delay parameters on basis of layout variation - Google Patents
Integrated circuit analyzing method for changing interconnection delay parameters on basis of layout variation Download PDFInfo
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Abstract
The invention discloses an integrated circuit analyzing method for changing interconnection delay parameters on basis of layout variation. The integrated circuit analyzing method includes steps of designing a same integrated circuit into a plurality of layout documents with different arrangements, extracting process documents of the integrated circuit according to manufacturing process documents of the integrated circuit, fittingly extracting a plurality of information documents of the layout documents with different arrangements, carrying out net extraction of parasitic parameters of an integrated layout and extraction of the interconnection delay parameters of the integrated circuit respectively, carrying out gate level circuit simulation of extracted parameters, testing performances, acquiring performance differences of the integrated circuit with different arrangements and analyzing affection on circuit performances from the layout variation. Affections on the circuit performances by different arrangements are confirmed by simulating the parasitic parameters of the circuit layout with different arrangements but with the identical schematic circuit diagram, and affection on the integrated circuit can be analyzed from the views of arrangement of the circuit layout and interconnection delay.
Description
Technical field
The invention belongs to the integrated circuit (IC) design field, relate to particularly a kind of integrated circuit analyzing method that changes interconnection delay parameters that changes based on domain.
Background technology
Along with the progress of SIC (semiconductor integrated circuit) technology and constantly dwindling of characteristic dimension, make that number of devices constantly increases on the single-wafer, the function of circuit is improved, and the design of circuit and layout become and become increasingly complex.By the part of Front-end Design, integrated circuit has been finished the design of RTL level, checking and comprehensive, realized the functional requirement of circuit, and rational placement-and-routing can help us to obtain postponing less, the better design proposal of performance in the design of rear end.So will substantially satisfy on the basis of function and characteristic index in circuit design, circuit characteristic constraint condition as requested (for example require the time delay of circuit can not be greater than a certain value), the position of components and parts or module in the Circuit tuning makes the overall performance of integrated circuit reach optimization in institute's claimed range.
Integrated circuit diagram is the middle bridge between Circuits System and the integrated circuit technology, is a requisite important step.Because advancing by leaps and bounds of microelectric technique, the characteristic dimension of integrated circuit is constantly reducing, and the frequency of operation of circuit is more and more higher, and device postpones also reducing, and interconnection resistance and electric capacity are increasing, and the delay of interconnection line begins to play a major role.In the design of high performance integrated circuit, metal interconnecting wires is distributed in multilayer and the quantity large scale is little, and the ghost effect of interconnection line is having a strong impact on the important performance characteristic such as reliability, time delay and power consumption of circuit.So the parasitic interconnection delay parameters of integrated circuit diagram is a key factor that affects circuit performance, the importance of integrated circuit diagram layout more and more highlights.
In the design flow of integrated circuit, be exactly to carry out parasitic parameter extraction and gate level circuit emulation after the layout design link, obtain the simulation result of circuit performance.So by the layout of Circuit tuning domain, change domain parasitic parameter, especially interconnection delay parameters, thereby the idea of improving circuit performance is achieved just.
The analytical approach of present integrated circuit all is to start with from the factor of the circuit such as the structure of circuit itself or component parameter value itself with analyzing, and realizes the optimization of circuit performance by various optimized algorithms.Although these methods are the most direct for the impact of circuit performance, but can not change the circuit parasitic parameter to the impact of circuit performance.Particularly for the nanoscale technology integrated circuit in generation, circuit parasitic parameter especially interconnection delay parameters produces more and more important impact over against the performance of circuit.Therefore from the integrated circuit diagram layout, change the circuit interconnection delay parameter, analyze the domain variation to the impact of integrated circuit, thereby the idea that realizes IC optimal design is very necessary.
The present invention has overcome can not change parasitic parameter to the defective of circuit performance impact in the prior art, proposed a kind of integrated circuit analyzing method that changes interconnection delay parameters that changes based on domain.The present invention changes the circuit interconnection delay parameter from the integrated circuit diagram layout change, analyzes the domain variation to the impact of integrated circuit, thereby improves the performance of integrated circuit, optimizes the method for integrated circuit.
Summary of the invention
The object of the invention is to propose a kind of integrated circuit analyzing method that changes interconnection delay parameters that changes based on domain.This method is from the integrated circuit diagram layout change, changes the circuit interconnection delay parameter, analyzes the domain variation to the impact of integrated circuit, thereby improves the performance of integrated circuit, optimizes the method for integrated circuit.
In order to achieve the above object, the present invention is to the same circuits schematic diagram is arranged but adopt the integrated circuit of multiple different laying out pattern to carry out respectively the extraction of domain parasitic parameter, by the integrated circuit die shape parameter that extracts circuit is carried out emulation, thereby check the difference of its performance and analyze the domain variation to the impact of circuit.
The present invention is based on domain and change the integrated circuit analyzing method that changes interconnection delay parameters, comprise the steps:
Step 1: the layout file that same integrated circuit is designed to respectively a plurality of different layouts;
Step 2: the process layer file that extracts integrated circuit according to the manufacturing process file of integrated circuit;
Step 3: utilize the process layer file that obtains in the step 2, cooperate the message file of the layout file of a plurality of different layouts that obtain in the extraction step one, carry out respectively the clean extraction of integrated circuit diagram parasitic parameter and the extraction of integrated circuit interconnection delay parameter;
Step 4: carry out respectively gate level circuit emulation according to the parameter that step 3 is extracted, test the performance of integrated circuit of the layout file of a plurality of different layouts, obtain the performance difference of integrated circuit of the domain of different layouts;
Step 5: according to the performance difference of the integrated circuit that obtains in the step 4, analyze the domain variation to the impact of integrated circuit.
Wherein, further comprise step 6: optimize laying out pattern, the optimized circuit performance.
Wherein, the quantity of the layout file of different layouts is two or more in the described step 1.
Wherein, described technical papers in the step 2 is extracted by software and transforms, obtain the process layer file.
Wherein, in the described step 3, utilize software, to layout file carry out the extraction of message file, clean extraction and the interconnection delay parameters of parasitic parameter extracts.
Wherein, described integrated circuit analyzing method is applicable to all types of integrated circuit.
Wherein, the domain parasitic parameter extraction of integrated circuit in the described integrated circuit analyzing method because importance and the singularity of interconnection delay parameters, was divided into for two steps with the extraction of the clean extraction of the domain parasitic parameter of integrated circuit and interconnection delay parameters and carries out.
The present invention proposes a kind of integrated circuit analyzing method that changes interconnection delay parameters that changes based on domain, its principle is that the domain parasitic parameter of different layouts is different, and different parasitic parameters can change the performance of integrated circuit, by extracting the same circuits schematic diagram but the circuit layout parasitic parameter of different layouts carries out respectively emulation, determine that different layout domains are on the impact of circuit performance, can be from the angle analysis integrated circuit of circuit layout layout and interconnect delay, can propose to optimize further the method for laying out pattern, the optimized circuit performance.
Description of drawings
Fig. 1 shows that the variation based on domain proposed by the invention changes the process flow diagram of the integrated circuit analyzing method of interconnection delay parameters.
Fig. 2 shows the domain of used three kinds of multi-form interconnection in the embodiment of the invention.Wherein, Fig. 2 A represents the electric capacity of parallel construction, and Fig. 2 B represents the electric capacity of decussate texture, and Fig. 2 C represents the pectination electric capacity of each metal level.
Embodiment
In conjunction with following specific embodiments and the drawings, the present invention is described in further detail, and protection content of the present invention is not limited to following examples.Under the spirit and scope that do not deviate from inventive concept, variation and advantage that those skilled in the art can expect all are included in the present invention, and take appending claims as protection domain.
Commonly used to multi-form interconnection comprise the parallel construction between parallel construction, second layer metal layer and the P injection region between parallel construction, first layer metal layer and the P injection region between parallel construction, first layer metal layer and the N trap between first layer metal layer and the polysilicon, the parallel construction of each metal interlevel, the coupled structure of polysilicon and metal interlevel, the collocation structure of metal interlevel, the decussate texture of metal interlevel.As shown in Figure 2, the layout file number of different layouts is two or more among the present invention, and present embodiment illustrates that take the domain that adopts three kinds of different interconnection forms as example the variation of laying out pattern is on the impact of circuit performance.Wherein, Fig. 2 A represents the electric capacity of parallel construction, and Fig. 2 B represents the electric capacity of decussate texture, and Fig. 2 C represents the pectination electric capacity of each metal level.
As shown in Figure 1, this specific implementation process is carried out according to following steps:
(1) with an integrated circuit that the same circuits schematic diagram is arranged, realize identical function, is designed to respectively have the domain form of three kinds of different layouts, as shown in Figure 2.Wherein that the IC Layout software application is the Virtuoso of Cadence.
(2) the integrated circuit fabrication process file of the standard that provides of integrated circuit manufacturer is the ict form, these technical paperss are extracted by Techgen (RCgen) software and change into the tf form, obtain at the needed process layer file of domain parasitic parameter extraction link (Techfile layer file).
(3) utilize three kinds of integrated circuit diagram files with different layouts by obtaining in the resulting process layer file of technical papers (Techfile layer file) the difference matching step (1) in the step (2), extract the message file (GDSII file) of layout file, again the GDSII file is imported in the 3D parasitic parameter extraction software Raphael software, utilize Raphael software to carry out the clean extraction of integrated circuit diagram parasitic parameter, thereby obtain the domain parasitic parameter of these three kinds of different layout integrated circuit diagrams.
Table one is depicted as three groups of stray capacitance parameters that adopt the domain of different interconnection forms using 3D parasitic parameter extraction software Raphael to extract in the present embodiment.
Use 3D parasitic parameter extraction software Raphael after the clean extraction of the domain parasitic parameter of finishing three kinds of different layout integrated circuit diagrams, respectively the integrated circuit diagram of these three kinds of different layouts is carried out again the extraction of interconnection delay parameters, thereby obtain the interconnect delay time parameter of the integrated circuit diagram of these three kinds of different layouts.
Three groups of delay time parameters that adopt the domain of different interconnection forms that table two extracts for present embodiment.
(4) the domain parasitic parameter that extracts according to step (3) carries out gate level circuit emulation to the integrated circuit diagram of these three kinds of different layouts respectively with interconnection delay parameters, emulation tool adopts the HSPICE software of Avanti company, and respectively test this moment three kinds of different layout domains performance of integrated circuits, thereby draw these three kinds of same circuits schematic diagrams but difference that the performance of the integrated circuit of different laying out pattern exists and can make performance of integrated circuits bring into play better laying out pattern form.
(5) according to the above-mentioned three kinds of same circuits schematic diagrams that obtain in the step (4) but the performance difference situation of the integrated circuit of different laying out pattern, summarize and analyze domain and change impact on integrated circuit.
(6) optimize laying out pattern, optimized circuit performance.
Claims (5)
1. the integrated circuit analyzing method based on domain variation change interconnection delay parameters is characterized in that, comprises the steps:
Step 1: the layout file that same integrated circuit is designed to respectively two or more different layouts;
Step 2: the process layer file that extracts integrated circuit according to the manufacturing process file of integrated circuit;
Step 3: utilize the process layer file that obtains in the step 2, cooperate the message file of the layout file of a plurality of different layouts that obtain in the extraction step one, carry out respectively the clean extraction of integrated circuit diagram parasitic parameter and the extraction of integrated circuit interconnection delay parameter;
Step 4: carry out respectively gate level circuit emulation according to the parameter that step 3 is extracted, test the performance of integrated circuit of the layout file of a plurality of different layouts, obtain the performance difference of integrated circuit of the domain of different layouts;
Step 5: according to the performance difference of the integrated circuit that obtains in the step 4, analyze the domain variation to the impact of integrated circuit;
Step 6: optimize laying out pattern, the optimized circuit performance.
2. a kind of integrated circuit analyzing method based on domain variation change interconnection delay parameters as claimed in claim 1 is characterized in that, the technical papers in the described step 2 is extracted and transforms by software, obtains the process layer file.
3. a kind of integrated circuit analyzing method based on domain variation change interconnection delay parameters as claimed in claim 1 is characterized in that, in the described step 3, behind the domain parasitic parameter extraction of integrated circuit, interconnection delay parameters is extracted again.
4. a kind of integrated circuit analyzing method that change to change interconnection delay parameters based on domain as claimed in claim 1, it is characterized in that, in the described step 3, utilize software to layout file carry out the extraction of message file, clean extraction and the interconnection delay parameters of parasitic parameter extracts.
5. a kind of integrated circuit analyzing method based on domain variation change interconnection delay parameters as claimed in claim 1 is characterized in that described integrated circuit analyzing method is applicable to all types of integrated circuit.
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| WO2023065309A1 (en) * | 2021-10-22 | 2023-04-27 | 华为技术有限公司 | Circuit design method and apparatus |
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