CN112149379A - Method and apparatus for simulating an integrated circuit and computer readable medium - Google Patents
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Abstract
Methods and apparatus, and computer-readable media, for simulating an integrated circuit are described herein. The method for simulating an integrated circuit described herein comprises: acquiring layout data indicating an integrated circuit; generating a graphical layout of the integrated circuit based on the layout data; dividing a graphical layout of an integrated circuit to determine a region to be simulated; and processing the region to be simulated by using a model corresponding to the layout pattern in the region to be simulated to generate a simulated microscopic image for the region to be simulated. By using the embodiments according to the present disclosure, a simulated microscopic image of a region to be simulated in an integrated circuit can be obtained, so that a designer can conveniently check the condition of a semiconductor device structure and judge whether the design is correct or not according to the condition.
Description
Technical Field
Embodiments of the present disclosure relate generally to the field of integrated circuit simulation, and more particularly, to methods and apparatus and computer-readable media for simulating integrated circuits.
Background
Technical Computer Aided Design (TCAD) has been widely used for simulation of integrated circuits as a tool for semiconductor process and device simulation. The designer can determine whether the designed semiconductor device structure has defects by looking at the simulation structure. For example, the TCAD tool may simulate the structural profile of a semiconductor device in an integrated circuit.
However, the standard operational flow of existing TCAD tools employs a default physical model, which is not friendly to actual device simulation because integrated circuit design fabrication may produce various structures, such as various conventional device structures and newly designed device structures. Furthermore, the existing TCAD tool can only simulate the virtual outline of the semiconductor device, and there is still a considerable difference between the virtual outline and the actual manufactured semiconductor structure, so that it is difficult for the user to find the defect existing in the designed semiconductor device in advance. It is desirable to provide improved schemes for simulating integrated circuits.
Disclosure of Invention
Embodiments of the present disclosure provide methods and apparatus and computer-readable media for simulating an integrated circuit.
In a first aspect, a method for simulating an integrated circuit is provided. The method comprises the following steps: acquiring layout data indicating an integrated circuit; generating a graphical layout of the integrated circuit based on the layout data; dividing a graphical layout of an integrated circuit to determine a region to be simulated; and generating a simulation microscopic image for the region to be simulated by processing the region to be simulated using a model corresponding to the layout pattern in the region to be simulated.
In some embodiments, generating the simulated microscopy image comprises: generating a contour pattern aiming at the region to be simulated based on the layout pattern; and generating a simulated microscopic image by processing the region to be simulated using a model corresponding to the outline pattern.
In some embodiments, generating the simulated microscope image by processing the region to be simulated using the model corresponding to the outline pattern comprises: searching the contour pattern in the simulation microscopic image library; and generating a microscopic image of the microscopic image model as a simulated microscopic image if the microscopic image model corresponding to the outline pattern is retrieved.
In some embodiments, generating the simulated microscope image by processing the region to be simulated using the model corresponding to the outline pattern further comprises: if no microscopic image model corresponding to the outline pattern is retrieved, the outline pattern is processed using a machine learning model to generate a simulated microscopic image.
In some embodiments, generating the simulated microscopy image for the region to be simulated comprises processing the layout pattern using a machine learning model to generate the simulated microscopy image.
In some embodiments, processing the layout pattern using the machine learning model to generate the simulated microscopy image comprises: generating a contour pattern based on the layout pattern; and processing the contour pattern using a machine learning model to generate a simulated microscopy image.
In some embodiments, the method further comprises: obtaining a plurality of sample layout patterns; acquiring a plurality of microscopic images respectively corresponding to the sample layout patterns; and training using the plurality of sample layout patterns and the plurality of microscopic images to generate a machine learning model.
In some embodiments, the method further comprises: generating a three-dimensional stacking structure aiming at the region to be simulated based on the region to be simulated; wherein generating the simulated microscopic image for the region to be simulated comprises: a simulated microscopic image for the side surface of the three-dimensional stacked structure is generated by processing the side surface using a model corresponding to the pattern of the side surface of the three-dimensional stacked structure.
In some embodiments, the method further comprises: acquiring user input, wherein the user input indicates a selected section line on the graphical layout; wherein determining the region to be simulated comprises determining the region to be simulated based on user input, the simulation region being used to generate a three-dimensional stacked structure.
In some embodiments, the simulated microscopy image comprises at least one of a simulated transmission electron microscopy image, a simulated scanning electron microscopy image, a simulated atomic force microscopy image, a simulated scanning tunneling microscopy image, a simulated scanning transmission electron microscopy image.
In some embodiments, generating a simulated microscopy image for the region to be simulated comprises: and generating a simulation microscopic image aiming at the region to be simulated based on the layout pattern in the region to be simulated and the process, material, structure and/or size related to the layout pattern.
In some embodiments, the method further comprises: acquiring spectral data aiming at a region to be simulated; comparing the spectrum data with reference spectrum data corresponding to the simulated microscopic image of the region to be simulated in the reference spectrum database to determine whether abnormal signals exist in the spectrum data; and if the abnormal signal is determined to exist in the comparison result, generating an abnormal indication signal indicating that an abnormal structure exists in the simulated microscopic image.
In some embodiments, acquiring spectral data for the region to be simulated includes acquiring at least one of energy dispersive X-ray spectral data, electron energy loss spectral data, electron backscatter diffraction spectral data, X-ray photoelectron spectral data, ultraviolet photoelectron spectral data, angle resolved photoelectron spectral data, focused ion beam spectral data for the region to be simulated.
In a second aspect, an electronic device is provided. The electronic device includes: a processing unit; a memory coupled to the processing unit and comprising a program stored thereon, which when executed by the processing unit causes the electronic device to perform the method according to any of the first aspects.
In a third aspect, a computer-readable storage medium is provided. The computer readable storage medium has stored thereon machine executable instructions which, when executed by at least one processor, cause the at least one processor to implement the above-described method.
According to the simulation method of the embodiment of the disclosure, a user can generate a visual simulation microscopic image from the layout design, so that whether the region to be simulated of the designed integrated circuit has defects or not can be conveniently checked. Cost and time are saved because there is no need to actually produce an integrated circuit and no need to microscopically inspect the produced integrated circuit.
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The above and other objects, features and advantages of the present disclosure will become more apparent by describing in greater detail exemplary embodiments thereof with reference to the attached drawings, in which like reference numerals generally represent like parts throughout.
FIG. 1 illustrates an exemplary diagram of an example environment in which various embodiments of the present disclosure can be implemented;
FIG. 2 illustrates a flow diagram of a process of simulating an integrated circuit, according to some embodiments of the present disclosure;
fig. 3 shows a schematic diagram of one example of generating a simulated microscopy image, according to some embodiments of the present disclosure;
FIG. 4 illustrates a schematic diagram of one example of generating simulated microscopic images for different processes, according to some embodiments of the present disclosure;
fig. 5 shows a schematic diagram of another example of generating a simulated microscopy image according to some embodiments of the present disclosure;
fig. 6 shows a schematic diagram of yet another example of generating a simulated microscopy image, according to some embodiments of the present disclosure;
FIG. 7 shows a schematic diagram of one example of different process stages and their corresponding spectra according to some embodiments of the present disclosure; and
FIG. 8 illustrates a block diagram of a computing device capable of implementing various embodiments of the present disclosure.
Detailed Description
Preferred embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. While the preferred embodiments of the present disclosure are illustrated in the accompanying drawings, it is to be understood that the present disclosure may be embodied in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The term "include" and its variants, as used herein, are intended to be inclusive in an open-ended manner, i.e., "including but not limited to. Unless specifically stated otherwise, the term "or" means "and/or". The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first," "second," and the like may refer to different or the same object. Other explicit and implicit definitions are also possible below.
As mentioned previously, in semiconductor production, the designed semiconductor device structure can be viewed through simulation. Conventional simulations typically use a default device model to simulate the outline of a designed semiconductor device. However, the default device models are typically of a limited variety. Integrated circuit designers design new semiconductor device structures for performance optimization or performance enhancement purposes during the design process. New semiconductor device structures are difficult to simulate with a default device model and often rely on Electronic Design Automation (EDA) vendors to update their device model libraries. This is not friendly to integrated circuit designers because it cannot handle more practical situations with user-defined models.
Furthermore, the simulation performed by integrated circuit design software provided by conventional EDA tool providers for semiconductor device structures typically only simulates the contours of the semiconductor device. The simulation results typically show the possible contour shapes of the designed semiconductor device structure after production fabrication in a two-dimensional or three-dimensional form. However, the contour shape does not reflect more information of the semiconductor device structure than the contour, but merely provides preliminary judgment information.
When more information is needed to determine whether a designed semiconductor device structure has physical defects, it is often necessary to take microscopic images, such as Scanning Electron Microscopy (SEM) and/or Transmission Electron Microscopy (TEM), of the actual semiconductor device structure being produced, in order to thereby further determine whether the actual physical structure of the designed semiconductor device is ideal. Conventional metrology schemes for the physical structure of semiconductor devices have limited functionality and require microscopy to support, due to the need to take microscopic images, such as SEM and TEM. In this regard, conventional simulation schemes are limited in functionality and inconvenient, and also result in additional detection costs.
In view of the above-mentioned shortcomings of the conventional solutions, there is a need for a solution that can also simulate microscopic images of semiconductor device structures so that designers can view the microscopic structures in a timely manner. By building a microscopic image model for the pattern of the region to be simulated of the designed semiconductor device, subsequently designed patterns can be processed using the microscopic image model to automatically generate corresponding microscopic images. In an embodiment of the present disclosure, the microscopic image model includes a microscopic image library model and a machine learning model.
In the microscopic image library model, a microscopic image library is created by providing a large number of microscopic images for various patterns. In this way, in the subsequent simulation process, the corresponding microscopic structure image can be searched in the microscopic image library aiming at the designed pattern.
In a machine learning model, training is performed by providing a large number of patterns and corresponding microscopic images to build the machine learning model. By using a large number of training samples for training to establish a machine learning model, when a designer designs a new semiconductor device structure, the machine learning model can also simulate a corresponding microscopic image according to the new semiconductor device structure. For example, Genetic Algorithm (GA) is a machine learning method that can be used to generate microscopic images. The genetic algorithm is designed and proposed according to the evolution rule of organisms in the nature. The algorithm converts the solving process of the problem into the processes of crossing, mutation and the like of chromosome genes in the similar biological evolution by a mathematical mode and by utilizing computer simulation operation. The genetic algorithm generally includes the following processes: generating an initial population; selecting a portion of the population to produce a new generation of the population; performing genetic manipulations, including crossover and mutation, etc., on the selected population; probabilistically weighing or punishing newly-produced populations; stopping according to the suspension condition.
According to an embodiment of the present disclosure, a solution for simulating an integrated circuit is provided. In this scheme, layout data including a plurality of semiconductor device structures is first received and a patterned layout is generated based on the layout data. The designer can arbitrarily divide the graphical layout to determine the region to be simulated. Then, a corresponding model may be determined based on the pattern in the determined region, and the region is simulated using the determined model to obtain a corresponding simulated microscopic image. The simulated microscopic image comprises at least one of a simulated transmission electron microscopic image, a simulated scanning electron microscopic image, a simulated atomic force microscopic image, a simulated scanning tunnel microscopic image and a simulated scanning transmission electron microscopic image.
By using the scheme of the disclosure, the corresponding simulated microscopic image can be obtained based on the designed layout pattern. In this way, a designer can specify a simulation area and obtain a corresponding microscopic image as needed, so that the condition of a designed semiconductor device structure can be checked at any time to find a design defect as early as possible. In addition, since the microscopic image can be displayed through simulation, the cost and time for manufacturing the semiconductor device are saved.
Embodiments of the present disclosure will be described below in detail with reference to the accompanying drawings. The computing device 102 in the example environment 100 may be any device with computing capabilities. By way of non-limiting example, the computing device 102 may be any type of fixed, mobile, or portable computing device, including but not limited to a desktop computer, laptop computer, notebook computer, netbook computer, tablet computer, multimedia computer, mobile phone, or the like; all or a portion of the components of the computing device 102 may be distributed in the cloud.
In this example environment 100, the computing device 102 includes a model module 122 that stores a model. The acts described below with respect to the computing device 102 may be specifically performed by a processor in the computing device 102.
The processor obtains layout data indicative of a layout representation 110 of the integrated circuit, for example, from a memory within the computing device 102 or an external device, and generates a graphical layout representation 110 of the integrated circuit based on the layout data. Although the layout is shown as a two-dimensional layout in fig. 1, it is to be understood that this is merely illustrative and not limiting of the scope of the present disclosure. In other embodiments, a graphical three-dimensional layout may also be generated based on the layout data.
The designer may divide the graphical layout of the integrated circuit by inputting instructions or using a pointing device such as a mouse to determine the area to be simulated. For example, the computing device 102 may display at least a portion of the generated layout illustration 110 on a display. The designer may display different portions of the layout representation 110 on the display by dragging a pointing device, such as a mouse. The designer may also select the area 112 to be simulated via an input device such as a mouse and/or a keyboard. In one embodiment, the region to be simulated 112 may be highlighted in a different color than the displayed layout part. Alternatively, the selected region to be simulated may be displayed enlarged as shown in fig. 1.
After selecting the region to be simulated, the processor may generate a simulated microscopic image 130 for the region to be simulated by processing the region to be simulated using a model corresponding to the layout pattern in the region to be simulated. In one embodiment, the processor may first retrieve a corresponding microscopic image model from a microscopic image database based on layout patterns in the region to be simulated. If a microscopic image model corresponding to the layout pattern exists in the database, a microscopic image of the microscopic image model is output as the simulated microscopic image 130. If there are no corresponding microscope images in the microscope image database, the processor uses the trained machine learning model to generate a corresponding microscope image based on the layout pattern 130.
In other embodiments, the processor of the computing device 120 may skip looking up the corresponding microscope image model from the microscope image library, and instead generate the corresponding microscope image directly using the machine learning model. By selecting the region of interest to be simulated as desired and generating corresponding microscopic images, the condition of the designed semiconductor device can be examined more comprehensively and possible defects can be discovered in advance. The microscopic image can more comprehensively and accurately show various possible situations of the semiconductor device than the conventional outline pattern.
FIG. 2 illustrates a flow diagram of a process 200 for simulating an integrated circuit, according to some embodiments of the present disclosure. In one embodiment, process 200 may be performed by computing device 120 of fig. 1. At 202, a processor of computing device 120 obtains layout data indicative of a layout of an integrated circuit. The layout data may be data in any data format for describing a circuit layout of the semiconductor integrated circuit. The processor may obtain the layout data from a memory of an external device or computing device 120.
At 204, the processor of the computing device 120 generates a patterned layout of the integrated circuit based on the layout data. In order to facilitate a designer to view the design layout of the integrated circuit, layout data can be generated into a graphical layout, so that the designer can visually view the design of any part of the layout. Further, the designer may use a pointing device or an input device such as a keyboard to drag, zoom in, zoom out, rotate the illustrated graphical layout on the display of the computing device 120, and may specify the region to be simulated by input. Alternatively, the displayed area may be defaulted to the area to be simulated. It is understood that the graphical layout includes a two-dimensional layout and a three-dimensional layout.
At 206, the processor of computing device 120 divides the patterned layout of the integrated circuit to determine the area to be simulated. It will be appreciated that layout data typically has a very large amount of data, and therefore the size of the graphical layout generated is also very large. Therefore, only a portion of the graphical layout is typically displayed on the display of the computing device 120 for clear viewing by the designer. The designer may select any area desired to be viewed by input and determine the area to be simulated.
In one embodiment, the computing device 120 may first display a two-dimensional layout pattern on its display. The user then selects the area to be simulated by drawing a cross-hatching on the layout pattern. The processor displays, based on the received input indicating the section line, a three-dimensional stack structure around the slope to which the section line corresponds. The three-dimensional stacked structure can be freely rotated and scaled by a user to better observe the three-dimensional structural condition of the semiconductor device.
At 208, the processor of the computing device 120 generates a simulated microscopic image for the area to be simulated by processing the area to be simulated using the model corresponding to the layout pattern in the area to be simulated. In one embodiment, the computing device 120 includes a memory that stores a database of microscopic images. The processor of the computing device 120 may retrieve from the memory a microscopic image model corresponding to the layout design pattern of the region to be simulated to obtain a simulated microscopic image. In one embodiment, the microscopic image model may be a simulated microscopic image. Alternatively, the microscopic image model may be a three-dimensional microscopic model including a simulated microscopic image.
In another embodiment, the memory of the computing device 120 stores a machine learning model that has been trained on a large amount of pattern data and corresponding microscopic images. EDA manufacturers may provide various design layout patterns for semiconductor devices. A true SEM or TEM image of the pattern for each layout design may be employed to form a corresponding microscopic image. Through training, the machine learning model can generate corresponding microscopic images aiming at the new layout patterns. Thus, designers can design new semiconductor device structures with greater design freedom without being constrained by device databases. Further, when the design is completed, the designer can also select an area desired to be simulated for simulation and review without actually performing production manufacturing of the semiconductor device and photographing of a microscopic image. This can greatly save the tape-out and photographing costs of the semiconductor device and eliminate defects that may exist in the design in advance.
Although the generation of simulated microscope images is described above with respect to layout design patterns, it is to be understood that this is merely illustrative and not a limitation on the scope of the present disclosure. In another embodiment, the processor of the computing device 120 generates a contour pattern for the region to be simulated based on the layout design pattern using conventional EDA software. It will be appreciated that layout design patterns are typically regular geometries, whereas EDA software simulated outline patterns typically include modifications and adjustments to the regular geometries for the actual process and related parameters, as shown, for example, in fig. 3. The outline pattern can be more closely fitted to the shape of the structure of a semiconductor device actually produced than a regular geometric pattern. The processor of the computing device 120 then generates a simulated microscope image by processing the region to be simulated using the model corresponding to the contour.
In one embodiment, the processor of the computing device 120 generates the simulated microscope image by looking up a microscope image model corresponding to the contour in a simulation image database. Specifically, if the processor of the computing device 120 finds a corresponding microscopic image model in the database, a microscopic image of the microscopic image model is used as the simulated microscopic image output. If the processor of the computing device 120 fails to find a corresponding microscopic image model, the machine learning model is used to generate the microscopic image model. The machine learning model is trained based on a previously prepared number of contour patterns and a corresponding number of microscopic images. In another embodiment, the processor of the computing device 120 directly generates the microscopic image model through a machine learning model.
Although multiple steps are shown in fig. 2 to generate the simulated microscopy image, it is to be understood that this is merely illustrative and not a limitation on the scope of the present disclosure. In other embodiments, the method for simulating an integrated circuit may include fewer or more steps, for example, one or more of the features described below may be applied to the flow 200 of FIG. 2.
Fig. 3 illustrates a schematic diagram of one example of generating a simulated microscopy image, according to some embodiments of the present disclosure. As described above, the processor of the computing device 120 first generates a patterned layout based on the received layout data and selects a region of interest from the layout as the region to be simulated 112. The area to be simulated 112 includes at least one pattern 114. Although a specific pattern shape is shown in fig. 3, this is merely an example and not a limitation on the scope of the present disclosure. In other embodiments, other patterns are possible.
The processor of the computing device 120 then generates a primary simulation area 116 including a contour pattern 117 based on the design pattern 114 using a conventional simulation scheme. The designer may initially determine whether a design defect exists by viewing the outline pattern 117 of the primary simulation area 116. If the design defect exists, the subsequent generation of the simulation microscopic image is not needed to be carried out, and the simulation microscopic image is returned to the layout design stage to be redesigned or modified. Thus, the time and the cost of the microscopic image simulation can be saved.
If the outline pattern 117 conforms to the design rules and there are no significant design defects, the processor of the computing device 120 may generate a simulated microscopy image 130 based on the outline pattern 117 of the primary simulation area 116. The processor of the computing device 120 may generate the simulated microscopy image 130 through a model lookup or machine learning model as described above. The designer then further determines the condition of the semiconductor device structure by looking at the simulated microscopic image 130 to determine whether the designed semiconductor device complies with the design rules and whether there are defects or undesirable conditions.
FIG. 4 illustrates a schematic diagram of one example of generating simulated microscopic images for different processes, according to some embodiments of the present disclosure. During the manufacturing process of integrated circuits, semiconductor materials such as silicon substrates require multiple processing steps to ultimately form integrated circuit chips. It will be appreciated that even the same layout design may have different contours and different microscopic images at different process stages. Furthermore, factors that affect the contours and the microscopic image include materials, structures, and/or dimensions in addition to the process.
As shown in FIG. 4, the same layout pattern 402 has a first profile 412 during the hard mask etch phase, a second profile 414 during the dielectric etch phase, and a third profile 416 during the Chemical Mechanical Polishing (CMP) Cu phase. The first profile 412, the second profile 414 and the third profile 416 may be derived by conventional EDA software simulation.
The processor of the computing device 120 may then generate corresponding first, second, and third simulated microscope images 422, 424, 426, respectively, based on the first, second, and third contours 412, 414, 416, by using the model as described above. In another embodiment, the contour simulation phase may also be skipped and the simulated microscope image generated directly based on the design pattern 402 and the process phase and/or corresponding process parameters.
In addition, it is understood that, in the training phase of the machine learning model, the layout design pattern and the corresponding microscopic image may also be trained to obtain the machine learning model by using different process phases and related process parameters.
The generation of simulated microscopic images for two-dimensional planar patterns is mainly described above. It is to be understood that the present disclosure is not so limited, but may be applied to the generation of simulated microscopic images of three-dimensional sections. Fig. 5 illustrates a schematic diagram of another example of generating a simulated microscopy image, according to some embodiments of the present disclosure. The pattern 502 is, for example, a pattern in a region to be simulated, and the cluster is, for example, a longitudinal cross-sectional pattern obtained by longitudinally cutting a semiconductor device structure of interest along a certain cross-sectional line from a two-dimensional planar pattern. The processor of computing device 120 generates an outline pattern 504 based on the profile layout design pattern 502. Thereafter, the processor of the computing device 120 uses the above-described models (including model-finding models and/or machine-learning models) to generate a simulated microscopic image 506 based on the outline pattern 504. The simulated microscope image 506 may be, for example, a real TEM image for the contour pattern pre-stored in a library of simulated microscope images or a simulated microscope image generated by machine learning.
Fig. 6 illustrates a schematic diagram of yet another example of generating a simulated microscopy image, according to some embodiments of the present disclosure. In this embodiment, the processor of the computing device 120 first generates a patterned layout pattern 602 based on the received layout data. The layout pattern 602 is a layout pattern of a two-dimensional plane. The designer selects the area of interest by moving a mouse or using an input device such as a keyboard. For example, the designer may draw the cross-hatching A-A' on layout illustration 604. The longitudinal section corresponding to the section line A-A' is selected as the region to be simulated.
The processor of computing device 120 then generates a three-dimensional stereographic structure 606 proximate to the cross-section corresponding to section line A-A'. The designer can rotate, drag, or zoom the three-dimensional solid schematic structure 606 through an input tool such as a mouse to see from different angles whether the structure near the region to be simulated has a condition violating the design rules or a design defect. After this, the processor of the computing device 120 may generate a corresponding simulated microscope image 608 based on the cross-sectional pattern using the model described above.
Fig. 7 shows a schematic diagram of one example of different process stages and their corresponding spectra according to some embodiments of the present disclosure. As a complementary solution for simulating an integrated circuit, an embodiment of the present disclosure also proposes to use spectrogram analysis to analyze whether a semiconductor device has a design problem. In one embodiment, the memory of the computing device 102 may store a plurality of maps for a plurality of actual semiconductor structures. The characteristic spectrum for a particular semiconductor device structure may be analyzed using one or more of energy dispersive X-ray (EDX) spectroscopy detection, Electron Energy Loss Spectroscopy (EELS) detection, electron backscatter diffraction spectroscopy (EBSD) detection, X-ray photoelectron spectroscopy (XPS) detection, Ultraviolet Photoelectron Spectroscopy (UPS) detection, angle resolved photoelectron spectroscopy (ARP) detection, focused ion beam spectroscopy (FIB) detection.
For example, fig. 7 shows a spectral graph 702, 704, 706, and 708 for particular regions of semiconductor device structures 701, 703, 705, and 707. It can be seen that the individual spectra are different for different semiconductor device structures, and thus it is possible to determine whether the semiconductor device structure is correct by analyzing the spectra. By pre-storing a library of spectra for correctly designed semiconductor devices in the memory of the computing device 120, it may be determined whether the designed semiconductor device structure is correct when the integrated circuit is subsequently designed by determining a spectral graph of the semiconductor device structure of the designed integrated circuit and comparing it to a corresponding spectral graph in the library of spectra.
For example, fig. 7 also shows a simulated microscope image corresponding to the region to be simulated. The processor of the computing device 120 acquires spectral data for the region to be simulated and generates a corresponding spectral map. This spectral data can be detected, for example, by the above-described detection of an integrated circuit actually produced. Alternatively, it may be generated based on simulated microscopic images by using a machine learning model.
The processor of the computing device 120 then compares the spectral data with reference spectral data in a reference spectral database corresponding to the simulated microscopic image of the region to be simulated to determine whether an abnormal signal is present in the spectral data. And if the abnormal signal exists in the comparison result, generating an abnormal indicating signal indicating that the abnormal structure exists in the simulation microscopic image. For example, spectrogram representation 710 in FIG. 7 has one more outlier spectral line 712 than reference spectrogram representation 708. Thereby determining that the region to be simulated may have defects. The defect may be caused, for example, by an additional anomalous film. Design defects can be found in advance through spectral line analysis.
Fig. 8 illustrates a schematic block diagram of an example device 800 that may be used to implement embodiments of the present disclosure. Device 800 may be used to implement computing device 102 of fig. 1. As shown, the device 800 includes a Central Processing Unit (CPU)801 that may perform various suitable actions and processes in accordance with computer program instructions stored in a Read Only Memory (ROM)802 or loaded from a storage unit 808 into a Random Access Memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the device 800 can also be stored. The CPU 801, ROM 802, and RAM 803 are connected to each other via a bus 804. An input/output (I/O) interface 805 is also connected to bus 804.
A number of components in the device 800 are connected to the I/O interface 805, including: an input unit 806, such as a keyboard, a mouse, or the like; an output unit 807 such as various types of displays, speakers, and the like; a storage unit 808, such as a magnetic disk, optical disk, or the like; and a communication unit 809 such as a network card, modem, wireless communication transceiver, etc. The communication unit 809 allows the device 800 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.
The processing unit 801 performs the various methods and processes described above, such as the process 200. For example, in some embodiments, process 200 may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as storage unit 808. The process 200 may be formed separately as a separate simulation program or as a plug-in to a conventional TCAD. In some embodiments, part or all of the computer program can be loaded and/or installed onto device 800 via ROM 802 and/or communications unit 809. When loaded into RAM 803 and executed by CPU 801, a computer program may perform one or more of the steps of process 200 described above. Alternatively, in other embodiments, CPU 801 may be configured to perform process 200 by any other suitable means (e.g., by way of firmware).
The functions described herein above may be performed, at least in part, by one or more hardware logic components. For example, without limitation, exemplary types of hardware logic components that may be used include: a Field Programmable Gate Array (FPGA), an Application Specific Integrated Circuit (ASIC), an Application Specific Standard Product (ASSP), a system on a chip (SOC), a load programmable logic device (CPLD), and the like.
Program code for implementing the methods of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the program codes, when executed by the processor or controller, cause the functions/acts specified in the flowchart and/or block diagram to be performed. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package partly on the machine and partly on a remote machine or entirely on the remote machine or server.
In the context of this disclosure, a machine-readable medium may be a tangible medium that can contain, or store a program for use by or in connection with an instruction execution system, apparatus, or device. The machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. More specific examples of a machine-readable storage medium may include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.
Further, while operations are depicted in a particular order, this should be understood as requiring that such operations be performed in the particular order shown or in sequential order, or that all illustrated operations be performed, to achieve desirable results. Under certain circumstances, multitasking and parallel processing may be advantageous. Likewise, while several specific implementation details are included in the above discussion, these should not be construed as limitations on the scope of the disclosure. Certain features that are described in the context of separate embodiments can also be implemented in combination in a single implementation. Conversely, various features that are described in the context of a single implementation can also be implemented in multiple implementations separately or in any suitable subcombination.
Although the subject matter has been described in language specific to structural features and/or methodological acts, it is to be understood that the subject matter defined in the appended claims is not necessarily limited to the specific features or acts described above. Rather, the specific features and acts described above are disclosed as example forms of implementing the claims.
Claims (15)
1. A method for simulating an integrated circuit, comprising:
acquiring layout data indicating an integrated circuit;
generating a graphical layout of the integrated circuit based on the layout data;
dividing the graphical layout of the integrated circuit to determine a region to be simulated; and
and processing the region to be simulated by using a model corresponding to the layout pattern in the region to be simulated so as to generate a simulated microscopic image aiming at the region to be simulated.
2. The method of claim 1, wherein generating the simulated microscopy image comprises:
generating a contour pattern for the region to be simulated based on the layout pattern; and
and processing the area to be simulated by using a model corresponding to the outline pattern to generate the simulated microscopic image.
3. The method of claim 2, wherein generating the simulated microscopy image by processing the area to be simulated using a model corresponding to the outline pattern comprises:
retrieving the contour pattern in a simulation microscopic image library; and
and if a microscopic image model corresponding to the outline pattern is retrieved, generating a microscopic image of the microscopic image model into the simulated microscopic image.
4. The method of claim 3, wherein generating the simulated microscopy image by processing the area to be simulated using a model corresponding to the outline pattern further comprises:
processing the contour pattern using a machine learning model to generate the simulated microscope image if a microscope image model corresponding to the contour pattern is not retrieved.
5. The method of claim 1, wherein generating a simulated microscopy image for the region to be simulated comprises processing the layout pattern using a machine learning model to generate the simulated microscopy image.
6. The method of claim 5, wherein processing the layout pattern using a machine learning model to generate the simulated microscopy image comprises:
generating a contour pattern based on the layout pattern; and
processing the contour pattern using the machine learning model to generate the simulated microscopy image.
7. The method of claim 5, further comprising:
obtaining a plurality of sample layout patterns;
obtaining a plurality of microscopic images respectively corresponding to the plurality of sample layout patterns; and
training using the plurality of sample layout patterns and the plurality of microscopic images to generate the machine learning model.
8. The method of claim 1, further comprising:
generating a three-dimensional stacking structure aiming at the area to be simulated based on the area to be simulated;
wherein generating a simulated microscopic image for the region to be simulated comprises: processing a side surface of the three-dimensional stacked structure by using a model corresponding to a pattern of the side surface to generate a simulated microscopic image for the side surface of the three-dimensional stacked structure.
9. The method of claim 8, further comprising:
obtaining a user input indicating a selected section line on the graphical layout;
wherein determining the area to be simulated comprises determining the area to be simulated based on the user input, the simulation area being used to generate the three-dimensional stacked structure.
10. The method of claim 1, wherein the simulated microscopy images comprise at least one of simulated transmission electron microscopy images, simulated scanning electron microscopy images, simulated atomic force microscopy images, simulated scanning tunneling microscopy images, simulated scanning transmission electron microscopy images.
11. The method of claim 1, wherein generating a simulated microscopy image for the region to be simulated comprises:
and generating a simulation microscopic image aiming at the region to be simulated based on the layout pattern in the region to be simulated and the process, material, structure and/or size related to the layout pattern.
12. The method of claim 1, further comprising:
acquiring spectral data aiming at the region to be simulated;
comparing the spectral data with reference spectral data corresponding to the simulated microscopic image of the region to be simulated in a reference spectral database to determine whether abnormal signals exist in the spectral data; and
and if the abnormal signal exists in the comparison result, generating an abnormal indicating signal indicating that an abnormal structure exists in the simulated microscopic image.
13. The method of claim 12, wherein acquiring spectral data for the region to be simulated comprises acquiring at least one of energy dispersive X-ray spectral data, electron energy loss spectral data, electron backscatter diffraction spectral data, X-ray photoelectron spectral data, ultraviolet photoelectron spectral data, angle resolved photoelectron spectral data, focused ion beam spectral data for the region to be simulated.
14. An electronic device, comprising:
a processing unit;
a memory coupled to the processing unit and including a program stored thereon, which when executed by the processing unit, causes the electronic device to perform the method of any of claims 1-13.
15. A computer-readable storage medium having stored thereon machine-executable instructions that, when executed by at least one processor, cause the at least one processor to implement the method of any one of claims 1 to 13.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112861464A (en) * | 2021-03-16 | 2021-05-28 | 上海壁仞智能科技有限公司 | Design method of integrated circuit chip and integrated circuit chip |
| CN113065307A (en) * | 2021-03-22 | 2021-07-02 | 浙江大学 | Power semiconductor module substrate optimization design method |
| CN113919259A (en) * | 2021-12-13 | 2022-01-11 | 深圳市华杰智通科技有限公司 | Integrated circuit layout design system and method |
| CN115062571A (en) * | 2022-05-06 | 2022-09-16 | 上海概伦电子股份有限公司 | Dynamic selection method, system, equipment and computer readable storage medium for data area of integrated circuit device |
| WO2022213515A1 (en) * | 2021-04-07 | 2022-10-13 | 长鑫存储技术有限公司 | Method and device for simulating circuit |
| CN117034847A (en) * | 2023-10-09 | 2023-11-10 | 深圳市锐骏半导体股份有限公司 | Simulation method, device, equipment and medium of power device terminal |
| US12045554B2 (en) | 2021-04-07 | 2024-07-23 | Changxin Memory Technologies, Inc. | Circuit simulation method and device |
Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080147373A1 (en) * | 2006-12-14 | 2008-06-19 | Thomas Roessler | Method for analyzing the design of an integrated circuit |
| CN103559329A (en) * | 2013-09-27 | 2014-02-05 | 华中科技大学 | Method for measuring rough nano structure feature parameters in optical scattering measurement |
| CN104123428A (en) * | 2014-08-14 | 2014-10-29 | 中国科学院微电子研究所 | CMP process simulation method and system |
| CN104915528A (en) * | 2015-07-15 | 2015-09-16 | 中国科学院微电子研究所 | Layout design method, layout design system and manufacturing method of integrated circuit |
| CN106252250A (en) * | 2016-08-18 | 2016-12-21 | 东方晶源微电子科技（北京）有限公司 | Image outline generates method and device |
| CN106815380A (en) * | 2015-11-27 | 2017-06-09 | 中国科学院微电子研究所 | Method and system for extracting parasitic resistance |
| CN106846463A (en) * | 2017-01-13 | 2017-06-13 | 清华大学 | Micro-image three-dimensional rebuilding method and system based on deep learning neutral net |
| CN108257166A (en) * | 2018-01-11 | 2018-07-06 | 上海华虹宏力半导体制造有限公司 | The emulating image of domain and the method for silicon chip SEM image Auto-matching |
| CN111353211A (en) * | 2018-12-21 | 2020-06-30 | 达索系统公司 | Multi-instantiation simulation for large environments |
| CN111445502A (en) * | 2020-03-06 | 2020-07-24 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Integrated circuit image matching method and system |
-
2020
- 2020-08-14 CN CN202010821020.0A patent/CN112149379A/en active Pending
Patent Citations (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20080147373A1 (en) * | 2006-12-14 | 2008-06-19 | Thomas Roessler | Method for analyzing the design of an integrated circuit |
| CN103559329A (en) * | 2013-09-27 | 2014-02-05 | 华中科技大学 | Method for measuring rough nano structure feature parameters in optical scattering measurement |
| CN104123428A (en) * | 2014-08-14 | 2014-10-29 | 中国科学院微电子研究所 | CMP process simulation method and system |
| CN104915528A (en) * | 2015-07-15 | 2015-09-16 | 中国科学院微电子研究所 | Layout design method, layout design system and manufacturing method of integrated circuit |
| CN106815380A (en) * | 2015-11-27 | 2017-06-09 | 中国科学院微电子研究所 | Method and system for extracting parasitic resistance |
| CN106252250A (en) * | 2016-08-18 | 2016-12-21 | 东方晶源微电子科技（北京）有限公司 | Image outline generates method and device |
| CN106846463A (en) * | 2017-01-13 | 2017-06-13 | 清华大学 | Micro-image three-dimensional rebuilding method and system based on deep learning neutral net |
| CN108257166A (en) * | 2018-01-11 | 2018-07-06 | 上海华虹宏力半导体制造有限公司 | The emulating image of domain and the method for silicon chip SEM image Auto-matching |
| CN111353211A (en) * | 2018-12-21 | 2020-06-30 | 达索系统公司 | Multi-instantiation simulation for large environments |
| CN111445502A (en) * | 2020-03-06 | 2020-07-24 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | Integrated circuit image matching method and system |
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112861464A (en) * | 2021-03-16 | 2021-05-28 | 上海壁仞智能科技有限公司 | Design method of integrated circuit chip and integrated circuit chip |
| CN112861464B (en) * | 2021-03-16 | 2022-08-16 | 上海壁仞智能科技有限公司 | Design method of integrated circuit chip and integrated circuit chip |
| CN113065307A (en) * | 2021-03-22 | 2021-07-02 | 浙江大学 | Power semiconductor module substrate optimization design method |
| CN113065307B (en) * | 2021-03-22 | 2022-05-17 | 浙江大学 | Power semiconductor module substrate optimization design method |
| WO2022213515A1 (en) * | 2021-04-07 | 2022-10-13 | 长鑫存储技术有限公司 | Method and device for simulating circuit |
| US12045554B2 (en) | 2021-04-07 | 2024-07-23 | Changxin Memory Technologies, Inc. | Circuit simulation method and device |
| CN113919259A (en) * | 2021-12-13 | 2022-01-11 | 深圳市华杰智通科技有限公司 | Integrated circuit layout design system and method |
| CN115062571A (en) * | 2022-05-06 | 2022-09-16 | 上海概伦电子股份有限公司 | Dynamic selection method, system, equipment and computer readable storage medium for data area of integrated circuit device |
| WO2023213094A1 (en) * | 2022-05-06 | 2023-11-09 | 上海概伦电子股份有限公司 | Dynamic data area selection method, system and device applied to integrated circuit device, and computer-readable storage medium |
| CN117034847A (en) * | 2023-10-09 | 2023-11-10 | 深圳市锐骏半导体股份有限公司 | Simulation method, device, equipment and medium of power device terminal |
| CN117034847B (en) * | 2023-10-09 | 2024-02-20 | 深圳市锐骏半导体股份有限公司 | Simulation method, device, equipment and medium of power device terminal |
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