CN113065307A - Power semiconductor module substrate optimization design method - Google Patents

Power semiconductor module substrate optimization design method Download PDF

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CN113065307A
CN113065307A CN202110301447.2A CN202110301447A CN113065307A CN 113065307 A CN113065307 A CN 113065307A CN 202110301447 A CN202110301447 A CN 202110301447A CN 113065307 A CN113065307 A CN 113065307A
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周宇
陈宇
李成敏
罗皓泽
李武华
何湘宁
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Abstract

The invention discloses a power semiconductor module substrate optimization design method, which comprises the following steps: s1, taking chip parameters and design rules required by substrate design as design input; s2, reading a substrate paradigm library; s3, forming a genetic sequence by the paradigm number, the loop number, the chip spacing and the wiring width to generate an initial population; s4, generating a substrate layout; s5, calculating the layout area and the current changing inductance; s6, generating a child population by taking the minimum layout area and the minimum commutation inductance as a target; and S7, jumping to S3 to iterate until the maximum iteration number K, and acquiring a pareto frontier solution as a result to be output. The method is mainly characterized in that a substrate layout is generated by using a genetic sequence composed of concise variables based on a layout normal form library, and then a layout scheme with the lowest area and commutation inductance is calculated based on a genetic algorithm. Compared with the existing optimization method using position coding, the method can avoid the check of design rules, narrow the search range and realize the compact and low-sense optimization of the power module layout.

Description

Power semiconductor module substrate optimization design method
Technical Field
The invention belongs to the field of power semiconductor module substrate optimization design, and particularly relates to a power semiconductor module substrate optimization design method.
Background
Due to the limited current capacity of a single power semiconductor chip (generally less than 200A), in high-power converter applications such as new energy power generation and traction drive, a plurality of chips are generally packaged in a power module for use. Due to the high-speed switch operation of the power chip, the parasitic inductance effect of the substrate circuit poses a serious challenge to the safe and stable operation of the power module, which is mainly reflected in that: on one hand, di/dt in the chip turn-off process can excite an induction voltage on a line inductor to cause chip overvoltage, thereby threatening the operation safety. On the other hand, the parasitic inductance may generate voltage/current oscillation with the junction capacitance of the device, increasing device loss, and affecting electromagnetic compatibility performance. Therefore, it is important to optimize the low inductance of the module substrate circuit while ensuring a compact design, and to improve the performance and safety of the power module.
Because the power module has a complex structure, a complex process and difficult testing, the time and the labor are usually consumed by depending on manual design iteration, and the optimal design is difficult to realize. The numerical optimization method represented by the genetic algorithm can search an optimal design solution set through searching and evaluating design variables, and has the advantages that artificial empirical design cannot be compared with. However, the numerical optimization design of the existing power module has the following characteristics: firstly, in the aspect of parasitic inductance optimization, partial methods only pay attention to the local characteristics of the size parameters of the bonding wire and the metal layer, and the substrate circuit is not optimized integrally, so that the optimization effect is limited; secondly, the existing substrate overall optimization method uses position variables to encode the design, so that not only is the design rule check required when the substrate layout is generated, but also the search range is large, the iteration times are multiple, and the efficiency of the optimization design is limited.
In view of the above, the invention uses the paradigm number, the number of loops, and the parallel connection mode to form the DNA code and generate the substrate layout based on the advantages of the genetic algorithm and based on the basic layout paradigm library, calculates the design scheme set with the minimum layout area and the minimum commutation inductance, can shorten the code length and the search range, and realizes the compact low-inductance optimization of the power module layout.
Disclosure of Invention
The invention aims to overcome the defects of the prior art and provides a power semiconductor module substrate optimization design method. The technical scheme of the invention is as follows:
the invention provides a power semiconductor module substrate optimization design method based on a genetic algorithm, which comprises the following steps:
s1, taking the number of parallel chips, the chip size, the minimum chip spacing and the minimum wiring width parameters required by the power semiconductor module substrate design as design input;
s2, reading a substrate paradigm library to obtain paradigm quantity;
s3, generating an initial population: forming a genetic sequence by taking the paradigm number, the loop number, the chip spacing and the wiring width as optimization variables, and randomly generating M groups of sequences as initial populations by taking the paradigm number in S2, the parallel chip number in S1, the minimum chip spacing and the minimum wiring width as limit values of the variables;
s4, generating a layout: aiming at each group of sequences in the population, firstly selecting a basic layout from a normal form library according to normal form numbers, then determining the size of the basic layout according to the number of chips and design rules, and then translating or mirroring the basic layout according to a parallel connection mode and the number of loops to generate an individual substrate layout;
s5, fitness evaluation: calculating the layout area and the current conversion inductance;
s6, genetic calculation: with the minimum layout area and the minimum commutation inductance as the target, screening parents through non-dominant sorting, and generating offspring populations through crossing and variation;
s7, iterative output: and skipping to S4 for iteration until the maximum iteration number K is reached, and acquiring a pareto front solution set as a result to be output.
Further, the library of substrate paradigms in step S2 has the following features: the substrate paradigm is composed of a first metal layer, a second metal layer, a third metal layer, a first chip set, a second chip set, a positive electrode, a negative electrode and an alternating current output port, wherein the first chip set and the positive electrode port are arranged on the first metal layer; the second chip set is arranged on the second metal layer; the negative electrode port is arranged on the third metal layer; the positive port is positioned in a first direction of the negative port, the alternating current port is positioned in a second direction of the positive port and the negative port, and the first direction is vertical to the second direction; the paradigm library includes at least the following paradigms:
paradigm 1: the first chip group is positioned in the first direction of the second chip group, and the chips belonging to the first chip group and the chips belonging to the second chip group are arranged along the second direction; a fourth metal layer is arranged in the first direction of the first chip set, and the alternating current output port is arranged on the fourth metal layer;
paradigm 2: the first chip group is positioned in the first direction of the second chip group, and the chips belonging to the first chip group and the chips belonging to the second chip group are arranged along the first direction; the alternating current output port is arranged on the second metal layer and is positioned in the first direction of the first chip set;
paradigm 3: the first chip group is positioned in a second direction of the second chip group, and the chips belonging to the first chip group and the chips belonging to the second chip group are arranged along the second direction; the alternating current output port is arranged on the second metal layer and is positioned in the first direction of the first chip set;
paradigm 4: the first chip group is positioned in the second direction of the second chip group, and the chips belonging to the first chip group and the chips belonging to the second chip group are arranged along the first direction; the alternating current output port is arranged on the second metal layer and is located in the first direction of the first chip set.
Further, the genetic sequence in step S3 is composed of multi-bit binary codes, where two bits of codes represent a canonical number, another two bits of codes represent the number of loops, another one bit of codes represents a parallel connection mode, another six bits of codes represent chip spacing, and another six bits of codes represent wiring width.
Further, the specific steps of generating the layout in step S4 are:
s41, selecting a basic layout from the paradigm library according to the paradigm number input by the sequence;
s42, inputting the number P of parallel chips according to the sequencetotalAnd the number of loops NloopCalculating the number of parallel chips P in the basic layoutloop＝Ptotal/Nloop；
S43, arranging the chips of the first chip group and the chips of the second chip group along the chip group arrangement direction specified by the basic layout according to the chip spacing input in sequence;
s44, determining the sizes of the metal layer and the bonding wire according to the wiring width and the design rule input in the sequence;
s45, parallel connection mode and loop number N input according to sequenceloopCarrying out parallel expansion on a basic layout, wherein the parallel expansion is divided into two conditions of translation and mirror image;
and finally outputting the expanded layout as a result.
Further, the step S44 is specifically: the size of the metal layer around the chip and the port is determined by the allowed welting distance; the size of the metal layer in the bonding wire area is determined by the width of the bonding area; the distance between adjacent metal layers is determined by the minimum insulation distance; the arc height of the bonding wire is determined by the bonding process; the width of the metal layer in the remaining region is determined by the width of the input wiring.
Further, in step S45, the translation is expanded to shift the basic layout by NloopThen, generate NloopA basic layout, making the layout space the same as the space of the metal layer in the layout;
the mirror image is expanded to carry out mirror image processing on the basic layout firstly, combine the new layout and then translate the new layout by NloopAnd 2 times, making the layout pitch the same as the pitch of the metal layer in the layout.
Further, the specific step of calculating the commutation inductance in step S5 is: firstly, a patterned metal layer and a bonding wire are dispersed into an equivalent circuit consisting of an RL network, a negative terminal of a module is used as a reference node, and a positive terminal is providedSub-injection of AC excitation IDC+Solving the voltage response V of the positive terminalDC+The commutation inductance is calculated by the following formula:
Figure BDA0002986437070000041
where f is the frequency of the excitation current.
Further, the output of the result in the step S7 is specifically: acquiring a parent population when iteration is finished, performing non-dominance ordering on the parent population, and acquiring a genetic sequence of a pareto front solution set; wherein, the paradigm number, the number of loops, the chip pitch and the wiring width described in the sequence, and the substrate layout generated in step S4 are used to optimize the design result of the substrate obtained by the genetic algorithm.
In summary, the present invention optimally designs the substrate of the power module by using genetic algorithm with the minimum substrate layout area and commutation inductance as the optimization target by using the DNA code composed of layout paradigm, number of loops, and parallel connection.
Based on the technical method, the invention has the following beneficial technical effects:
(1) the invention uses layout normal form, loop quantity and parallel connection mode to form DNA code, and generates substrate layout according to basic normal form, thus avoiding design rule check, reducing search range of optimization and realizing high-efficiency optimization design.
(2) The invention takes the minimum of the substrate layout area and the current conversion inductance as optimization targets, and uses the genetic algorithm to carry out optimization design on the substrate of the power module, thereby realizing the compact low-inductance optimization of the layout of the power module.
Drawings
FIG. 1 is a diagram of a layout paradigm in an exemplary paradigm library;
FIG. 2 is a genetic code map used in the examples;
FIG. 3 is a diagram of two expansion ways of the basic layout;
FIG. 4 is an implementation flow chart;
FIG. 5 is a graph of the results of the previous iteration and the pareto frontier results for an embodiment;
FIG. 6 is a graph of a design parameter distribution of the leading edge results of the example;
FIG. 7 is a plot of the leading edge results of example No. 7;
fig. 8 is a conventional module substrate layout.
Detailed Description
In order to explain the present invention in more detail, the present invention will be further explained in detail with reference to the drawings and examples.
The invention provides a power semiconductor module substrate optimization design method, which comprises the following specific steps:
s1, design input: inputting the number of parallel chips, the size of the chips, the minimum chip spacing and the minimum wiring width;
s2, reading a paradigm library: reading a substrate paradigm library to obtain the paradigm quantity;
s3, generating an initial population: forming genetic sequences by the paradigm numbers, the loop number, the chip spacing and the wiring width, and randomly generating M groups of sequences as initial populations by taking the paradigm number in S2, the parallel chip number in S1, the minimum chip spacing and the minimum wiring width as limit values;
s4, generating a layout: aiming at each individual sequence in the population, firstly, a basic layout is selected from a normal form library according to normal form numbers, then the size of the basic layout is determined according to the number of chips and design rules, and then the basic layout is translated or mirrored according to the parallel connection mode and the number of loops to generate the substrate layout of the individual.
S5, fitness evaluation: calculating the layout area and the current conversion inductance;
s6, genetic calculation: with the minimum layout area and the minimum commutation inductance as the target, screening parents through non-dominant sorting, and generating offspring populations through crossing and variation;
s7, iterative output: and skipping to S4 for iteration until the maximum iteration number K is reached, and acquiring a pareto front solution set as a result to be output.
The steps of the present invention are further described below with reference to specific examples.
In an embodiment of the present invention, the input parameters of the embodiment in step S1 are shown in table 1.
Table 1 example input parameters
Figure BDA0002986437070000051
Figure BDA0002986437070000061
The library of substrate paradigms in step S2 has the following features: the substrate paradigm is composed of a first metal layer, a second metal layer, a third metal layer, a first chip set, a second chip set, a positive electrode, a negative electrode and an alternating current output port, wherein the first chip set and the positive electrode port are arranged on the first metal layer; the second chip set is arranged on the second metal layer; the negative electrode port is arranged on the third metal layer; the positive port is located in a first direction of the negative port, the alternating current port is located in a second direction of the positive port and the negative port, and the first direction is perpendicular to the second direction. As shown in fig. 1, the paradigm library of an embodiment comprises the following paradigms:
paradigm 1: the first chip group is positioned in the first direction of the second chip group, and the chips belonging to the first chip group and the chips belonging to the second chip group are arranged along the second direction; a fourth metal layer is arranged in the first direction of the first chip set, and the alternating current output port is arranged on the fourth metal layer;
paradigm 2: the first chip group is positioned in the first direction of the second chip group, and the chips belonging to the first chip group and the chips belonging to the second chip group are arranged along the first direction; the alternating current output port is arranged on the second metal layer and is positioned in the first direction of the first chip set;
paradigm 3: the first chip group is positioned in a second direction of the second chip group, and the chips belonging to the first chip group and the chips belonging to the second chip group are arranged along the second direction; the alternating current output port is arranged on the second metal layer and is positioned in the first direction of the first chip set;
paradigm 4: the first chip group is positioned in the second direction of the second chip group, and the chips belonging to the first chip group and the chips belonging to the second chip group are arranged along the first direction; the alternating current output port is arranged on the second metal layer and is located in the first direction of the first chip set.
The genetic sequence in step S3 uses binary coding, wherein two bits of the binary coding represent a paradigm number, the other two bits of the binary coding represent the number of loops, the other one bit of the binary coding represents a parallel connection mode, the other six bits of the binary coding represent chip spacing, and the other six bits of the binary coding represent wiring width. FIG. 2 shows the coding pattern of the genetic sequences in the examples.
The specific steps of the layout generation in step S4 are:
s41, selecting a basic layout from the paradigm library according to the paradigm number input by the sequence;
s42, inputting the number P of parallel chips according to the sequencetotalAnd the number of loops NloopCalculating the number of parallel chips P in the basic layoutloop＝Ptotal/Nloop；
S43, arranging the chips of the first chip group and the chips of the second chip group along the chip group arranging direction defined by the basic layout according to the chip spacing input in sequence;
s44, determining the sizes of the metal layer and the bonding wire according to the wiring width and the design rule input in the sequence: the size of the metal layer around the chip and the port is determined by the allowed welting distance; the size of the metal layer in the bonding wire area is determined by the width of the bonding area; the distance between adjacent metal layers is determined by the minimum insulation distance; the arc height of the bonding wire is determined by the bonding process; the width of the metal layer in the remaining region is determined by the width of the input wiring. Table 2 shows the design rules in the present embodiment.
TABLE 2 design rules of the examples
Figure BDA0002986437070000071
S45, parallel connection mode and loop number N input according to sequenceloopThe basic layout is expanded in parallel, as shown in FIG. 3, into translation andtwo cases are mirrored:
translation expansion: translating the basic layout by NloopThen, generate NloopA basic layout, making the layout space the same as the space of the metal layer in the layout;
mirror image expansion: the basic layout is firstly mirrored, the new layout is merged, and then the new layout is translated by N loop2 times, making the layout space the same as the space of the metal layer in the layout;
and finally outputting the expanded layout as a result.
The specific steps of the commutation inductance in step S5 are as follows: firstly, a patterned metal layer and a bonding wire are dispersed into an equivalent circuit consisting of an RL network, a negative terminal of a module is used as a reference node, and an alternating current excitation I is injected into a positive terminalDC+Solving the voltage response V of the positive terminalDC+The commutation inductance is calculated by the following formula:
Figure BDA0002986437070000072
where f is the frequency of the excitation current. Example f is 10 MHz.
The implementation flow of the embodiment is shown in fig. 4, the number of the initial generation population is selected to be 30, the maximum number of iterations is selected to be 50, the result tends to converge, and the results of the past iterations and the finally obtained pareto frontier are shown in fig. 5. Fig. 6 shows the design parameters of the output results along the leading edge trajectory.
To verify the optimization effect of the method, a No. 7 leading edge solution (layout area 14.6 mm) is selected2Commutation inductance 6.1nH), the layout design of which is shown in fig. 7, is reduced by 45% compared with the conventional layout of fig. 8, and the effectiveness of the invention is verified.
The embodiments described above are presented to enable a person having ordinary skill in the art to make and use the invention. It will be readily apparent to those skilled in the art that various modifications to the above-described embodiments may be made, and the generic principles defined herein may be applied to other embodiments without the use of inventive faculty. Therefore, the present invention is not limited to the above embodiments, and those skilled in the art should make improvements and modifications to the present invention based on the disclosure of the present invention within the protection scope of the present invention.

Claims (8)

1. A power semiconductor module substrate optimization design method based on genetic algorithm is characterized by comprising the following steps:
s1, taking the number of parallel chips, the chip size, the minimum chip spacing and the minimum wiring width parameters required by the power semiconductor module substrate design as design input;
s2, reading a substrate paradigm library to obtain paradigm quantity;
s3, generating an initial population: forming a genetic sequence by taking the paradigm number, the loop number, the chip spacing and the wiring width as optimization variables, and randomly generating M groups of sequences as initial populations by taking the paradigm number in S2, the parallel chip number in S1, the minimum chip spacing and the minimum wiring width as limit values of the variables;
s4, generating a layout: aiming at each group of sequences in the population, firstly selecting a basic layout from a normal form library according to normal form numbers, then determining the size of the basic layout according to the number of chips and design rules, and then translating or mirroring the basic layout according to a parallel connection mode and the number of loops to generate an individual substrate layout;
s5, fitness evaluation: calculating the layout area and the current conversion inductance;
s6, genetic calculation: with the minimum layout area and the minimum commutation inductance as the target, screening parents through non-dominant sorting, and generating offspring populations through crossing and variation;
s7, iterative output: and skipping to S4 for iteration until the maximum iteration number K is reached, and acquiring a pareto front solution set as a result to be output.
2. The power semiconductor module substrate optimal design method according to claim 1, characterized in that: the library of substrate paradigms in the step S2 has the following features: the substrate paradigm is composed of a first metal layer, a second metal layer, a third metal layer, a first chip set, a second chip set, a positive electrode, a negative electrode and an alternating current output port, wherein the first chip set and the positive electrode port are arranged on the first metal layer; the second chip set is arranged on the second metal layer; the negative electrode port is arranged on the third metal layer; the positive port is positioned in a first direction of the negative port, the alternating current port is positioned in a second direction of the positive port and the negative port, and the first direction is vertical to the second direction; the paradigm library includes at least the following paradigms:
paradigm 1: the first chip group is positioned in the first direction of the second chip group, and the chips belonging to the first chip group and the chips belonging to the second chip group are arranged along the second direction; a fourth metal layer is arranged in the first direction of the first chip set, and the alternating current output port is arranged on the fourth metal layer;
paradigm 2: the first chip group is positioned in the first direction of the second chip group, and the chips belonging to the first chip group and the chips belonging to the second chip group are arranged along the first direction; the alternating current output port is arranged on the second metal layer and is positioned in the first direction of the first chip set;
paradigm 3: the first chip group is positioned in a second direction of the second chip group, and the chips belonging to the first chip group and the chips belonging to the second chip group are arranged along the second direction; the alternating current output port is arranged on the second metal layer and is positioned in the first direction of the first chip set;
paradigm 4: the first chip group is positioned in the second direction of the second chip group, and the chips belonging to the first chip group and the chips belonging to the second chip group are arranged along the first direction; the alternating current output port is arranged on the second metal layer and is located in the first direction of the first chip set.
3. The power semiconductor module substrate optimal design method according to claim 1, characterized in that: the genetic sequence in step S3 is composed of multi-bit binary codes, where two bits of codes represent a paradigm number, the other two bits of codes represent the number of loops, the other one bit of codes represents a parallel connection mode, the other six bits of codes represent chip spacing, and the other six bits of codes represent wiring width.
4. The power semiconductor module substrate optimal design method according to claim 1, characterized in that: the specific steps of generating the layout in step S4 are as follows:
s41, selecting a basic layout from the paradigm library according to the paradigm number input by the sequence;
s42, inputting the number P of parallel chips according to the sequencetotalAnd the number of loops NloopCalculating the number of parallel chips P in the basic layoutloop＝Ptotal/Nloop；
S43, arranging the chips of the first chip group and the chips of the second chip group along the chip group arrangement direction specified by the basic layout according to the chip spacing input in sequence;
s44, determining the sizes of the metal layer and the bonding wire according to the wiring width and the design rule input in the sequence;
s45, parallel connection mode and loop number N input according to sequenceloopCarrying out parallel expansion on a basic layout, wherein the parallel expansion is divided into two conditions of translation and mirror image;
and finally outputting the expanded layout as a result.
5. The method for optimally designing a power semiconductor module substrate according to claim 4, wherein the step S44 specifically comprises the steps of: the size of the metal layer around the chip and the port is determined by the allowed welting distance; the size of the metal layer in the bonding wire area is determined by the width of the bonding area; the distance between adjacent metal layers is determined by the minimum insulation distance; the arc height of the bonding wire is determined by the bonding process; the width of the metal layer in the remaining region is determined by the width of the input wiring.
6. The power semiconductor module substrate optimal design method according to claim 4, characterized in that: in step S45, the translation is expanded to shift the basic layout by NloopThen, generate NloopA basic layout, making the layout space the same as the space of the metal layer in the layout;
the mirror image is expanded to mirror the basic layout first and then mergedNew layout, and shifting the new layout by NloopAnd 2 times, making the layout pitch the same as the pitch of the metal layer in the layout.
7. The power semiconductor module substrate optimal design method according to claim 1, characterized in that: the specific steps of calculating the commutation inductance in step S5 are as follows: firstly, a patterned metal layer and a bonding wire are dispersed into an equivalent circuit consisting of an RL network, a negative terminal of a module is used as a reference node, and an alternating current excitation I is injected into a positive terminalDC+Solving the voltage response V of the positive terminalDC+The commutation inductance is calculated by the following formula:
Figure FDA0002986437060000031
where f is the frequency of the excitation current.
8. The power semiconductor module substrate optimal design method according to claim 1, characterized in that: the output of the result in step S7 is specifically: acquiring a parent population when iteration is finished, performing non-dominance ordering on the parent population, and acquiring a genetic sequence of a pareto front solution set; wherein, the paradigm number, the number of loops, the chip pitch and the wiring width described in the sequence, and the substrate layout generated in step S4 are used to optimize the design result of the substrate obtained by the genetic algorithm.
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