JP3554479B2

JP3554479B2 - Automatic placement and routing method and automatic placement and routing device

Info

Publication number: JP3554479B2
Application number: JP03686898A
Authority: JP
Inventors: 俊幸森脇; 雅弘祇園; 次康初田
Original assignee: Panasonic Corp; Matsushita Electric Industrial Co Ltd
Current assignee: Panasonic Corp; Panasonic Holdings Corp
Priority date: 1998-02-19
Filing date: 1998-02-19
Publication date: 2004-08-18
Anticipated expiration: 2018-02-19
Also published as: JPH11238802A

Description

【０００１】
【発明の属する技術分野】
本発明は、半導体集積回路における論理回路、特に、標準セル（スタンダードセル）の電圧降下を低減する自動配置配線及び自動配置配線装置に関する。
【０００２】
【従来の技術】
半導体プロセスの微細化及び配線層の多層化に伴って、該配線層を構成するメタル配線は、ますます薄膜化されることにより配線抵抗が増大すると共にその配線ピッチが縮小されることにより配線容量が増大している。このため、半導体集積回路を設計する上で配線の寄生素子を考慮することが重要な設計要素となってきている。
【０００３】
集積回路の回路ブロックに電源電圧を供給する電源配線の設計においては、回路の消費電流と電源配線の寄生素子（抵抗、容量及びインダクタンス）とにより、電源配線に電圧変動が生じる。殊に、動作周波数が数百ＭＨｚを超える集積回路においては、配線抵抗に起因する電圧降下と該電圧降下に起因する遅延に対する対策が重要な課題となる。
【０００４】
従来の自動配置配線方法は、電源配線に生じる電圧降下の対策として、あらかじめ回路ブロック全体の消費電力を見積っておき、その見積もり結果から電源幅を決定したり、回路ブロックの形状に応じて電源補強箇所を決めたりして自動配置配線処理を行なっている。
【０００５】
【発明が解決しようとする課題】
しかしながら、前記従来の自動配置配線方法は、実際の標準セルの配置を考慮していないため、各電源配線に対する電圧降下等が評価されていない。従って、実際の配置処理においては各セルの配置位置によって電圧降下量にばらつきが生じるので、種類が同一の標準セルであっても、配置位置によって遅延時間がばらついてしまうという問題がある。その結果、シミュレーションとの対応が不正確となって、結果的に、過剰な設計マージンや必要以上の電源幅を設けることになり、集積回路の面積が大きくなる。
【０００６】
本発明は、前記従来の問題を解決し、標準セルを配置する設計段階で電源配線の電圧降下量を均等化できるようにすることを第１の目的とし、電圧降下量を抑制できるようにすることを第２の目的とする。
【０００７】
【課題を解決するための手段】
本発明に係る第１の自動配置配線方法は、第１の目的を達成し、複数の標準セルを含む論理回路の自動配置配線方法であって、複数の標準セルの各標準セルごとに、固有の消費電流データ、負荷インピーダンスデータ及び回路活性化率データに基づいて実質的な消費電流である実質消費電流を算出する実質消費電流算出工程と、実質消費電流の合計値がほぼ均等となるように複数の標準セルを複数のセル群に分割する分割工程と、各セル群を論理回路の接続情報に基づいて配置する配置工程とを備えている。
【０００８】
第１の自動配置配線方法によると、論理回路を構成する複数の標準セルを実質消費電流の合計値がほぼ均等となるように複数のセル群に分割するため、セル群ごとの電圧降下量がほぼ均等となる。
【０００９】
第１の自動配置配線方法において、分割工程が、実質消費電流の総和である総消費電流を所定数で除することによりセル群平均消費電流を算出する工程と、セル群ごとの実質消費電流の合計値とセル群平均消費電流の値との差が小さくなるまで複数の標準セルの分割をし直す工程とを含み、配置工程がセル群ごとに各標準セルを列形状に配置する工程を含むことが好ましい。
【００１０】
第１の自動配置配線方法において、分割工程が、実質消費電流の総和である総消費電流を所定数で除することによりセル群平均消費電流を算出する工程と、セル群ごとの実質消費電流の合計値とセル群平均消費電流の値との差が小さくなるまで複数の標準セルの分割をし直す工程とを含み、配置工程が複数のセル群を格子状の電源線に囲まれた領域に配置する工程を含むことが好ましい。
【００１１】
本発明に係る第２の自動配置配線方法は、第２の目的を達成し、複数の標準セルを含む論理回路の自動配置配線方法であって、複数の標準セルの各標準セルごとに、固有の消費電流データ、負荷インピーダンスデータ及び回路活性化率データに基づいて実質的な消費電流である実質消費電流を算出する実質消費電流算出工程と、複数の標準セルのうち実質消費電流が相対的に大きい標準セルを電源線側に配置する配置工程とを備えている。
【００１２】
第２の自動配置配線方法によると、複数の標準セルのうち実質消費電流が相対的に大きい標準セルを電源線側に配置するため、この実質消費電流が相対的に大きい標準セルを、実質消費電流が相対的に小さい他の標準セルを介して電源線に接続する場合よりも電圧降下量が低減する。
【００１３】
本発明に係る第３の自動配置配線方法は、第１又は第２の目的を達成し、複数の標準セルを含む論理回路の自動配置配線方法であって、複数の標準セルの各標準セルごとに、固有の消費電流データ、負荷インピーダンスデータ及び回路活性化率データに基づいて実質的な消費電流である実質消費電流を算出する実質消費電流算出工程と、複数の標準セルを論理回路の接続情報に基づいて複数のセル群に分割する仮配置工程と、実質消費電流の値に基づいて一のセル群に属する標準セルと他のセル群に属する標準セルとを交換する再配置工程とを備えている。
【００１４】
第３の自動配置配線方法によると、論理回路に含まれる複数の標準セルをいったん論理回路の接続情報に基づいて仮配置した後に、実質消費電流の値に基づいて一のセル群に属する標準セルと他のセル群に属する標準セルとを交換するため、一のセル群の実質消費電流の合計値が相対的に大きく、他のセル群の実質消費電流の合計値が相対的に小さい場合には、一のセル群全体の電圧降下量が減少し且つ他のセル群全体の電圧降下量が増大するため、論理回路全体の電圧降下量が均等化する。
【００１５】
第３の自動配置配線方法において、再配置工程が、実質消費電流の合計値が相対的に大きい一のセル群に属する標準セルのうち実質消費電流が相対的に大きい標準セルと、実質消費電流の合計値が相対的に小さい他のセル群に属する標準セルのうち実質消費電流が相対的に小さい標準セルとを、一のセル群の実質消費電流の合計値及び他のセル群の実質消費電流の合計値の差が小さくなるように交換する工程を含むことが好ましい。
【００１６】
第３の自動配置配線方法において、再配置工程が、実質消費電流が大きい一の標準セルと、該一の標準セルよりも電源線側に近い位置に配置され且つ実質消費電流が一の標準セルに比べて小さい標準セルとを交換する工程を含むことが好ましい。
【００１７】
本発明に係る第１の自動配置配線装置は、第１の目的を達成し、複数の標準セルを含む論理回路の自動配置配線装置であって、複数の標準セルを含む論理回路の自動配置配線装置であって、論理回路の接続情報を入力する接続情報入力手段と、各標準セルの固有の消費電流データを入力する固有消費電流データ入力手段と、各標準セルの負荷インピーダンスデータを入力する負荷インピーダンスデータ入力手段と、各標準セルの回路活性化率データを入力する回路活性化率データ入力手段と、標準セルごとに、入力された消費電流データ、負荷インピーダンスデータ及び回路活性化率データに基づいて実質的な消費電流である実質消費電流を算出する実質消費電流算出手段と、実質消費電流の合計値がほぼ均等となるように複数の標準セルを複数のセル群に分割する分割手段と、各セル群を接続情報に基づいて配置する配置手段とを備えている。
【００１８】
第１の自動配置配線装置によると、論理回路を構成する複数の標準セルを実質消費電流の合計値がほぼ均等となるように複数のセル群に分割するため、セル群ごとの電圧降下量がほぼ均等となる。
【００１９】
第１の自動配置配線装置において、分割手段が、実質消費電流の総和である総消費電流を所定数で除することによりセル群平均消費電流を算出するセル群平均消費電流算出部と、セル群ごとの実質消費電流の合計値とセル群平均消費電流の値との差が小さくなるまで複数の標準セルの分割をし直す再分割部とを有し、配置手段がセル群ごとに各標準セルを列形状に配置することが好ましい。
【００２０】
第１の自動配置配線装置において、分割手段が、実質消費電流の総和である総消費電流を所定数で除することによりセル群平均消費電流を算出するセル群平均消費電流算出部と、セル群ごとの実質消費電流の合計値とセル群平均消費電流の値との差が小さくなるまで複数の標準セルの分割をし直す再分割部とを有し、配置手段が複数のセル群を格子状の電源線に囲まれた領域に配置することが好ましい。
【００２１】
本発明に係る第２の自動配置配線装置は、第２の目的を達成し、複数の標準セルを含む論理回路の自動配置配線装置であって、論理回路の接続情報を入力する接続情報入力手段と、各標準セルの固有の消費電流データを入力する固有消費電流データ入力手段と、各標準セルの負荷インピーダンスデータを入力する負荷インピーダンスデータ入力手段と、各標準セルの回路活性化率データを入力する回路活性化率データ入力手段と、標準セルごとに、入力された消費電流データ、負荷インピーダンスデータ及び回路活性化率データに基づいて実質的な消費電流である実質消費電流を算出する実質消費電流算出手段と、複数の標準セルのうち実質消費電流が相対的に大きい標準セルを電源線側に配置する配置手段とを備えている。
【００２２】
第２の自動配置配線装置によると、複数の標準セルのうち実質消費電流が相対的に大きい標準セルを電源線側に配置する配置手段を備えているため、実質消費電流が相対的に大きい標準セルを、実質消費電流が相対的に小さい他の標準セルを介して電源線に接続する場合よりも電圧降下量が低減する。
【００２３】
本発明に係る第３の自動配置配線装置は、第１の目的を達成し、複数の標準セルを含む論理回路の自動配置配線装置であって、論理回路の接続情報を入力する接続情報入力手段と、各標準セルの固有の消費電流データを入力する固有消費電流データ入力手段と、各標準セルの負荷インピーダンスデータを入力する負荷インピーダンスデータ入力手段と、各標準セルの回路活性化率データを入力する回路活性化率データ入力手段と、標準セルごとに、入力された消費電流データ、負荷インピーダンスデータ及び回路活性化率データに基づいて実質的な消費電流である実質消費電流を算出する実質消費電流算出手段と、複数の標準セルを接続情報に基づいて複数のセル群に分割する仮配置手段と、実質消費電流の合計値が相対的に大きいセル群に属する標準セルのうち実質消費電流が相対的に大きい標準セルと、実質消費電流の合計値が相対的に小さいセル群に属する標準セルのうち実質消費電流が相対的に小さい標準セルとを、一のセル群の実質消費電流の合計値及び他のセル群の実質消費電流の合計値の差が小さくなるように交換する再配置手段とを備えている。
【００２４】
第３の自動配置配線装置によると、仮配置手段が、論理回路に含まれる複数の標準セルをいったん接続情報に基づいて仮配置した後に、再配置手段が、仮配置された標準セルのうち、一の電源線に接続された実質消費電流の合計値が相対的に大きい一のセル群と他の電源線に接続された実質消費電流の合計値が相対的に小さい他のセル群とが存在する場合に、一のセル群のうちの消費電流が相対的に大きい標準セルと、他のセル群のうちの消費電流が相対的に小さい他の標準セルとを一のセル群の実質消費電流の合計値及び他のセル群の実質消費電流の合計値の差が小さくなるように交換するため、一の電源線の電圧降下量が減少し且つ他の電源線の電圧降下量が増加するので、論理回路の電圧降下量が均等化する。
【００２５】
第３の自動配置配線装置において、再配置手段が、実質消費電流が大きい一の標準セルと、該一の標準セルよりも電源線側に近い位置に配置され且つ実質消費電流が一の標準セルに比べて小さい標準セルとを交換するセル群内再配置部を有していることが好ましい。
【００２６】
【発明の実施の形態】
（第１の実施形態）
本発明に係る第１の実施形態を図面に基づいて説明する。
【００２７】
図１は本発明の第１の実施形態に係る標準セルの自動配置配線方法の処理フローを表わしている。図１に示すように、まず、所定データ読み込み工程Ｓ０１において、複数の標準セル同士を互いに接続するための論理回路の回路接続情報、自動配置配線を行なう際に必要な設計制約、各標準セルのレイアウト（配置）データ及び固有の消費電流データを含むライブラリデータ、各標準セルの回路活性化率データ並びに各標準セルの負荷インピーダンスデータをそれぞれ読み込む。
【００２８】
ここで、回路活性化率の算出方法は、論理シミュレーションによって各標準セルごとにスイッチング頻度を算出する方法や、論理回路が持つ論理関数に基づいて、一の論理値から他の論理値に遷移する遷移確率を算出する方法等がある。また、負荷インピーダンスの算出方法は、回路接続情報と回路規模とに基づいて、ファンアウト容量、ファンイン容量、配線抵抗及び配線容量を算出する方法等がある。また設計制約は、アスペクト比等のレイアウトを行なう際の概略形状や該概略形状の個数等を与えるデータである。
【００２９】
次に、実質消費電流算出工程Ｓ０２において、所定データ読み込み工程Ｓ０１で読み込まれたデータのうちの、回路活性化率データ、消費電流データ及び負荷インピーダンスデータを用いて、各標準セルの実質的な消費電流及び該実質的な消費電流の総和である総消費電流を算出する。
【００３０】
次に、回路分割工程Ｓ０３において、回路接続情報とレイアウト面積とを考慮しながら、総消費電流を基に実質的な消費電流の合計値がほぼ均等となるように、複数の標準セルを設計制約で与えられる所定数のセル群に分割する。ここでセル群は、自動配置配線方法を用いてレイアウトされる際の、例えば、列形状のサブブロックを構成する標準セルのグループをいい、従って、このサブブロックの数がセル群の数となる。
【００３１】
次に、配置工程Ｓ０４において、セル群に分割された各標準セルを回路接続情報に基づいて配置した後、実配線処理工程Ｓ０５において、それぞれ配置された標準セル同士の配線処理を行なう。
【００３２】
以下、所定データ読み込み工程Ｓ０１、実質消費電流算出工程Ｓ０２及び回路分割工程Ｓ０３の各処理の詳細を図面を参照しながら説明する。
【００３３】
図２は本実施形態に係る自動配置配線方法が対象とする論理回路の一例を示し、図２に示すように、ＮＡＮＤ回路よりなるセル１、ＡＮＤ回路よりなるセル２、３入力ＮＡＮＤ回路よりなるセル３、ＮＯＲ回路よりなるセル４、ＡＮＤ回路よりなるセル５及びインバータ回路よりなるセル６を含んでいる。
【００３４】
まず、所定データ読み込み工程Ｓ０１において、ライブラリデータの読み込み時に、入力波形の鈍りによって発生するスイッチング時における標準セルの種類ごとの消費電流データの貫通電流成分Ｉ_０と消費電流データの負荷依存成分ΔＩとが読み込まれ、さらに、標準セルごとの負荷容量Ｃが読み込まれる。
【００３５】
次に、実質消費電流算出工程Ｓ０２において、各標準セルの実質的な消費電流である平均消費電流を算出する。図３は該論理回路に含まれるセルの各消費電流の算出例を示し、図３に示すように、標準セルの消費電流は、例えば、消費電流データの貫通電流成分Ｉ_０と、消費電流データの負荷依存成分ΔＩ及び負荷容量Ｃの積で表わされる充放電に基づく消費電流（ΔＩ×Ｃ）との和として記述される。さらに、平均消費電流を、消費電流データＩ_０と負荷データΔＩ×Ｃとの和に回路活性化率αを乗じて算出し、図３に示すセル１〜セル６の各算出結果及び総和を得る。
【００３６】
次に、回路分割工程Ｓ０３において、実質消費電流算出工程Ｓ０２の算出結果を基に、平均消費電流の合計値が均等なセル群となるように論理回路を構成するセル１〜セル６を分割する。ここで、例えば、図２に示す論理回路を２つのセル列として配置するとすると、図３に示す各平均消費電流の算出結果から、論理回路の消費電流の総和は１１０（相対値）となり、この消費電流の総和をセル列で除してなるセル群平均消費電流はその値が５５（相対値）となる。従って、このセル群平均消費電流の値に近づくように論理回路を分割してセル１〜セル６をグループ化する。例えば、セル１、セル３及びセル４をグループＡとし、セル２、セル５及びセル６をグループＢとして分割した場合には、グループＡの消費電流は７０（相対値）となり、グループＢの消費電流は４０（相対値）となってグループ間の消費電流が不均等となる。そこで、セル１、セル２及びセル４をグループＡとし、セル３、セル５及びセル６をグループＢとして再度分割すれば、グループＡ及びグループＢが共に消費電流が５５（相対値）となって均等化される。図２において、第１のセル群１１がグループＡに相当し、第２のセル群１２がグループＢに相当する。
【００３７】
このように、第１のセル群１１と第２のセル群１２との消費電流を均等化すると、例えば、回路遅延が最大となる、いわゆる最悪回路遅延経路を構成する標準セルがいずれのサブブロックに含まれていても、電源配線の電圧降下が論理回路内で均等化されるため、回路遅延の配置位置依存性がなくなるので、遅延のばらつきを抑制することができる。
【００３８】
以上説明したように、本実施形態によると、実質消費電流算出工程Ｓ０２及び回路分割工程Ｓ０３を用いて、各セル群に属する標準セルの平均消費電流の合計値を互いに均等化するように論理回路を分割して配置するため、電源配線の電圧降下量が均等化されるので、回路遅延のばらつきを小さくすることができる。その結果、論理回路の動作速度や電源幅等の設計マージンを必要最小限度にまで削減でき、回路の面積を小さくできるので、半導体集積回路に集積化する際に該半導体集積回路の高速化及び高集積化を図ることができる。
【００３９】
なお、セル配置の設計制約として、本実施形態に示した、電源配線の電圧降下を考慮した消費電流に基づく制約の他に、通常の自動配置配線方法と同様に、レイアウト面積や回路遅延による制約を加えてもよい。
【００４０】
また、本実施形態においては、説明を簡単にするために、電源配線の寄生素子を抵抗成分のみとしており、以下の実施形態においても同様とする。
【００４１】
以下、本発明の第１の実施形態に係る自動配置配線方法を実現する自動配置配線装置について図面を参照しながら説明する。
【００４２】
図４は本実施形態に係る自動配置配線装置の動作フローを表わしている。本実施形態に係る自動配置配線装置は外部記憶装置を備えたコンピュータを想定しており、該外部記憶装置及びコンピュータの形態や機種等を問わない。
【００４３】
本実施形態に係る自動配置配線装置の動作を説明すると、図４に示すように、あらかじめ、論理回路に含まれる標準セルの配置と該配置の前提となる消費電流の計算に必要な種々のデータを用意する。すなわち、論理回路の接続記述よりなる回路接続情報２１、各標準セルの固有の消費電流データが登録された消費電流ライブラリ２２、各標準セルのファンアウト容量，ファンイン容量，配線容量及び配線抵抗よりなる負荷データ２３、標準セルの回路活性化率データ２４、自動配置配線をする際に必要な設計制約２５及び各標準セルのレイアウトデータが登録されたレイアウトライブラリ２６を用意する。
【００４４】
まず、これらのデータは、通常、外部記憶装置に格納されており、該データのうちの、消費電流ライブラリ２２、負荷データ２３及び回路活性化率データ２４をＩ／Ｏ手段（図示せず）を通じて装置側に取り込み、セル消費電流算出手段３１が、装置に入力されたデータを基に標準セルごとの平均消費電流を図３に示した手順を用いて算出することによりセル消費電流データ２７を作成する。
【００４５】
次に、回路分割手段３２は、平均消費電流の合計値がほぼ均等となるように複数の標準セルを設計制約２５で定義されたサブブロック数に分割する。ここで、回路分割手段３２は、セル群平均消費電流算出部としてのサブブロック消費電流算出部３２１、再分割部としてのセル群消費電流算出部３２２及びサブブロック消費電流算出部３２１が出力するサブブロックの平均消費電流（＝セル群平均消費電流）とセル群消費電流算出部３２２から出力されるセル群ごとの消費電流とを比較する消費電流比較部３２３とを有している。
【００４６】
具体的には、サブブロック消費電流算出部３２１は、各標準セルの平均消費電流の総和である総消費電流を求め、該総消費電流を設計制約２５に含まれるレイアウトの下位の階層となるサブブロック数で除すことにより各サブブロックの割当電流量（＝セル群平均消費電流）を算出する。一方、セル群消費電流算出部３２２は、各標準セルの平均消費電流と設計制約２５に含まれるサブブロック数及びアスペクト比を基にして、レイアウト面積を考慮しながら、平均消費電流が均等となるように複数の標準セルを複数のセル群に分割した後、該セル群に属する標準セルの平均消費電流を合算して、セル群ごとの消費電流量を算出する。
【００４７】
消費電流比較部３２３は、サブブロック消費電流算出部３２１が算出した割当電流量と、セル群消費電流算出部３２２が算出したセル群の消費電流量とを比較し、これら２つの電流量の差が大きい場合は、その差が小さくなるまで、セル群を生成するグループ化、該セル群ごとの消費電流の算出及び比較の手順を再帰的に繰り返す。このようにすると、論理回路を消費電流が均等なセル群に分割することができる。
【００４８】
次に、セル配置手段３３は、回路分割手段３２が生成したセル群と回路接続情報２１と標準セルのレイアウトライブラリ２６とを用いて、標準セルのセル配置データ２８を作成し、その後、実配線処理手段３４が、標準セル間の配線を行なって最終レイアウトデータ２９を作成する。
【００４９】
以下、回路分割手段３２の動作の詳細について図面を参照しながら説明する。
【００５０】
図５は標準セルよりなるセル列をレイアウトの下位の階層であるサブブロックとした場合のセル配置を示している。図５に示すように、レイアウト上に互いに平行に設けられた電源線及び接地線よりなる第１の電源幹線４１及び第２の電源幹線４２との間には、第１のセル列５１及び第２のセル列５２がそれぞれ配置されている。第１のセル列５１は、電源線及び接地線よりなる第１の電源配線４３を介して第１の電源幹線４１及び第２の電源幹線４２と電気的に接続され、第２のセル列５２は、電源線及び接地線よりなる第２の電源配線４４を介して第１の電源幹線４１及び第２の電源幹線４２と電気的に接続されている。
【００５１】
従って、回路分割手段３２のサブブロック消費電流算出部３２１が、セル消費電流データ２７に基づいて論理回路の総消費電流の１１０（相対値）を算出し、また、セル群消費電流算出部３２２が、各セル列の消費電流が最終的に５５（相対値）となるように論理回路を分割することによりセル１〜セル６をグループ化する。その結果、セル１、セル２及びセル４がグループＡとして第１のセル群５１に割り当てられると共に、セル３、セル５及びセル６がグループＢとして第２のセル群５２に割り当てられる。
【００５２】
以上説明したように、本実施形態に係る自動配置配線装置によると、セル消費電流算出手段３１と回路分割手段３２とを用いて、論理回路の消費電流を均等化するように該論理回路を分割（グループ化）して標準セルを配置するため、電源配線の電圧降下量が均等化されるので、回路遅延のばらつきを抑えることができる。これにより、論理回路の動作速度や電源幅等の設計マージンを必要最小限度にまで削減できるため、半導体集積回路の高速化及び高集積化を図ることができる。
【００５３】
なお、セル配置の設計制約として、電源配線の電圧降下を考慮した消費電流に基づく制約の他に、通常の自動配置配線装置と同様に、レイアウト面積や回路遅延による制約を加えてもよい。
【００５４】
（第１の実施形態の一変形例）
以下、本発明の第１の実施形態の一変形例に係る自動配置配線方法及びその装置について図面を参照しながら説明する。
【００５５】
第１の実施形態においては標準セルよりなるセル列をサブブロックとしたが、本変形例においては、電源幹線とサブブロックの電源配線とを格子状に配置した場合の各電源幹線及び各電源配線で囲まれてなる領域（以下、エリアと呼ぶ。）をサブブロックとする。
【００５６】
図６はこのようなエリアをレイアウトの下位の階層であるサブブロックとした場合のセル配置を示している。図５に示すように、レイアウト上に互いに平行に設けられた電源線及び接地線よりなる複数の電源幹線５５と、該電源幹線５５と直交する電源線及び接地線よりなる複数の電源配線５６が設けられており、複数のエリアがこれらの電源幹線５５及び電源配線５６に囲まれて形成されている。複数のエリアのうちの第１のエリア６１及び第２のエリア６２に着目すると、図４に示す回路分割手段３２のセル群消費電流算出部３２２が、各セル群の消費電流が均等化されるように論理回路を分割する。本変形例においては、セル１及びセル３がグループＡに、また、セル２、セル４及びセル６がグループＢとして分割されるため、第１のエリア６１にグループＡを割り当て、第２のエリア６２にグループＢを割り当てることにより、各サブブロックの消費電流が共に４５（相対値）となる。
【００５７】
このようにグループ化して配置することにより、各エリア内に配置された標準セルの平均消費電流がエリアごとに均等化されるため、論理回路の電圧降下量がほぼ等しくなる。
【００５８】
また、セル群の消費電流を均等化すると、例えば、最悪回路遅延経路を構成する標準セルが、複数のエリアのうちのいずれのエリアに配置されていても、電源配線の電圧降下量が回路内でほぼ均等化されるため、回路遅延の配置位置依存性がなくなるので、遅延のばらつきを抑制することができる。
【００５９】
また、電源幹線５５を格子状に配置しているため、第１の実施形態に比較して、電源配線５６の電圧降下をより小さく抑えることができる。
【００６０】
（第２の実施形態）
以下、本発明に係る第２の実施形態を図面に基づいて説明する。
【００６１】
第１の実施形態においては、複数の標準セルのすべてを対象としてその平均消費電流を基に配置を決定したが、本実施形態においては、配置対象となる標準セルを特定の標準セルに限定し、自動配置配線処理の簡便化を図っている。
【００６２】
図７は本発明の第２の実施形態に係る標準セルの自動配置配線方法の処理フローを表わしている。図７に示すように、まず、所定データ読み込み工程Ｓ０１において、論理回路の回路接続情報、自動配置配線を行なう際に必要な設計制約、標準セルのレイアウトデータ及び固有の消費電流データを含むライブラリデータ、各標準セルの回路活性化率データ並びに各標準セルの負荷インピーダンスデータをそれぞれ読み込む。
【００６３】
次に、実質消費電流算出工程Ｓ０２において、所定データ読み込み工程Ｓ０１で読み込んだデータのうちの、回路活性化率データ、消費電流データ及び負荷インピーダンスデータを用いて、各標準セルの実質的な消費電流及び該実質的な消費電流の総和である総消費電流を算出する。
【００６４】
次に、特定標準セル配置工程Ｓ１３において、複数の標準セルのうちの特定の標準セル、例えば、消費電流の大小等の特定の評価関数によって幾つかの標準セルを選択し、選択された標準セルの配置を他の標準セルよりも先に配置し、その後、不特定標準セル配置工程Ｓ１４により特定の標準セル以外の標準セルを配置する。その後、実配線処理工程Ｓ０５において、特定標準セル及び不特定標準セルの配線処理を行なう。
【００６５】
以下、平均消費電流が相対的に大きい標準セルを特定標準セルに選んだ場合の効果を説明する。
【００６６】
図８は電源配線に接続された３つの標準セルの等価回路を示している。説明を簡単にするため、各標準セル間に敷設されている電源配線はそれぞれ同一の配線長及び配線幅を有しているとし、これにより各配線抵抗は等しいとする。
【００６７】
電源幹線の電圧をＶ０とし、各標準セルの電源配線の接続点の電圧を電源幹線側から順にＶ１，Ｖ２，Ｖ３とすると、これらは以下に示す式（１），（２）及び（３）のように表わされる。
【００６８】
Ｖ１＝Ｖ０ −Ｒ×（Ｉ１＋Ｉ２＋Ｉ３） …（１）
Ｖ２＝Ｖ０ −Ｒ×（Ｉ１＋Ｉ２＋Ｉ３）−Ｒ×（Ｉ２＋Ｉ３） …（２）
Ｖ３＝Ｖ０ −Ｒ×（Ｉ１＋Ｉ２＋Ｉ３）−Ｒ×（Ｉ２＋Ｉ３）−Ｒ×Ｉ３
＝Ｖ０ −Ｒ×Ｉ１ −２Ｒ×Ｉ２ −３Ｒ×Ｉ３ …（３）
式（１）に示すように、電源幹線近傍の接続点の電位Ｖ１は、各標準セルの消費電流の総和に比例して電圧降下が発生することが分かり、一方、式（３）に示すように、電源幹線から最も離れた位置にある接続点の電位Ｖ３は、Ｉ３の消費電流が大きくなるほど電圧降下が大きくなり、その結果遅延時間の劣化が大きくなることが分かる。従って、消費電流が相対的に大きいセルを電源幹線の近傍に配置した方が、回路の遅延時間の劣化を抑制することができる。これにより、論理回路の動作速度や電源幅等の設計マージンを必要最小限度にまで削減できるため、半導体集積回路の高速化及び高集積化を図ることができる。
【００６９】
本実施形態においては、消費電流が大きい一の標準セルについて、その位置と電圧降下との関係について説明したが、複数の標準セルのうちの消費電流が最も大きい標準セルを電源幹線側に配置し、以降、降順となるように標準セルを配置していく方法もある。この場合は、上述の方法よりもさらに電源配線への接続点電位の電圧降下量が少なくなるため、電源幹線から離れた位置にあるセルの遅延時間の劣化を抑制することができる。また、論理回路に含まれる標準セル全体の配置に先立って、特定の標準セルのみを配置するため、回路遅延を考慮した標準セル配置を簡便に得ることができる。
【００７０】
以下、本発明の第２の実施形態に係る自動配置配線方法を実現する自動配置配線装置について図面を参照しながら説明する。
【００７１】
図９は本実施形態に係る自動配置配線装置の動作フローを表わしている。本実施形態に係る自動配置配線装置は外部記憶装置を備えたコンピュータを想定しており、該外部記憶装置及びコンピュータの形態や機種等を問わない。また、図９において、図４に示す構成要素と同一の構成要素には同一の符号を付すことにより説明を省略する。
【００７２】
まず、図９に示すように、セル消費電流算出手段３１は、装置に入力された所定データのうちの消費電流ライブラリ２２、負荷データ２３及び回路活性化率データ２４を用いて標準セルごとの平均消費電流を算出してセル消費電流データ２７を作成する。
【００７３】
次に、特定標準セル配置決定手段７１は、セル消費電流データ２７の算出結果を基に特定の標準セルを選択し、選択された標準セルの配置を決定して特定標準セル配置データ７２を作成する。
【００７４】
次に、セル配置手段７３は、特定標準セル配置データ７２と回路接続情報２１とレイアウトライブラリ２６とを用いて論理回路全体の標準セルのセル配置データ２８を作成する。その後、実配線処理手段３４がセル配置データ２８に基づいて標準セル間の配線を行なって最終レイアウトデータ２９を作成する。
【００７５】
以下、図面を参照しながら具体例を説明する。図１０は消費電流が相対的に大きい標準セルを特定の標準セルに選択し、該特定の標準セルを電源幹線側に指定して配置する様子を示している。図１０に示すように、レイアウト上に設けられた電源線及び接地線よりなる電源幹線５５と、該電源幹線５５と直交し電源線及び接地線よりなる電源配線５６とが配置されており、図１０に示すセル１〜セル６は図２に示した６つの標準セルとそれぞれ同等の標準セルとし、各標準セルの平均消費電流は図３に示した一覧表のデータで表わされるとする。
【００７６】
図９に示す特定標準セル配置決定手段７１が、セル１〜セル６のうちから平均消費電流が相対的に大きいセル４及びセル３を選択し、電源幹線５５の近傍に配置する。その後、セル配置手段７３が、残りのセル１、セル２、セル５及びセル６を配置し、すべての標準セルを含むセル配置データ２８を作成する。
【００７７】
このように、平均消費電流が相対的に大きい標準セルの配置位置を電源幹線側に優先的に指定すると、電源幹線から離れた位置にあるセル１及びセル６の電源配線５６との接続点の電圧降下量が少なくなるため、セル１及びセル６の遅延時間の劣化を抑制することができる。
【００７８】
また、ここでは、電源幹線５５側に配置する特定の標準セルをそれぞれ１つずつとしたが、特定の標準セルを複数個選び、平均消費電流が大きい標準セルから降順に、電源幹線５５側から配置してもよい。このようにすると、上述の方法よりもさらに電源配線５６における接続点電位の電圧降下量が少なくなるため、他の標準セルを介し電源幹線５５から離れた位置にある標準セルの遅延時間の劣化を抑制することができる。
【００７９】
以上説明したように、本実施形態に係る自動配置配線装置によると、特定標準セル配置決定手段７１とセル配置手段７３とが、標準セルごとの平均消費電流の算出結果に基づいて該平均消費電流が相対的に大きい特定の標準セルを電源幹線側に配置するため、論理回路の遅延時間の増大を抑えることができる。その結果、論理回路の動作速度や電源幅等の設計マージンを必要最小限度にまで削減できるため、半導体集積回路の高速化及び高集積化を図ることができる。
【００８０】
また、特定の標準セルを優先的に配置するため、論理回路を構成する標準セルのレイアウト指定の簡便化を図ることができる。
【００８１】
なお、セル配置の設計制約として、電源配線の電圧降下を考慮した消費電流に基づく制約の他に、通常の自動配置配線装置と同様に、レイアウト面積や回路遅延による制約を加えてもよい。
【００８２】
（第３の実施形態）
以下、本発明に係る第３の実施形態を図面に基づいて説明する。
【００８３】
第２の実施形態においては、配置対象の標準セルを特定の標準セルに限定し、自動配置配線の処理の簡便化を図っている。本実施形態においては、いったん標準セルを仮配置した後に又は従来の自動配置方法を用いてすべての標準セルの配置を行なった後に、標準セルごとの平均消費電流データを基に再配置対象となる標準セルを特定し、特定された標準セル同士を交換して平均消費電流を均等化することにより、自動配置配線の処理のさらなる簡便化を図っている。
【００８４】
図１１は本発明の第３の実施形態に係る標準セルの自動配置配線方法の処理フローを表わしている。図１１に示すように、まず、所定データ読み込み工程Ｓ０１において、論理回路の回路接続情報、設計制約、標準セルのレイアウトデータ及び固有の消費電流データを含むライブラリデータ、各標準セルの回路活性化率データ並びに各標準セルの負荷インピーダンスデータをそれぞれ読み込む。
【００８５】
次に、実質消費電流算出工程Ｓ０２において、所定データ読み込み工程Ｓ０１で読み込んだデータのうちの、回路活性化率データ、消費電流データ及び負荷インピーダンスデータを用いて、各標準セルの実質的な消費電流及び該実質的な消費電流の総和である総消費電流を算出する。
【００８６】
次に、仮配置決定工程Ｓ２３において、論理回路に含まれる配置対象のすべての標準セルの配置を決定した後、再配置工程としての特定標準セル交換工程Ｓ２４において、実質消費電流算出工程Ｓ０２で算出した各標準セルの平均消費電流に基づいて、例えば、一のセル群と該一のセル群よりも消費電流が小さい他のセル群とに着目し、一のセル群のうち消費電流が相対的に大きい標準セルを一の特定標準セルとし、他のセル群のうち消費電流が相対的に小さい標準セルを他の特定標準セルとし、これら一の特定標準セルの配置位置と他の特定標準セルの配置位置とを互いに交換することにより消費電流を均等化する。
【００８７】
以下、本発明の第３の実施形態に係る自動配置配線方法を実現する自動配置配線装置について図面を参照しながら説明する。
【００８８】
図１２は本実施形態に係る自動配置配線装置の動作フローを表わしている。本実施形態に係る自動配置配線装置は外部記憶装置を備えたコンピュータを想定しており、該外部記憶装置及びコンピュータの形態や機種等を問わない。また、図１２において、図４に示す構成要素と同一の構成要素には同一の符号を付すことにより説明を省略する。
【００８９】
まず、図１２に示すように、セル消費電流算出手段３１は、装置に入力された所定データのうちの消費電流ライブラリ２２、負荷データ２３及び回路活性化率データ２４を用いて標準セルごとの平均消費電流を算出してセル消費電流データ２７を作成する。
【００９０】
次に、セル仮配置手段８１は、回路接続情報２１と設計制約２５と標準セルのレイアウトライブラリ２６とを用いて論理回路に含まれるすべての標準セルの配置を暫定的に行なう。その後、再配置手段としての特定標準セル交換手段８２が、交換する必要がある特定標準セルを選択して、選択した特定標準セルの配置位置を互いに交換する。
【００９１】
図１３及び図１４は標準セルよりなるセル列をレイアウトの下位の階層であるサブブロックとした場合のセル配置を示している。ここでは、平均消費電流が大きい標準セルと平均消費電流が小さい標準セルとを特定標準セルとして選択し、その配置位置を互いに交換する。
【００９２】
図１３に示すように、レイアウト上に互いに平行に設けられた電源線及び接地線よりなる第１の電源幹線４１及び第２の電源幹線４２との間には、第１のセル列５１及び第２のセル列５２が配置されている。第１のセル列５１は、電源線及び接地線よりなる第１の電源配線４３を介して第１の電源幹線４１及び第２の電源幹線４２と電気的に接続され、第２のセル列５２は、電源線及び接地線よりなる第２の電源配線４４を介して第１の電源幹線４１及び第２の電源幹線４２と電気的に接続されている。ここで、セル１、セル２及びセル５よりなる第１のセル列５１と、セル３、セル４及びセル６よりなる第２のセル列５２とは、図１２に示すセル仮配置手段８１により仮配置された状態であり、セル１〜セル６は図２に示した６つの標準セルとそれぞれ同等の標準セルとし、各標準セルの平均消費電流は図３に示した一覧表のデータで表わされるとする。従って、このような仮配置後の状態では、第１のセル列５１の相対的な消費電流は５０であり、第２のセル列５２の相対的な消費電流は６０であって不均等となる。この後、図１２に示す特定標準セル交換手段８２が、第１のセル列５１のセル５と、第２のセル列５２のセル４とをそれぞれ特定セルに指定してこれらを互いに交換する。交換した結果、新たに構成される、セル１、セル２及びセル５よりなる第１のセル列５１とセル３、セル５及びセル６よりなる第２のセル列５２との消費電流は共に相対値で５５となり均等化される。
【００９３】
図１４は図１２に示すセル仮配置手段８１により仮配置された他の状態を示している。図１３においてはセル列間の交換を説明したが、ここではセル列内の交換を説明する。図１４に示すように、第１のセル列５１内では平均消費電流が最大であるセル４が第１の電源幹線４１側に配置されておらず、また、第２のセル列５２内でも平均消費電流が最大であるセル３が第１の電源幹線４１側に配置されていないため、第１の電源幹線４１から離れた位置にあるセルにおける電源配線４３，４４との接続点電位の各電圧降下量が大きくなっている。
【００９４】
その後、図２に示す特定標準セル交換手段８２が、第１のセル列５１においてセル２及びセル４を特定セルに指定すると共に、第２のセル列５２においてセル３及びセル６を特定セルに指定し、これらをセル列内でそれぞれ交換する。
【００９５】
交換した結果、再配置された第１のセル列５１及び第２のセル列５２はいずれも消費電流の大きなセルから順に第１の電源幹線４１側に配置されることになり、第１の電源幹線４１から離れた位置にあるセルの電源配線との接続点電位の電圧降下量が少なくなるため、遅延時間の劣化を抑制することができる。
【００９６】
以上説明したように、本実施形態に係る自動配置配線装置によると、セル仮配置手段８１と特定標準セル交換手段８２とが、標準セルごとの平均消費電流の算出結果を基に特定の標準セルの配置位置を交換するため、電源配線の電圧降下量を均等にしたり、小さくしたりすることができるようになり、回路遅延のばらつきを小さくすることができる。これにより、論理回路の動作速度や電源幅等の設計マージンを必要最小限度にまで削減できるため、半導体集積回路の高速化及び高集積化を図ることができる。
【００９７】
また、回路全体のセル配置を行なった後に特定のセルを配置交換するため、従来の自動配置配線装置からの変更が少なく、効果的なレイアウトを簡便に得ることができる。
【００９８】
なお、セル配置の設計制約として、電源配線の電圧降下を考慮した消費電流に基づく制約の他に、通常の自動配置配線装置と同様に、レイアウト面積や回路遅延による制約を加えてもよい。
【００９９】
また、本発明の第１〜第３の実施形態においては、電源配線の寄生素子として抵抗成分のみを考えたが、配線容量や配線インダクタンスを考慮した場合にも、同様の効果を得ることができる。
【０１００】
【発明の効果】
本発明の第１の自動配置配線方法及び第１の自動配置配線装置によると、論理回路を構成する複数の標準セルを実質消費電流の合計値がほぼ均等となるように複数のセル群に分割するため、セル群ごとの電圧降下量がほぼ均等となるので、回路遅延のばらつきを抑制できる。これにより、論理回路の動作速度や電源幅等の設計マージンを削減できるため、半導体集積回路の高速化及び高集積化を図ることができる。
【０１０１】
第１の自動配置配線方法において、分割工程が、実質消費電流の総和である総消費電流を所定数で除することによりセル群平均消費電流を算出する工程と、セル群ごとの実質消費電流の合計値とセル群平均消費電流の値との差が小さくなるまで複数の標準セルの分割をし直す工程とを含み、配置工程がセル群ごとに各標準セルを列形状に配置する工程を含むと、列形状をなすセル群をサブブロックとすれば、サブブロックごとの電圧降下量がほぼ均等となるので、該サブブロックの遅延のばらつきを確実に抑制できる。
【０１０２】
第１の自動配置配線方法において、分割工程が、実質消費電流の総和である総消費電流を所定数で除することによりセル群平均消費電流を算出する工程と、セル群ごとの実質消費電流の合計値とセル群平均消費電流の値との差が小さくなるまで複数の標準セルの分割をし直す工程とを含み、配置工程が複数のセル群を格子状の電源線に囲まれた領域に配置する工程を含むと、格子状の電源線に囲まれた領域をサブブロックとすれば、サブブロックごとの電圧降下量がほぼ均等となるので、該サブブロックの遅延のばらつきをさらに抑制できる。
【０１０３】
本発明の第２の自動配置配線方法及び第２の自動配置配線装置によると、複数の標準セルのうちで実質消費電流が相対的に大きい標準セルを電源線側に配置するため、この実質消費電流が相対的に大きい標準セルを、実質消費電流が相対的に小さい他の標準セルを介して電源線に接続する場合よりも電圧降下量が低減する。従って、実質消費電流が相対的に大きい標準セルであっても、遅延時間が増大することがなく、論理回路の動作速度や電源幅等の設計マージンを削減できるため、半導体集積回路の高速化及び高集積化を図ることができる。
【０１０４】
本発明の第３の自動配置配線方法によると、複数の標準セルを接続情報に基づいていったん仮配置した後、実質消費電流の値に基づいて一のセル群に属する標準セルと他のセル群に属する標準セルとを交換するため、一のセル群の実質消費電流の合計値が相対的に大きく、他のセル群の実質消費電流の合計値が相対的に小さい場合には、一のセル群全体の電圧降下量が減少し且つ他のセル群全体の電圧降下量が増大するため、論理回路全体の電圧降下量が均等化するので、回路遅延のばらつきを抑制できる。これにより、論理回路の動作速度や電源幅等の設計マージンを削減できるため、半導体集積回路の高速化及び高集積化を図ることができる。
【０１０５】
第３の自動配置配線方法において、再配置工程が、実質消費電流の合計値が相対的に大きい一のセル群に属する標準セルのうち実質消費電流が相対的に大きい標準セルと、実質消費電流の合計値が相対的に小さい他のセル群に属する標準セルのうち実質消費電流が相対的に小さい標準セルとを、一のセル群の実質消費電流の合計値及び他のセル群の実質消費電流の合計値の差が小さくなるように交換する工程を含むと、一の電源線に接続された実質消費電流の合計値が大きい一のセル群と他の電源線に接続された実質消費電流の合計値が小さい他のセル群が存在する場合に、一のセル群のうちの消費電流が相対的に大きい標準セルと、他のセル群のうちの消費電流が相対的に小さい標準セルとを交換するため、一の電源線の電圧降下量が減少し且つ他の電源線の電圧降下量が増加して論理回路の電圧降下量が均等化するので、回路遅延のばらつきを確実に抑制できる。
【０１０６】
第３の自動配置配線方法において、再配置工程が、実質消費電流が大きい一の標準セルと、該一の標準セルよりも電源線側に近い位置に配置され且つ実質消費電流が一の標準セルに比べて小さい標準セルとを交換する工程を含むと、消費電流が大きい一の標準セルが他の標準セルを介して電源線に接続される場合に比べて該一の標準セルの電圧降下量を確実に低減できる。
【０１０７】
本発明の第３の自動配置配線装置によると、一の電源線に接続された実質消費電流の合計値が大きい一のセル群と他の電源線に接続された実質消費電流の合計値が小さい他のセル群が存在する場合に、一のセル群のうちの消費電流が相対的に大きい標準セルと、他のセル群のうちの消費電流が相対的に小さい標準セルとを交換するため、一の電源線の電圧降下量が減少し且つ他の電源線の電圧降下量が増加して論理回路の電圧降下量が均等化するので、回路遅延のばらつきを抑制できる。これにより、論理回路の動作速度や電源幅等の設計マージンを削減できるため、半導体集積回路の高速化及び高集積化を図ることができる。
【図面の簡単な説明】
【図１】本発明の第１の実施形態に係る自動配置配線方法を表わす処理フロー図である。
【図２】本発明の第１〜第３の実施形態に係る自動配置配線方法及び自動配置配線装置が対象とする論理回路を示す回路図である。
【図３】図２に示す論理回路が含む各セルの消費電流の算出方法を示す図である。
【図４】本発明の第１の実施形態に係る自動配置配線装置の動作フロー図である。
【図５】本発明の第１の実施形態に係る自動配置配線装置が作成するセル配置を示し、セル列をサブブロックとする平面図である。
【図６】本発明の第１の実施形態の一変形例に係る自動配置配線装置のセル配置を示し、電源線で囲まれてなる領域をサブブロックとする平面図である。
【図７】本発明の第２の実施形態に係る自動配置配線方法を表わす処理フロー図である。
【図８】本発明の第２の実施形態に係る自動配置配線方法の原理を説明するための、電源配線に接続された標準セルの等価回路図である。
【図９】本発明の第２の実施形態に係る自動配置配線装置の動作フロー図である。
【図１０】本発明の第２の実施形態に係る自動配置配線装置のセル配置を示す平面図である。
【図１１】本発明の第３の実施形態に係る自動配置配線方法を表わす処理フロー図である。
【図１２】本発明の第３の実施形態に係る自動配置配線装置の動作フロー図である。
【図１３】本発明の第３の実施形態に係る自動配置配線装置のセル配置を示し、セル列間でセル交換を行なう様子を表わす平面図である。
【図１４】本発明の第３の実施形態に係る自動配置配線装置のセル配置を示し、セル列内でセル交換を行なう様子を表わす平面図である。
【符号の説明】
Ｓ０１所定データ読み込み工程
Ｓ０２実質消費電流算出工程
Ｓ０３回路分割工程
Ｓ０４配置工程
Ｓ０５実配線処理工程
Ｓ１３特定標準セル配置工程
Ｓ１４不特定標準セル配置工程
Ｓ２３仮配置工程
Ｓ２４特定標準セル交換工程（再配置工程）
１１第１のセル群
１２第２のセル群
２１回路接続情報
２２消費電流ライブラリ
２３負荷データ
２４回路活性化率データ
２５設計制約
２６レイアウトライブラリ
２７セル消費電流データ
２８セル配置データ
２９最終レイアウトデータ
３１セル消費電流算出手段
３２回路分割手段
３２１サブブロック消費電流算出部（セル群平均消費電流算出部）
３２２セル群消費電流算出部（再分割部）
３２３消費電流比較部
３３セル配置手段
３４実配線処理手段
４１第１の電源幹線
４２第２の電源幹線
４３第１の電源配線
４４第２の電源配線
５１第１のセル列
５２第２のセル列
５５電源幹線
５６電源配線
６１第１のエリア
６２第２のエリア
７１特定標準セル配置決定手段
７２特定標準セル配置データ
７３セル配置手段
８１セル仮配置手段
８２特定標準セル交換手段（再配置手段）
Ｉ_０消費電流の貫通電流成分
ΔＩ消費電流の負荷依存成分
Ｃ負荷容量
α 回路活性化率[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a logic circuit in a semiconductor integrated circuit, and more particularly to an automatic placement and routing apparatus and an automatic placement and routing apparatus for reducing a voltage drop in a standard cell (standard cell).
[0002]
[Prior art]
With the miniaturization of semiconductor processes and the increase in the number of wiring layers, metal wirings constituting the wiring layers are becoming thinner and thinner, thereby increasing the wiring resistance and reducing the wiring pitch. Is increasing. For this reason, in designing a semiconductor integrated circuit, it is becoming an important design factor to consider wiring parasitic elements.
[0003]
In designing a power supply line for supplying a power supply voltage to a circuit block of an integrated circuit, voltage fluctuation occurs in the power supply line due to current consumption of the circuit and parasitic elements (resistance, capacitance, and inductance) of the power supply line. In particular, in an integrated circuit having an operation frequency exceeding several hundred MHz, it is important to take measures against a voltage drop caused by wiring resistance and a delay caused by the voltage drop.
[0004]
The conventional automatic placement and routing method estimates the power consumption of the entire circuit block in advance as a measure against the voltage drop that occurs in the power supply wiring, determines the power supply width from the estimation result, and reinforces the power supply according to the shape of the circuit block Automatic placement and routing processing is performed by deciding the location.
[0005]
[Problems to be solved by the invention]
However, the conventional automatic placement and routing method does not consider the actual arrangement of the standard cells, and thus does not evaluate a voltage drop or the like for each power supply wiring. Therefore, in the actual arrangement processing, the amount of voltage drop varies depending on the arrangement position of each cell. Therefore, there is a problem that the delay time varies depending on the arrangement position even for standard cells of the same type. As a result, the correspondence with the simulation becomes inaccurate. As a result, an excessive design margin and an unnecessarily large power supply width are provided, and the area of the integrated circuit is increased.
[0006]
SUMMARY OF THE INVENTION It is a first object of the present invention to solve the above-mentioned conventional problem and to make it possible to equalize the voltage drop amount of a power supply wiring at a design stage of arranging a standard cell, and to suppress the voltage drop amount. This is a second object.
[0007]
[Means for Solving the Problems]
A first automatic placement and routing method according to the present invention achieves the first object and is an automatic placement and routing method for a logic circuit including a plurality of standard cells, wherein a unique method is provided for each of the plurality of standard cells. The actual consumption current calculation step of calculating the actual consumption current that is the actual consumption current based on the consumption current data, the load impedance data, and the circuit activation rate data, so that the total value of the actual consumption current is substantially equal. The method includes a dividing step of dividing a plurality of standard cells into a plurality of cell groups, and an arranging step of arranging each cell group based on connection information of a logic circuit.
[0008]
According to the first automatic placement and routing method, a plurality of standard cells constituting a logic circuit are divided into a plurality of cell groups so that the total value of the substantial current consumption is substantially equal. It is almost even.
[0009]
In the first automatic placement and routing method, the dividing step includes a step of calculating a cell group average current consumption by dividing a total current consumption which is a sum of the substantial current consumption by a predetermined number, and a step of calculating the real current consumption of each cell group. Re-dividing the plurality of standard cells until the difference between the total value and the value of the cell group average current consumption is reduced, and the arranging step includes arranging each standard cell in a column shape for each cell group. Is preferred.
[0010]
In the first automatic placement and routing method, the dividing step includes a step of calculating a cell group average current consumption by dividing a total current consumption which is a sum of the substantial current consumption by a predetermined number, and a step of calculating the real current consumption of each cell group. Re-dividing the plurality of standard cells until the difference between the total value and the value of the cell group average current consumption is reduced, and the arranging step includes placing the plurality of cell groups in an area surrounded by grid-like power supply lines. It is preferable to include a step of disposing.
[0011]
A second automatic placement and routing method according to the present invention achieves the second object and is an automatic placement and routing method for a logic circuit including a plurality of standard cells, wherein a unique method is provided for each standard cell of the plurality of standard cells. Current consumption data, load impedance data and circuit activation rate data, based on the actual current consumption of the actual consumption current calculation step of calculating the actual consumption current, the actual consumption current of the plurality of standard cells is relatively Arranging a large standard cell on the power supply line side.
[0012]
According to the second automatic placement and routing method, a standard cell having a relatively large current consumption among a plurality of standard cells is arranged on the power supply line side. The amount of voltage drop is smaller than when the power supply line is connected via another standard cell having a relatively small current.
[0013]
A third automatic placement and routing method according to the present invention achieves the first or second object and is an automatic placement and routing method for a logic circuit including a plurality of standard cells. A real current consumption calculating step of calculating a real current consumption which is a real current consumption based on the unique current consumption data, load impedance data, and circuit activation rate data; and connecting information of a plurality of standard cells to a logic circuit. And a rearrangement step of exchanging a standard cell belonging to one cell group and a standard cell belonging to another cell group based on the value of the actual current consumption. ing.
[0014]
According to the third automatic placement and routing method, after temporarily arranging a plurality of standard cells included in a logic circuit based on connection information of the logic circuit, the standard cells belonging to one cell group are determined based on the value of the actual current consumption. To exchange standard cells belonging to other cell groups, the total value of the real current consumption of one cell group is relatively large, and the total value of the real current consumption of the other cell group is relatively small. Since the voltage drop of the entire cell group decreases and the voltage drop of the other cell group increases, the voltage drop of the entire logic circuit is equalized.
[0015]
In the third automatic placement and routing method, the rearrangement step includes: a standard cell having a relatively large actual current consumption among the standard cells belonging to one cell group having a relatively large total current consumption; Of standard cells belonging to another cell group having a relatively small total value and a standard cell having a relatively small substantial current consumption, and the total value of the substantial current consumption of one cell group and the substantial consumption of the other cell groups. It is preferable to include a step of replacing the current so as to reduce the difference between the total values of the currents.
[0016]
In the third automatic placement and routing method, the rearrangement step includes a step of placing one standard cell having a substantially large current consumption and a standard cell being disposed at a position closer to the power supply line side than the one standard cell and having a substantial current consumption. It is preferable to include a step of replacing the standard cell with a smaller standard cell.
[0017]
A first automatic placement and routing apparatus according to the present invention achieves a first object, and is an automatic placement and routing apparatus for a logic circuit including a plurality of standard cells. An apparatus, comprising: connection information input means for inputting connection information of a logic circuit; unique current consumption data input means for inputting unique current consumption data of each standard cell; and a load for inputting load impedance data of each standard cell. Impedance data input means, circuit activation rate data input means for inputting circuit activation rate data of each standard cell, and, for each standard cell, based on input current consumption data, load impedance data, and circuit activation rate data. And a plurality of standard cells such that the total value of the actual current consumption is substantially equal. It includes dividing means for dividing the cell group number, and arrangement means for arranging on the basis of the respective cell groups in the connection information.
[0018]
According to the first automatic placement and routing apparatus, a plurality of standard cells constituting a logic circuit are divided into a plurality of cell groups so that the total value of the substantial current consumption is substantially equal. It is almost even.
[0019]
In the first automatic placement and routing apparatus, the dividing means calculates a cell group average current consumption by dividing the total current consumption, which is the sum of the substantial current consumption, by a predetermined number; A re-division unit for re-dividing a plurality of standard cells until the difference between the total value of the actual current consumption of each of the cells and the value of the average current consumption of the cell group is reduced, and Are preferably arranged in a row.
[0020]
In the first automatic placement and routing apparatus, the dividing means calculates a cell group average current consumption by dividing the total current consumption, which is the sum of the substantial current consumption, by a predetermined number; A re-division unit that re-divides the plurality of standard cells until the difference between the total value of the actual current consumption of each of the cells and the value of the average current consumption of the cell group is reduced, and the arranging unit divides the plurality of cell groups into a grid. Is preferably arranged in a region surrounded by the power supply line.
[0021]
A second automatic placement and routing apparatus according to the present invention achieves the second object, and is a logic circuit automatic placement and routing apparatus including a plurality of standard cells, wherein connection information input means for inputting connection information of a logic circuit. A unique current consumption data input means for inputting unique current consumption data of each standard cell, a load impedance data input means for inputting load impedance data of each standard cell, and a circuit activation rate data of each standard cell Circuit activation rate data input means, and for each standard cell, the actual current consumption, which is the actual current consumption, based on the input current consumption data, load impedance data, and circuit activation rate data The power supply apparatus further includes a calculating unit and an arranging unit for arranging a standard cell having a relatively large current consumption among the plurality of standard cells on the power supply line side.
[0022]
According to the second automatic placement and routing apparatus, since the arrangement means for arranging the standard cell having a relatively large current consumption among the plurality of standard cells on the power supply line side is provided, the standard having a relatively large substantial current consumption is provided. The amount of voltage drop is smaller than when the cell is connected to the power supply line via another standard cell whose actual current consumption is relatively small.
[0023]
A third automatic placement and routing apparatus according to the present invention achieves the first object and is an automatic placement and routing apparatus for a logic circuit including a plurality of standard cells, wherein connection information input means for inputting connection information of the logic circuit. A unique current consumption data input means for inputting unique current consumption data of each standard cell, a load impedance data input means for inputting load impedance data of each standard cell, and a circuit activation rate data of each standard cell Circuit activation rate data input means, and for each standard cell, the actual current consumption, which is the actual current consumption, based on the input current consumption data, load impedance data, and circuit activation rate data Calculating means, provisional arrangement means for dividing the plurality of standard cells into a plurality of cell groups based on the connection information, and A standard cell having a relatively large actual current consumption among standard cells to be used and a standard cell having a relatively small substantial current consumption among the standard cells belonging to a cell group having a relatively small sum of the substantial current consumption. And a rearrangement means for replacing the total value of the substantial current consumption of the cell group and the total value of the substantial current consumption of the other cell groups.
[0024]
According to the third automatic placement and routing apparatus, after the provisional placement means temporarily places a plurality of standard cells included in the logic circuit based on the connection information, the relocation means sets the provisional standard cells among the provisionally placed standard cells. There is one cell group connected to one power supply line and having a relatively large total current consumption, and another cell group connected to another power supply line having a relatively small total consumption current. In this case, the standard cell having a relatively large current consumption of one cell group and the other standard cell having a relatively small current consumption of another cell group are effectively consumed by the one cell group. Is replaced so that the difference between the total value of the power supply line and the total value of the actual current consumption of the other cell groups is reduced, so that the voltage drop of one power supply line decreases and the voltage drop of the other power supply line increases. Thus, the amount of voltage drop in the logic circuit is equalized.
[0025]
In the third automatic placement and routing apparatus, the rearrangement means includes one standard cell having a substantial current consumption and a standard cell arranged at a position closer to the power supply line side than the one standard cell and having a substantial current consumption. It is preferable to have a cell group rearrangement unit for exchanging a standard cell smaller than the standard cell.
[0026]
BEST MODE FOR CARRYING OUT THE INVENTION
(1st Embodiment)
A first embodiment according to the present invention will be described with reference to the drawings.
[0027]
FIG. 1 shows a processing flow of the standard cell automatic placement and routing method according to the first embodiment of the present invention. As shown in FIG. 1, first, in a predetermined data reading step S01, circuit connection information of a logic circuit for connecting a plurality of standard cells to each other, design constraints required for performing automatic placement and routing, Library data including layout (arrangement) data and unique current consumption data, circuit activation rate data of each standard cell, and load impedance data of each standard cell are read.
[0028]
Here, the method of calculating the circuit activation rate is a method of calculating a switching frequency for each standard cell by a logic simulation, or a transition from one logic value to another logic value based on a logic function of a logic circuit. There is a method of calculating the transition probability, and the like. Further, as a method of calculating the load impedance, there is a method of calculating a fan-out capacity, a fan-in capacity, a wiring resistance, and a wiring capacity based on circuit connection information and a circuit scale. The design constraint is data that gives a schematic shape when performing layout such as an aspect ratio, the number of the schematic shape, and the like.
[0029]
Next, in the actual consumption current calculation step S02, the actual activation of each standard cell is performed using the circuit activation rate data, the consumption current data, and the load impedance data of the data read in the predetermined data reading step S01. A total current consumption, which is a sum of the current and the substantial current consumption, is calculated.
[0030]
Next, in the circuit dividing step S03, a plurality of standard cells are subjected to design constraints such that the total value of the substantial current consumption becomes substantially equal based on the total current consumption, while taking into account the circuit connection information and the layout area. Is divided into a predetermined number of cell groups given by Here, the cell group refers to, for example, a group of standard cells constituting a column-shaped sub-block when laid out using the automatic placement and routing method, and accordingly, the number of this sub-block is the number of cell groups. .
[0031]
Next, in the placement step S04, the standard cells divided into the cell groups are placed based on the circuit connection information, and then, in the actual wiring processing step S05, the wiring processing of the placed standard cells is performed.
[0032]
Hereinafter, details of the predetermined data reading step S01, the substantial current consumption calculating step S02, and the circuit dividing step S03 will be described with reference to the drawings.
[0033]
FIG. 2 shows an example of a logic circuit targeted by the automatic placement and routing method according to the present embodiment. As shown in FIG. 2, the cell 1 is composed of a NAND circuit, the cell 2 is composed of an AND circuit, and is composed of a three-input NAND circuit. It includes a cell 3, a cell 4 composed of a NOR circuit, a cell 5 composed of an AND circuit, and a cell 6 composed of an inverter circuit.
[0034]
First, in a predetermined data reading step S01, at the time of reading library data, the through current component I of the consumption current data for each type of standard cell at the time of switching caused by the dull input waveform. ₀ And the load-dependent component ΔI of the current consumption data are read, and the load capacitance C for each standard cell is read.
[0035]
Next, in a substantial current consumption calculating step S02, an average current consumption which is a substantial current consumption of each standard cell is calculated. FIG. 3 shows a calculation example of each current consumption of the cells included in the logic circuit. As shown in FIG. 3, the current consumption of the standard cell is, for example, a through current component I of the current consumption data. ₀ And the current consumption (ΔI × C) based on charge / discharge represented by the product of the load-dependent component ΔI of the current consumption data and the load capacitance C. Further, the average current consumption is calculated by using the current consumption data I ₀ And the load data ΔI × C are multiplied by the circuit activation rate α to obtain the calculation results and total sum of the cells 1 to 6 shown in FIG.
[0036]
Next, in the circuit dividing step S03, the cells 1 to 6 constituting the logic circuit are divided based on the calculation result of the substantial current consumption calculating step S02 such that the total value of the average current consumption becomes a uniform cell group. . Here, for example, if the logic circuit shown in FIG. 2 is arranged as two cell columns, the sum of the current consumption of the logic circuit is 110 (relative value) from the calculation results of the average current consumption shown in FIG. The value of the cell group average current consumption obtained by dividing the total current consumption by the cell row is 55 (relative value). Therefore, the logic circuit is divided so as to approach the value of the cell group average current consumption, and the cells 1 to 6 are grouped. For example, when the cell 1, the cell 3, and the cell 4 are divided into the group A and the cell 2, the cell 5, and the cell 6 are divided into the group B, the current consumption of the group A is 70 (relative value), and the consumption of the group B is 70%. The current becomes 40 (relative value), and the current consumption between the groups becomes uneven. Therefore, if the cell 1, the cell 2 and the cell 4 are divided into the group A and the cell 3, the cell 5 and the cell 6 are divided again into the group B, the current consumption of both the group A and the group B becomes 55 (relative value). Be equalized. In FIG. 2, the first cell group 11 corresponds to the group A, and the second cell group 12 corresponds to the group B.
[0037]
As described above, when the current consumptions of the first cell group 11 and the second cell group 12 are equalized, for example, the standard cell that constitutes the so-called worst circuit delay path that maximizes the circuit delay becomes , Since the voltage drop of the power supply wiring is equalized in the logic circuit, the dependence of the circuit delay on the arrangement position is eliminated, so that the variation in delay can be suppressed.
[0038]
As described above, according to the present embodiment, the logic circuit is configured to equalize the sum of the average current consumption of the standard cells belonging to each cell group using the substantial current consumption calculation step S02 and the circuit division step S03. Are divided, the amount of voltage drop of the power supply wiring is equalized, so that variations in circuit delay can be reduced. As a result, the design margins such as the operation speed and the power supply width of the logic circuit can be reduced to the necessary minimum, and the circuit area can be reduced. Integration can be achieved.
[0039]
In addition to the constraints based on the current consumption in consideration of the voltage drop of the power supply wiring shown in the present embodiment, the design restrictions on the cell layout are also limited by the layout area and the circuit delay as in the normal automatic layout and wiring method. May be added.
[0040]
Further, in the present embodiment, for simplicity of explanation, the parasitic element of the power supply wiring is made only of the resistance component, and the same applies to the following embodiments.
[0041]
Hereinafter, an automatic placement and routing apparatus for realizing the automatic placement and routing method according to the first embodiment of the present invention will be described with reference to the drawings.
[0042]
FIG. 4 shows an operation flow of the automatic placement and routing apparatus according to the present embodiment. The automatic placement and routing apparatus according to the present embodiment assumes a computer having an external storage device, and the external storage device and the computer may be in any form or model.
[0043]
The operation of the automatic placement and routing apparatus according to the present embodiment will be described. As shown in FIG. 4, various data necessary for calculating the arrangement of the standard cells included in the logic circuit and the current consumption as a premise of the arrangement are obtained in advance. Prepare. That is, the circuit connection information 21 including the connection description of the logic circuit, the current consumption library 22 in which the current consumption data unique to each standard cell is registered, the fan-out capacity, the fan-in capacity, the wiring capacity, and the wiring resistance of each standard cell. A load library 23 is prepared in which registered load data 23, circuit activation rate data 24 of standard cells, design constraints 25 required for automatic placement and routing, and layout data of each standard cell are registered.
[0044]
First, these data are usually stored in an external storage device, and among the data, the current consumption library 22, the load data 23, and the circuit activation rate data 24 are converted through I / O means (not shown). The cell current consumption calculation means 31 calculates the average current consumption for each standard cell using the procedure shown in FIG. 3 based on the data input to the device, and generates the cell current consumption data 27. I do.
[0045]
Next, the circuit dividing means 32 divides the plurality of standard cells into the number of sub-blocks defined by the design constraint 25 so that the total value of the average current consumption becomes substantially equal. Here, the circuit dividing means 32 includes a sub-block consumption current calculation section 321 as a cell group average consumption current calculation section, a cell group consumption current calculation section 322 as a re-division section, and a sub-block consumption current calculation section 321 output by the sub-block consumption current calculation section 321. A current consumption comparison unit 323 for comparing the average current consumption of the block (= cell group average current consumption) with the current consumption of each cell group output from the cell group current consumption calculation unit 322 is provided.
[0046]
Specifically, the sub-block current consumption calculation unit 321 obtains the total current consumption, which is the sum of the average current consumptions of the standard cells, and uses the total current consumption as a sub-level in the lower hierarchy of the layout included in the design constraint 25. By dividing by the number of blocks, the allocated current amount of each sub-block (= cell group average current consumption) is calculated. On the other hand, based on the average current consumption of each standard cell and the number of subblocks and the aspect ratio included in the design constraint 25, the cell group current consumption calculation unit 322 makes the average current consumption uniform while considering the layout area. After dividing the plurality of standard cells into a plurality of cell groups as described above, the average current consumption of the standard cells belonging to the cell group is added up to calculate the amount of current consumption for each cell group.
[0047]
The current consumption comparison unit 323 compares the allocated current amount calculated by the sub-block current consumption calculation unit 321 with the current consumption amount of the cell group calculated by the cell group current consumption calculation unit 322, and calculates the difference between the two current amounts. Is larger, the procedure of grouping for generating the cell group, the calculation of the current consumption for each cell group, and the comparison are recursively repeated until the difference becomes smaller. In this manner, the logic circuit can be divided into a group of cells having a uniform current consumption.
[0048]
Next, the cell placement unit 33 creates the cell placement data 28 of the standard cell using the cell group, the circuit connection information 21, and the layout library 26 of the standard cell generated by the circuit dividing unit 32. The processing unit 34 performs wiring between the standard cells to create the final layout data 29.
[0049]
Hereinafter, the operation of the circuit dividing means 32 will be described in detail with reference to the drawings.
[0050]
FIG. 5 shows a cell arrangement in a case where a cell row composed of standard cells is used as a sub-block which is a lower hierarchy of the layout. As shown in FIG. 5, between a first power supply trunk line 41 and a second power supply trunk line 42 composed of a power supply line and a ground line provided in parallel with each other on the layout, a first cell column 51 and a Two cell rows 52 are arranged respectively. The first cell column 51 is electrically connected to a first power line 41 and a second power line 42 via a first power line 43 composed of a power line and a ground line. Are electrically connected to a first power supply main line 41 and a second power supply main line 42 via a second power supply line 44 composed of a power supply line and a ground line.
[0051]
Accordingly, the sub-block current consumption calculation unit 321 of the circuit dividing unit 32 calculates 110 (relative value) of the total current consumption of the logic circuit based on the cell current consumption data 27, and the cell group current consumption calculation unit 322 calculates By dividing the logic circuit so that the current consumption of each cell column finally becomes 55 (relative value), cells 1 to 6 are grouped. As a result, cell 1, cell 2 and cell 4 are assigned as group A to first cell group 51, and cell 3, cell 5 and cell 6 are assigned as group B to second cell group 52.
[0052]
As described above, according to the automatic placement and routing apparatus according to the present embodiment, the logic circuit is divided using the cell current consumption calculation means 31 and the circuit division means 32 so as to equalize the current consumption of the logic circuit. Since the standard cells are arranged (grouped), the amount of voltage drop of the power supply wiring is equalized, so that variations in circuit delay can be suppressed. As a result, the design margin of the operation speed of the logic circuit, the power supply width, and the like can be reduced to the necessary minimum, so that the speed and integration of the semiconductor integrated circuit can be increased.
[0053]
As a design constraint on the cell arrangement, in addition to the constraint based on the current consumption in consideration of the voltage drop of the power supply wiring, a constraint due to a layout area or a circuit delay may be added similarly to a normal automatic placement and routing apparatus.
[0054]
(Modification of First Embodiment)
Hereinafter, an automatic placement and routing method and apparatus according to a modification of the first embodiment of the present invention will be described with reference to the drawings.
[0055]
In the first embodiment, a cell row composed of standard cells is used as a sub-block. However, in this modified example, each power supply main line and each power supply line when a power supply main line and a power supply line of a sub-block are arranged in a grid pattern. An area surrounded by (hereinafter, referred to as an area) is defined as a sub-block.
[0056]
FIG. 6 shows a cell arrangement when such an area is a sub-block which is a lower hierarchy of the layout. As shown in FIG. 5, a plurality of power supply trunks 55 composed of a power supply line and a ground line provided in parallel with each other on a layout, and a plurality of power supply wirings 56 composed of a power supply line and a ground line orthogonal to the power supply trunk line 55 are provided. A plurality of areas are formed so as to be surrounded by the power supply main line 55 and the power supply wiring 56. Focusing on the first area 61 and the second area 62 of the plurality of areas, the cell group current consumption calculator 322 of the circuit dividing means 32 shown in FIG. 4 equalizes the current consumption of each cell group. The logic circuit is divided as follows. In this modification, cell 1 and cell 3 are divided into group A, and cell 2, cell 4 and cell 6 are divided into group B. Therefore, group A is assigned to first area 61 and second area 61 By allocating the group B to 62, the current consumption of each sub-block becomes 45 (relative value).
[0057]
By grouping and arranging in this manner, the average current consumption of the standard cells arranged in each area is equalized for each area, so that the voltage drop amounts of the logic circuits become substantially equal.
[0058]
Further, when the current consumption of the cell group is equalized, for example, even if the standard cell forming the worst circuit delay path is arranged in any of a plurality of areas, the voltage drop amount of the power supply wiring is reduced in the circuit. Since the circuit delay is substantially equalized, the dependence of the circuit delay on the arrangement position is eliminated, and the variation in the delay can be suppressed.
[0059]
Further, since the power supply main lines 55 are arranged in a lattice shape, the voltage drop of the power supply wiring 56 can be suppressed smaller than in the first embodiment.
[0060]
(Second embodiment)
Hereinafter, a second embodiment according to the present invention will be described with reference to the drawings.
[0061]
In the first embodiment, the arrangement is determined based on the average current consumption of all of the plurality of standard cells, but in the present embodiment, the standard cells to be arranged are limited to specific standard cells. This simplifies the automatic placement and routing process.
[0062]
FIG. 7 shows a processing flow of the standard cell automatic placement and routing method according to the second embodiment of the present invention. As shown in FIG. 7, first, in a predetermined data reading step S01, library data including circuit connection information of a logic circuit, design constraints required for performing automatic placement and routing, layout data of standard cells, and unique current consumption data. Then, the circuit activation rate data of each standard cell and the load impedance data of each standard cell are read.
[0063]
Next, in the actual current consumption calculating step S02, the actual current consumption of each standard cell is determined using the circuit activation rate data, the current consumption data and the load impedance data among the data read in the predetermined data reading step S01. And a total current consumption which is a sum of the substantial current consumption.
[0064]
Next, in the specific standard cell disposing step S13, a specific standard cell among a plurality of standard cells, for example, some standard cells are selected by a specific evaluation function such as the magnitude of current consumption, and the selected standard cells are selected. Are arranged before the other standard cells, and thereafter, standard cells other than the specific standard cells are arranged in the unspecified standard cell arranging step S14. Thereafter, in the actual wiring processing step S05, wiring processing of the specific standard cell and the unspecified standard cell is performed.
[0065]
Hereinafter, the effect when the standard cell having a relatively large average current consumption is selected as the specific standard cell will be described.
[0066]
FIG. 8 shows an equivalent circuit of three standard cells connected to the power supply wiring. For the sake of simplicity, it is assumed that the power supply wirings laid between the standard cells have the same wiring length and wiring width, so that the wiring resistances are equal.
[0067]
Assuming that the voltage of the power supply main line is V0 and the voltages at the connection points of the power supply wiring of each standard cell are V1, V2, and V3 in order from the power supply main line side, these are expressed by the following equations (1), (2), and (3). It is represented as
[0068]
V1 = V0-R * (I1 + I2 + I3) (1)
V2 = V0−R × (I1 + I2 + I3) −R × (I2 + I3) (2)
V3 = V0-R * (I1 + I2 + I3) -R * (I2 + I3) -R * I3
= V0−R × I1−2R × I2−3R × I3 (3)
As shown in equation (1), it is found that the potential V1 at the connection point near the power supply main line causes a voltage drop in proportion to the sum of the current consumption of each standard cell, while the equation (3) shows In addition, it can be seen that the potential V3 of the connection point located farthest from the power supply main line has a larger voltage drop as the current consumption of I3 increases, and as a result, the deterioration of the delay time increases. Therefore, by arranging cells with relatively large current consumption near the power supply main line, it is possible to suppress the deterioration of the circuit delay time. As a result, the design margin of the operation speed of the logic circuit, the power supply width, and the like can be reduced to the necessary minimum, so that the speed and integration of the semiconductor integrated circuit can be increased.
[0069]
In the present embodiment, the relationship between the position and the voltage drop of one standard cell having a large current consumption has been described, but the standard cell having the largest current consumption among a plurality of standard cells is arranged on the power supply main line side. Thereafter, there is a method of arranging the standard cells in descending order. In this case, since the voltage drop of the potential of the connection point to the power supply wiring is smaller than in the above-described method, it is possible to suppress the deterioration of the delay time of the cell located at a position distant from the power supply main line. In addition, since only a specific standard cell is arranged before the entire standard cell included in the logic circuit is arranged, a standard cell arrangement taking circuit delay into account can be easily obtained.
[0070]
Hereinafter, an automatic placement and routing apparatus for realizing an automatic placement and routing method according to a second embodiment of the present invention will be described with reference to the drawings.
[0071]
FIG. 9 shows an operation flow of the automatic placement and routing apparatus according to the present embodiment. The automatic placement and routing apparatus according to the present embodiment assumes a computer having an external storage device, and the external storage device and the computer may be in any form or model. In FIG. 9, the same components as those shown in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted.
[0072]
First, as shown in FIG. 9, the cell current consumption calculating means 31 uses the current consumption library 22, the load data 23 and the circuit activation rate data 24 of the predetermined data input to the device to calculate the average for each standard cell. The current consumption is calculated to create the cell current consumption data 27.
[0073]
Next, the specific standard cell arrangement determining means 71 selects a specific standard cell based on the calculation result of the cell current consumption data 27, determines the arrangement of the selected standard cell, and creates the specific standard cell arrangement data 72. I do.
[0074]
Next, the cell placement unit 73 creates the cell placement data 28 of the standard cells of the entire logic circuit using the specific standard cell placement data 72, the circuit connection information 21, and the layout library 26. Thereafter, the actual wiring processing means 34 performs wiring between the standard cells based on the cell arrangement data 28 to create final layout data 29.
[0075]
Hereinafter, specific examples will be described with reference to the drawings. FIG. 10 shows a state in which a standard cell having a relatively large current consumption is selected as a specific standard cell, and the specific standard cell is designated and arranged on the power supply main line side. As shown in FIG. 10, a power supply trunk line 55 composed of a power supply line and a ground line provided on the layout and a power supply line 56 orthogonal to the power supply trunk line 55 and composed of a power supply line and a ground line are arranged. It is assumed that cells 1 to 6 shown in FIG. 10 are standard cells equivalent to the six standard cells shown in FIG. 2, respectively, and that the average current consumption of each standard cell is represented by data in a list shown in FIG.
[0076]
The specific standard cell arrangement determining means 71 shown in FIG. 9 selects the cells 4 and 3 having relatively large average current consumption from the cells 1 to 6, and arranges them near the power supply main line 55. After that, the cell arranging means 73 arranges the remaining cells 1, 2, 5, and 6, and creates the cell arrangement data 28 including all the standard cells.
[0077]
As described above, when the arrangement position of the standard cell having a relatively large average current consumption is designated preferentially on the power supply main line side, the connection point of the connection point with the power supply wiring 56 of the cell 1 and the cell 6 at a position distant from the power supply main line is designated. Since the amount of voltage drop is reduced, deterioration of the delay time of the cell 1 and the cell 6 can be suppressed.
[0078]
Further, here, the specific standard cells arranged on the power supply main line 55 side are each one. However, a plurality of specific standard cells are selected, and the standard cells having the higher average current consumption are arranged in descending order from the power supply main line 55 side. It may be arranged. By doing so, the voltage drop amount of the connection point potential in the power supply wiring 56 is further reduced as compared with the above-described method. Can be suppressed.
[0079]
As described above, according to the automatic placement and routing apparatus according to the present embodiment, the specific standard cell placement determining means 71 and the cell placement means 73 determine the average current consumption based on the calculation result of the average current consumption for each standard cell. Is arranged on the power supply main line side, it is possible to suppress an increase in the delay time of the logic circuit. As a result, the design margins such as the operation speed of the logic circuit and the power supply width can be reduced to the necessary minimum, so that the speed and integration of the semiconductor integrated circuit can be increased.
[0080]
In addition, since specific standard cells are preferentially arranged, layout designation of standard cells constituting a logic circuit can be simplified.
[0081]
As a design constraint on the cell arrangement, in addition to the constraint based on the current consumption in consideration of the voltage drop of the power supply wiring, a constraint due to a layout area or a circuit delay may be added similarly to a normal automatic placement and routing apparatus.
[0082]
(Third embodiment)
Hereinafter, a third embodiment according to the present invention will be described with reference to the drawings.
[0083]
In the second embodiment, the standard cells to be arranged are limited to specific standard cells, and the processing of automatic arrangement and wiring is simplified. In the present embodiment, once the standard cells are temporarily arranged or after all the standard cells are arranged using the conventional automatic arrangement method, the standard cells are to be rearranged based on the average current consumption data for each standard cell. The standard cells are specified, and the specified standard cells are replaced with each other to equalize the average current consumption, thereby further simplifying the processing of the automatic placement and routing.
[0084]
FIG. 11 shows the processing flow of the standard cell automatic placement and routing method according to the third embodiment of the present invention. As shown in FIG. 11, first, in a predetermined data reading step S01, circuit connection information of a logic circuit, design constraints, library data including standard cell layout data and unique current consumption data, a circuit activation rate of each standard cell The data and the load impedance data of each standard cell are read.
[0085]
Next, in the actual current consumption calculating step S02, the actual current consumption of each standard cell is determined using the circuit activation rate data, the current consumption data and the load impedance data among the data read in the predetermined data reading step S01. And a total current consumption which is a sum of the substantial current consumption.
[0086]
Next, in the provisional placement determination step S23, after determining the placement of all the standard cells to be placed included in the logic circuit, in the specific standard cell replacement step S24 as a relocation step, the actual current consumption calculation step S02 is performed. Based on the average current consumption of each of the standard cells, for example, focusing on one cell group and other cell groups whose current consumption is smaller than that of the one cell group, the current consumption of one cell group is relatively small. The standard cell having a relatively large current consumption is defined as one specific standard cell, and the standard cell having a relatively small current consumption among other cell groups is defined as another specific standard cell. The current consumption is equalized by exchanging the arrangement positions with each other.
[0087]
Hereinafter, an automatic placement and routing apparatus for realizing an automatic placement and routing method according to a third embodiment of the present invention will be described with reference to the drawings.
[0088]
FIG. 12 shows an operation flow of the automatic placement and routing apparatus according to the present embodiment. The automatic placement and routing apparatus according to the present embodiment assumes a computer having an external storage device, and the external storage device and the computer may be in any form or model. In FIG. 12, the same components as those shown in FIG. 4 are denoted by the same reference numerals, and description thereof will be omitted.
[0089]
First, as shown in FIG. 12, the cell current consumption calculating means 31 uses the current consumption library 22, the load data 23 and the circuit activation rate data 24 of the predetermined data input to the device to calculate the average for each standard cell. The current consumption is calculated to create the cell current consumption data 27.
[0090]
Next, the provisional cell arranging means 81 provisionally arranges all the standard cells included in the logic circuit using the circuit connection information 21, the design constraints 25, and the standard cell layout library 26. Thereafter, the specific standard cell exchange means 82 as the relocation means selects the specific standard cells that need to be exchanged, and exchanges the arrangement positions of the selected specific standard cells with each other.
[0091]
FIGS. 13 and 14 show a cell arrangement in a case where a cell row composed of standard cells is used as a sub-block which is a lower hierarchy of the layout. Here, a standard cell having a large average current consumption and a standard cell having a small average current consumption are selected as specific standard cells, and their arrangement positions are exchanged with each other.
[0092]
As shown in FIG. 13, a first cell column 51 and a second cell line 51 are provided between a first power line 41 and a second power line 42, which are composed of a power line and a ground line provided in parallel with each other on the layout. Two cell rows 52 are arranged. The first cell column 51 is electrically connected to a first power line 41 and a second power line 42 via a first power line 43 composed of a power line and a ground line. Are electrically connected to a first power supply main line 41 and a second power supply main line 42 via a second power supply line 44 composed of a power supply line and a ground line. Here, a first cell row 51 composed of cell 1, cell 2 and cell 5 and a second cell row 52 composed of cell 3, cell 4 and cell 6 are combined by temporary cell placement means 81 shown in FIG. In the provisionally arranged state, cells 1 to 6 are standard cells equivalent to the six standard cells shown in FIG. 2, respectively, and the average current consumption of each standard cell is represented by data in the list shown in FIG. Suppose. Therefore, in the state after such provisional placement, the relative current consumption of the first cell row 51 is 50, and the relative current consumption of the second cell row 52 is 60, which is unequal. . Thereafter, the specific standard cell exchange means 82 shown in FIG. 12 designates the cell 5 of the first cell row 51 and the cell 4 of the second cell row 52 as specific cells, and exchanges them with each other. As a result of the exchange, the current consumptions of the newly constructed first cell column 51 composed of cell 1, cell 2 and cell 5 and the second cell column 52 composed of cell 3, cell 5 and cell 6 are both relative. The value is 55, which is equalized.
[0093]
FIG. 14 shows another state in which the cells are temporarily arranged by the cell temporary arrangement means 81 shown in FIG. In FIG. 13, exchange between cell columns has been described. Here, exchange within a cell column will be described. As shown in FIG. 14, the cell 4 having the largest average current consumption is not arranged on the first power supply trunk line 41 side in the first cell row 51, and the averaged current consumption is also in the second cell row 52. Since the cell 3 having the largest current consumption is not arranged on the first power supply main line 41 side, each voltage of the connection point potential with the power supply wirings 43 and 44 in the cell located at a position distant from the first power supply main line 41 The amount of descent is large.
[0094]
After that, the specific standard cell exchange means 82 shown in FIG. 2 designates the cells 2 and 4 as the specific cells in the first cell row 51 and sets the cells 3 and 6 as the specific cells in the second cell row 52. And exchange them in the cell column.
[0095]
As a result of the replacement, the rearranged first cell column 51 and second cell column 52 are both disposed on the first power supply main line 41 side in order from the cell having the largest current consumption. Since the amount of voltage drop of the potential at the connection point with the power supply wiring of the cell located at a position distant from the main line 41 is reduced, deterioration of the delay time can be suppressed.
[0096]
As described above, according to the automatic placement and routing apparatus according to the present embodiment, the cell provisional placement unit 81 and the specific standard cell replacement unit 82 use the specific standard cell based on the calculation result of the average current consumption for each standard cell. Is exchanged, it is possible to equalize or reduce the amount of voltage drop of the power supply wiring, and to reduce variation in circuit delay. As a result, the design margin of the operation speed of the logic circuit, the power supply width, and the like can be reduced to the necessary minimum, so that the speed and integration of the semiconductor integrated circuit can be increased.
[0097]
Further, since the specific cells are replaced after the cells are arranged in the entire circuit, there is little change from the conventional automatic placement and routing apparatus, and an effective layout can be easily obtained.
[0098]
As a design constraint on the cell arrangement, in addition to the constraint based on the current consumption in consideration of the voltage drop of the power supply wiring, a constraint due to a layout area or a circuit delay may be added similarly to a normal automatic placement and routing apparatus.
[0099]
Further, in the first to third embodiments of the present invention, only the resistance component is considered as the parasitic element of the power supply wiring, but the same effect can be obtained when the wiring capacitance and the wiring inductance are considered. .
[0100]
【The invention's effect】
According to the first automatic placement and routing method and the first automatic placement and routing apparatus of the present invention, a plurality of standard cells constituting a logic circuit are divided into a plurality of cell groups so that the total value of the substantial current consumption is substantially equal. As a result, the amount of voltage drop for each cell group becomes substantially equal, so that variations in circuit delay can be suppressed. As a result, a design margin such as an operation speed and a power supply width of the logic circuit can be reduced, so that the speed and integration of the semiconductor integrated circuit can be increased.
[0101]
In the first automatic placement and routing method, the dividing step includes a step of calculating a cell group average current consumption by dividing a total current consumption which is a sum of the substantial current consumption by a predetermined number, and a step of calculating the real current consumption of each cell group. Re-dividing the plurality of standard cells until the difference between the total value and the value of the cell group average current consumption is reduced, and the arranging step includes arranging each standard cell in a column shape for each cell group. If the cell group forming the column shape is a sub-block, the amount of voltage drop in each sub-block becomes substantially equal, so that the variation in delay of the sub-block can be surely suppressed.
[0102]
In the first automatic placement and routing method, the dividing step includes calculating a cell group average current consumption by dividing a total current consumption, which is a sum of the substantial current consumption, by a predetermined number; Re-dividing the plurality of standard cells until the difference between the total value and the value of the cell group average current consumption is reduced, and the arranging step includes placing the plurality of cell groups in an area surrounded by grid-like power supply lines. Including the step of arranging, if the area surrounded by the grid-like power supply lines is a sub-block, the amount of voltage drop for each sub-block becomes substantially equal, so that the variation in delay of the sub-block can be further suppressed.
[0103]
According to the second automatic placement and routing method and the second automatic placement and routing apparatus of the present invention, a standard cell having a relatively large current consumption among a plurality of standard cells is arranged on the power supply line side. The amount of voltage drop is smaller than when a standard cell having a relatively large current is connected to the power supply line via another standard cell having a relatively small current consumption. Therefore, even in the case of a standard cell having relatively large current consumption, the delay time does not increase and the design margin such as the operation speed and the power supply width of the logic circuit can be reduced. High integration can be achieved.
[0104]
According to the third automatic placement and routing method of the present invention, after a plurality of standard cells are temporarily placed based on the connection information, the standard cells belonging to one cell group and the other cell groups are placed based on the value of the actual current consumption. If the total value of the real current consumption of one cell group is relatively large and the total value of the real current consumption of another cell group is relatively small, Since the voltage drop amount of the entire group decreases and the voltage drop amount of the other cell groups increases, the voltage drop amounts of the entire logic circuit are equalized, so that variations in circuit delay can be suppressed. As a result, a design margin such as an operation speed and a power supply width of the logic circuit can be reduced, so that the speed and integration of the semiconductor integrated circuit can be increased.
[0105]
In the third automatic placement and routing method, the rearrangement step includes: a standard cell having a relatively large actual current consumption among the standard cells belonging to one cell group having a relatively large total current consumption; Of the standard cells belonging to another cell group having a relatively small total value and a standard cell having a relatively small substantial current consumption, and the total value of the substantial current consumption of one cell group and the substantial Including a step of replacing the difference in the total value of the currents so as to reduce the difference in the total value of the current, the substantial current consumption connected to the one power supply line connected to one power supply line and the other power supply line connected to the other power supply line When there is another cell group having a small sum of the standard cells, the current consumption of the one cell group is relatively large, and the standard cell of the other cell group is relatively small. To reduce the voltage drop on one power line And the voltage drop amount of the other power supply line to equalize the voltage drop amount of the logical circuit increases, can be reliably suppressed fluctuation of the circuit delay.
[0106]
In the third automatic placement and routing method, the rearrangement step includes a step of placing one standard cell having a substantially large current consumption and a standard cell being disposed at a position closer to the power supply line side than the one standard cell and having a substantial current consumption. Including the step of replacing the standard cell with a smaller standard cell, the voltage drop amount of the one standard cell compared to the case where one standard cell having a large current consumption is connected to the power supply line via another standard cell is included. Can be reliably reduced.
[0107]
According to the third automatic placement and routing apparatus of the present invention, the sum of the substantial current consumption of one cell group connected to one power supply line is large and the total value of the substantial current consumption connected to another power supply line is small. When there is another cell group, to replace a standard cell having a relatively large current consumption of one cell group and a standard cell having a relatively small current consumption of another cell group, Since the amount of voltage drop of one power supply line decreases and the amount of voltage drop of another power supply line increases to equalize the amount of voltage drop of the logic circuit, variation in circuit delay can be suppressed. As a result, a design margin such as an operation speed and a power supply width of the logic circuit can be reduced, so that the speed and integration of the semiconductor integrated circuit can be increased.
[Brief description of the drawings]
FIG. 1 is a process flowchart showing an automatic placement and routing method according to a first embodiment of the present invention.
FIG. 2 is a circuit diagram showing a logic circuit targeted by the automatic placement and routing method and the automatic placement and routing apparatus according to the first to third embodiments of the present invention.
3 is a diagram illustrating a method for calculating current consumption of each cell included in the logic circuit illustrated in FIG. 2;
FIG. 4 is an operation flowchart of the automatic placement and routing apparatus according to the first embodiment of the present invention.
FIG. 5 is a plan view showing a cell arrangement created by the automatic placement and routing apparatus according to the first embodiment of the present invention, where a cell column is a sub-block.
FIG. 6 is a plan view showing a cell arrangement of the automatic placement and routing apparatus according to a modification of the first embodiment of the present invention, and a region surrounded by a power supply line as a sub-block.
FIG. 7 is a processing flowchart illustrating an automatic placement and routing method according to a second embodiment of the present invention.
FIG. 8 is an equivalent circuit diagram of a standard cell connected to a power supply wiring, for explaining the principle of the automatic placement and routing method according to the second embodiment of the present invention.
FIG. 9 is an operation flowchart of the automatic placement and routing apparatus according to the second embodiment of the present invention.
FIG. 10 is a plan view showing a cell arrangement of an automatic placement and routing apparatus according to a second embodiment of the present invention.
FIG. 11 is a processing flowchart showing an automatic placement and routing method according to a third embodiment of the present invention.
FIG. 12 is an operation flowchart of the automatic placement and routing apparatus according to the third embodiment of the present invention.
FIG. 13 is a plan view showing a cell arrangement of the automatic placement and routing apparatus according to the third embodiment of the present invention, and showing how cells are exchanged between cell columns.
FIG. 14 is a plan view showing a cell arrangement of an automatic placement and routing apparatus according to a third embodiment of the present invention, and showing how cells are exchanged in a cell column.
[Explanation of symbols]
S01 Predetermined data reading process
S02 Substantial current consumption calculation step
S03 Circuit dividing process
S04 Placement process
S05 Actual wiring process
S13 Specific standard cell placement process
S14 Unspecified standard cell placement process
S23 Temporary placement step
S24 Specific standard cell exchange process (relocation process)
11 First cell group
12 Second cell group
21 Circuit connection information
22 Current Consumption Library
23 Load data
24 Circuit activation rate data
25 Design constraints
26 Layout Library
27 Cell Current Consumption Data
28 cell layout data
29 Final layout data
31 Cell current consumption calculation means
32 circuit dividing means
321 Sub-block current consumption calculation unit (cell group average current consumption calculation unit)
322 Cell group current consumption calculation unit (re-division unit)
323 Current consumption comparison unit
33 Cell placement means
34 actual wiring processing means
41 1st power supply mains
42 Second power supply mains
43 First Power Wiring
44 Second power supply wiring
51 First cell column
52 Second cell column
55 Power mains
56 Power supply wiring
61 First Area
62 Second area
71 Specific standard cell arrangement determining means
72 Specific standard cell placement data
73 Cell placement means
81 Cell temporary arrangement means
82 Specified standard cell exchange means (relocation means)
I ₀ Through current component of current consumption
ΔI Load dependent component of current consumption
C Load capacity
α circuit activation rate

Claims

An automatic placement and routing method for a logic circuit including a plurality of standard cells,
For each standard cell of the plurality of standard cells, a unique current consumption data, a real current consumption calculating step of calculating a real current consumption that is a substantial current consumption based on the load impedance data and the circuit activation rate data,
A dividing step of dividing the plurality of standard cells into a plurality of cell groups such that the total value of the substantial current consumption is substantially equal;
Arranging each cell group based on the connection information of the logic circuit.

The dividing step includes:
Calculating a cell group average current consumption by dividing the total current consumption, which is the sum of the substantial current consumption, by a predetermined number;
Re-dividing the plurality of standard cells until the difference between the sum of the substantial current consumption for each cell group and the value of the cell group average current consumption is reduced,
The arranging step includes:
2. The automatic placement and routing method according to claim 1, further comprising the step of arranging each standard cell in a column shape for each cell group.

The dividing step includes:
Calculating a cell group average current consumption by dividing the total current consumption, which is the sum of the substantial current consumption, by a predetermined number;
Re-dividing the plurality of standard cells until the difference between the sum of the substantial current consumption for each cell group and the value of the cell group average current consumption is reduced,
The arranging step includes:
2. The automatic placement and routing method according to claim 1, further comprising the step of arranging a plurality of cell groups in a region surrounded by a grid-like power supply line.

An automatic placement and routing method for a logic circuit including a plurality of standard cells,
For each standard cell of the plurality of standard cells, a unique current consumption data, a real current consumption calculating step of calculating a real current consumption that is a substantial current consumption based on the load impedance data and the circuit activation rate data,
An arrangement step of arranging the standard cells having relatively large current consumption among the plurality of standard cells on the power supply line side.

An automatic placement and routing method for a logic circuit including a plurality of standard cells,
For each standard cell of the plurality of standard cells, a unique current consumption data, a real current consumption calculating step of calculating a real current consumption that is a substantial current consumption based on the load impedance data and the circuit activation rate data,
A temporary placement step of dividing a plurality of standard cells into a plurality of cell groups based on the connection information of the logic circuit;
A relocation step of exchanging standard cells belonging to one cell group with standard cells belonging to another cell group based on the value of the substantial current consumption.

The rearrangement step includes:
Among the standard cells belonging to one cell group whose total value of the substantial current consumption is relatively large, a standard cell having a relatively large substantial current consumption and another cell having a relatively small total value of the substantial current consumption The difference between the total value of the substantial current consumption of the one cell group and the total value of the substantial current consumption of the other cell group is smaller than that of the standard cells belonging to the group, wherein the substantial current consumption is relatively small. 6. The automatic placement and routing method according to claim 5, further comprising a step of performing replacement.

The rearrangement step includes:
A step of replacing the one standard cell having a large substantial current consumption with a standard cell arranged closer to the power supply line side than the one standard cell and having a substantial substantial current consumption smaller than the one standard cell; 6. The automatic placement and routing method according to claim 5, comprising:

An automatic placement and routing apparatus for a logic circuit including a plurality of standard cells,
Connection information input means for inputting connection information of the logic circuit;
Unique current consumption data input means for inputting unique current consumption data of each standard cell;
Load impedance data input means for inputting load impedance data of each standard cell,
A circuit activation rate data input means for inputting circuit activation rate data of each standard cell; and a substantial current consumption based on the inputted current consumption data, load impedance data and circuit activation rate data for each standard cell. A real current consumption calculating means for calculating a real current consumption,
Dividing means for dividing a plurality of standard cells into a plurality of cell groups so that the total value of the substantial current consumption becomes substantially equal;
And an arrangement means for arranging each cell group based on the connection information.

The dividing means,
A cell group average current consumption calculation unit that calculates a cell group average current consumption by dividing a total current consumption that is a sum of the substantial current consumption by a predetermined number,
A subdivision unit that re-divides the plurality of standard cells until the difference between the total value of the substantial current consumption for each cell group and the value of the cell group average current consumption is reduced,
The arrangement means,
9. The automatic placement and routing apparatus according to claim 8, wherein each standard cell is arranged in a column shape for each cell group.

The dividing means,
A cell group average current consumption calculation unit that calculates a cell group average current consumption by dividing a total current consumption that is a sum of the substantial current consumption by a predetermined number,
A subdivision unit that re-divides the plurality of standard cells until the difference between the total value of the substantial current consumption for each cell group and the value of the cell group average current consumption is reduced,
The arrangement means,
9. The automatic placement and routing apparatus according to claim 8, wherein a plurality of cell groups are arranged in a region surrounded by a grid-like power supply line.

An automatic placement and routing apparatus for a logic circuit including a plurality of standard cells,
Connection information input means for inputting connection information of the logic circuit;
Unique current consumption data input means for inputting unique current consumption data of each standard cell;
Load impedance data input means for inputting load impedance data of each standard cell,
Circuit activation rate data input means for inputting circuit activation rate data of each standard cell;
For each standard cell, a real current consumption calculating means for calculating a real current consumption which is a real current consumption based on the input current consumption data, load impedance data and circuit activation rate data;
And an arranging means for arranging the standard cells having relatively large current consumption among the plurality of standard cells on the power supply line side.

An automatic placement and routing apparatus for a logic circuit including a plurality of standard cells,
Connection information input means for inputting connection information of the logic circuit;
Unique current consumption data input means for inputting unique current consumption data of each standard cell;
Load impedance data input means for inputting load impedance data of each standard cell,
Circuit activation rate data input means for inputting circuit activation rate data of each standard cell;
For each standard cell, a real current consumption calculating means for calculating a real current consumption which is a real current consumption based on the input current consumption data, load impedance data and circuit activation rate data;
Provisional placement means for dividing a plurality of standard cells into a plurality of cell groups based on the connection information,
Among the standard cells belonging to a cell group having a relatively large sum of the substantial current consumption, a standard cell having a relatively large substantial current consumption and a standard belonging to a cell group having a relatively small sum of the substantial current consumption are included. The standard cells having a relatively small actual current consumption among the cells are exchanged so that the difference between the total value of the substantial current consumption of the one cell group and the total value of the substantial current consumption of the other cell group becomes small. An automatic placement and routing apparatus, comprising:

The relocation means,
A cell that replaces one of the standard cells having a large substantial current consumption and a standard cell that is disposed closer to the power supply line side than the one standard cell and has a substantial current consumption smaller than that of the one standard cell. The automatic placement and routing apparatus according to claim 12, further comprising an intra-group relocation unit.