CN102521460A - Filling method for matted metal - Google Patents
Filling method for matted metal Download PDFInfo
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- CN102521460A CN102521460A CN2011104276110A CN201110427611A CN102521460A CN 102521460 A CN102521460 A CN 102521460A CN 2011104276110 A CN2011104276110 A CN 2011104276110A CN 201110427611 A CN201110427611 A CN 201110427611A CN 102521460 A CN102521460 A CN 102521460A
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Abstract
The invention discloses a filling method for matted metal. The filling method for matted metal includes lithographic simulation, extraction of circuit network lists, simulation of a circuit, delay limit of nodes of the circuit, computation of equivalent electric parameters under lithographic distortion condition, computation of parasitic capacitance limit, and filling of the matted metal under constraint conditions, so that filling of the matted metal with lithographic distortion is realized, influence of lithographic distortion on parasitic resistance and parasitic capacitance is taken into consideration in a parasitism estimation and redundant matted metal filling process, influence of changes of the parasitic resistance and the parasitic capacitance due to filling of redundant matted metal on designed performances of a circuit is controlled within a specified range, flatness of metal interconnection lines of various parts of the circuit is improved to the greatest extent, and accordingly manufacturability of a design of the integrated circuit is improved.
Description
Technical field
The present invention relates to a kind of mute metal filled method, particularly a kind of mute metal filled method to the photoetching distortion.
Background technology
Chemically mechanical polishing is the important step of integrated circuit fabrication process flow process, and after integrated circuit fabrication process entering 65-45nm process node, interconnection line has become the deciding factor that influences chip performance and reliability.Because the difference of the hardness of metal and insulating medium, the chemically mechanical polishing meeting causes the thickness deviation of copper interconnecting line and dielectric layer, and these deviations bring negative effect can for the electrical parameter of interconnection line, and then has influence on the Performance And Reliability of chip.For the redundancy that the chip surface thickness fluctuation that reduces after the chemically mechanical polishing carries out mute metal filled.
Redundant mute metal filled, can cause the growth of interconnect capacitance on the one hand and bring negative effect for the electrical characteristics of chip, this is existing in the mute metal filled process of existing redundancy considers; Owing to causing distortion, the redundant mute metal filled figure that may give existing metal interconnecting wires of the reason of dark nanoscale photoetching distortion causes that interconnection line metallic pattern part narrows down or broadens on the other hand; The dead resistance that makes interconnection line cause becomes big or diminishes; The actual stray capacitance of filling between metal and the interconnection line metallic pattern is bigger than normal or less than normal than the stray capacitance that ideal is estimated because of having certain difference between actual range between the metallic pattern and the ideal distance, and the difference of the variation of this dead resistance and electric capacity estimation can cause the difference that circuit performance is estimated.
Summary of the invention
For solving the problems referred to above that exist in the prior art; The invention provides a kind of fill method of filling redundant mute metal of optimizing, the problem that metal interconnecting wires dead resistance that the photoetching distortion causes in the existing fill method of solution and parasitic capacitor variations influence circuit performance.
Concrete technical scheme is realized by following steps:
A kind of mute metal filled method comprises the steps:
A lithography simulation semiconductor physical layout, the semiconductor physics layout data that obtains distorting;
B carries out the parasitic parameter extraction to the semiconductor physics layout data of said distortion, obtains comprising the circuit meshwork list of spurious element device;
C carries out transient analysis through circuit simulation to the circuit of the semiconductor physics domain of said distortion, obtains the transient analysis result;
E is according to the time-delay limit and the equivalent electrical information of said circuit node, behind the gauze of introducing the redundant mute metal filled physical layout of giving said distortion, calculates the limit stray capacitance that said circuit node carries;
F is the upper limit, repeatedly adjusts mute metal filled method with said circuit node limit stray capacitance, optimizes the mechanical planarization degree of the chip of semiconductor physics domain.
Preferably, the time-delay limit of circuit node described in step D basis is suc as formula calculating shown in (1):
Tdealylimit，n ＝k/fclk；
Wherein, Tdealylimit, n are the time-delay limit on the gauze n of physical layout of said distortion; Fclk is the clock signal frequency of gauze n direct correlation; K is a constant, and its span is generally between [0.01,0.10].
Preferably, said equivalent electrical information comprises circuit node equivalent parasitic capacitances and circuit node equivalence conducting resistance.
Preferably, said circuit node equivalent parasitic capacitances is the existing stray capacitance sum of institute's wired network, comprises that promptly the device of said gauze is connected to the stray capacitance of said gauze and the stray capacitance between the said gauze interconnection line.
Preferably, the device of the said gauze n stray capacitance that is connected to said gauze is according to suc as formula calculating shown in (2);
Cnet.n，exist，dev＝∑Cnet.n，exist，dev，i
(2)
Wherein,
i＝1，2，3，…，Nnet，n，dev_cnum；
Nnet, n, dev_cnum goes up the stray capacitance quantity that device causes for gauze n;
Cnet.n, exist, dev are the stray capacitance that the device of said gauze n is connected to said gauze.
Preferably, the stray capacitance between the mutual interconnection line of said gauze is calculated according to suc as formula calculating shown in (3);
Cnet.n，exist，wire＝∑Cnet.n，exist，wire，i
(3)
Wherein,
i＝1，2，3，…，Nnet，n，wire_cnum；
Nnet, n, wire_cnum are that said gauze n goes up the stray capacitance quantity that interconnection line causes;
Cnet.n, exist, wir are the stray capacitance between the said gauze n interconnection line.
Preferably, the computing method of said circuit node equivalence conducting resistance comprise the steps:
A calculate power supply between the corresponding node of said gauze to the power supply equivalent resistance;
B calculates ground wire to the equivalent resistance over the ground between the corresponding node of gauze;
C said to power supply equivalent resistance and said equivalent resistance over the ground in, choose maximal value and be said circuit node equivalence conducting resistance.
Preferably, said gauze limit stray capacitance is by calculating as shown in the formula (4):
Cnet，n，extra_limit＝Tdealylimit，n/Ron-Cnet.n，exist
Wherein,
Tdealylimit, n are the time-delay limit of gauze n;
Ron is said gauze equivalence conducting resistance;
Cnet.n, exist are the equivalent parasitic capacitances of gauze n;
Cnet, n, extra_limit are the limit stray capacitance that the redundant mute metal filled gauze n of giving introduces.
The present invention is mute metal filled through equivalent electrical parameter calculates under lithography simulation, circuit meshwork list extraction, circuit simulation, the circuit node time-delay limit, the photoetching distortion situation, limit stray capacitance is calculated, mute metal filled under the constraint condition realized considering that photoetching distorts; In the mute metal filled process of parasitism estimation and redundancy, consider the influence of photoetching distortion to dead resistance and stray capacitance; Guarantee redundant mute metal filled dead resistance that causes and parasitic capacitor variations to the circuit design Effect on Performance within preset range; Improve the flatness of circuit each several part metal interconnecting wires substantially, thereby improve the manufacturability of IC design.
Description of drawings
Fig. 1 is a kind of mute metal filled method flow diagram based on the circuit delay limit that the embodiment of the invention provides;
Fig. 2 is the time-delay limit and the equivalent electrical information according to circuit node that the embodiment of the invention provides, and it is mute metal filled to behind the gauze to confirm to introduce redundancy, the process flow diagram of the limit stray capacitance that each circuit node carries;
Fig. 3 is the existing equivalent parasitic capacitances process flow diagram of counting circuit node that the embodiment of the invention provides;
Fig. 4 is the counting circuit node equivalence conducting resistance process flow diagram that the embodiment of the invention provides;
Fig. 5 be the embodiment of the invention provide optimize and revise mute metal filled method flow diagram.
Embodiment
Below in conjunction with embodiment the present invention is further described in detail, the embodiment that provides has been merely and has illustrated the present invention, rather than in order to limit scope of the present invention.
Below in conjunction with accompanying drawing and embodiment, the present invention is elaborated as follows:
Referring to Fig. 1, the embodiment of the invention provides a kind of mute metal filled method based on the circuit delay limit, and details are as follows:
Step S101 carries out lithography simulation to physical layout and obtains the actual photoetching physical layout data of distortion afterwards;
Step S102 extracts the circuit meshwork list that comprises the spurious element device from the physical layout of photoetching distortion;
Step S103 carries out transient analysis through circuit simulation to circuit under the existing physical layout design;
Step S104 analyzes the time-delay limit of definite each circuit node and the equivalent electrical information of circuit node to the transient analysis result;
Step S105 confirms the mute metal filled limit stray capacitance of introducing to gauze of redundancy that each circuit node can carry according to the time-delay limit of each circuit node and the equivalent electrical information of circuit node;
Step S106 is that the upper limit serves as that the planarization that mute metal is guaranteed chemically mechanical polishing is filled in basis estimation stray capacitance, optimization as constraint condition, with the lithography simulation result with the additional parasitic electric capacity that can carry.
In the embodiment of the invention; Step S101 carries out lithography simulation to physical layout and obtains the actual photoetching physical layout data of distortion afterwards: in dark nanoscale ic manufacturing process; The optical wavelength of litho machine is far smaller than the feature process size of integrated circuit; Interfere the effect with diffraction between the light beam, caused the desired metallic interconnection line figure of the physical layout design of actual metal interconnection line figure and integrated circuit after the photoetching to have certain difference, can not react the metal interconnecting wires ghost effect of actual integrated circuit with original desirable layout data extraction parasitic parameter; In order accurately to react the metal interconnecting wires ghost effect of actual integrated circuit; Must carry out lithography simulation to desirable physical layout data, obtain photoetching distortion physical layout data afterwards, and then these data are carried out parasitic parameter extract.Lithography simulation can like the PROLITH of KLA-Tencor company and the SOLID-C of Sigma-C company, or adopt inner photoetching emulation tool by the business software instrument.
In the embodiment of the invention; Step S102 extracts the circuit meshwork list that contains the spurious element device from the physical layout of photoetching distortion: integrated circuit manufacturer externally the technological design bag of issue (Process Design Kit comprises the execution script that extracts the circuit meshwork list that contains the spurious element device from physical layout automatically in PDK).Move business-like parasitic parameter and extract software; Like the ASSURA of CADENCE company, the STAR-RCX of SYNOPSYS company, the CALIBRE of MENTOR company and the Related product of other companies; Certainly also can move endophyte parameter extraction software; Carry out corresponding script command, finally extract the circuit meshwork list that contains the spurious element device.The input data are for closing the physical layout data that gram emulation obtains, and output data is the circuit meshwork list of SPICE form, CDL form or SPEF form.
In the embodiment of the invention; The emulation of step S103 oversampling circuit is carried out transient analysis to the circuit under the existing physical layout design: transient analysis is one of basic function of integrated circuit circuit simulation tools, and the input data of transient analysis comprise circuit meshwork list, test and excitation and operation, measurement and the output control command that contains the spurious element device.The circuit meshwork list that contains the spurious element device by parasitic parameter in the last step extract software to physical layout data calculate produce; Test and excitation is provided by the designer; Operation, measurement and output control command can be set by edit tool or graphic interface tool by the designer; Also can be by measurement that program analyzed the circuit meshwork list of input and automatic generation the, particularly circuit meshwork list node are relevant and the generation of exporting control command.Transient analysis can be through operation commercial circuit emulation tool, like SPECTRE and the ULTRA-SIM of CADENCE, HSPICE and the HSIM of SYNOPSYS, realization; Also can realize through operation internal circuit analysis tool.Transient analysis is activated by the operation control command of above-mentioned emulation tool; Among process is carried out in transient analysis; According to measurement control order and output control command the electricity variate-value of specified node is measured computing, and output information supplies subsequent step to calculate and analyze on request.
Referring to Fig. 2, in the embodiment of the invention, step S104 comprises the equivalent electrical information that the transient analysis result analyzes circuit node under the time-delay limit of confirming each circuit node, the photoetching distortion situation
The step S10401 circuit node time-delay limit is calculated;
The existing equivalent parasitic capacitances of step S10402 circuit node is calculated;
Step S10403 circuit node equivalence conducting resistance is calculated.
The following Tdealylimit of time-delay limit computing formula of step S10401 circuit node, n=k/fclk,
Wherein, Tdealylimit, n are the signal lag limit on the gauze n;
Fclk is the clock signal frequency of gauze n direct correlation;
K is a constant, and its span is generally between [0.01,0.10].
Calculating for the clock signal frequency fclk of gauze n direct correlation: if this gauze is the clock signal gauze; Then fclk is the online signal frequency of this clock cable; Otherwise be starting point with this node; Logical reach is in 1 the scope, seeks clock signal, and the highest its frequency of clock signal of selecting frequency is as fclk; If do not find clock signal, be starting point with this node, distance is in 2 the scope, to seek clock signal, the highest its frequency of clock signal of selecting frequency is as fclk; If do not find clock signal, be starting point with this node, distance is in 3 the scope, to seek clock signal, the highest its frequency of clock signal of selecting frequency is as fclk; By that analogy, until finding clock signal.
The equivalent electrical information spinner of circuit node will comprise this circuit node stray capacitance Cnet, n, extra_limit and be this circuit node stray capacitance Cnet, the conducting resistance Ron that n, extra_limit discharge and recharge.
Referring to Fig. 3, in the embodiment of the invention, the existing equivalent parasitic capacitances of step S10402 circuit node is calculated and is comprised:
The device itself that step S1030401 is connected to this gauze n is connected to the calculating of the stray capacitance of this gauze;
Stray capacitance between the interconnection line of other gauze interconnection lines of step S1030402 and gauze n is calculated;
The existing equivalent parasitic capacitances of step S1040203 circuit node is calculated.
The existing stray capacitance Cnet.n of gauze n; Exist is the existing stray capacitance sum of this gauze; Comprise that the device itself that is connected to this gauze n is connected to the stray capacitance Cnet.n of this gauze, exist, the stray capacitance Cnet.n between the interconnection line of dev, other gauze interconnection lines and gauze n; Exist, wire.
The device itself that step S1040201 is connected to this gauze n is connected to the stray capacitance Cnet.n of this gauze, exist, the calculating of dev: read in parasitic parameter and extract circuit meshwork list that obtain, that comprise the spurious element device; The device that traversal gauze n connects; Obtain the stray capacitance that is connected with this gauze on these devices from the circuit simulation output file; They are sued for peace, can obtain Cnet.n, exist, dev:
Cnet.n，exist，dev＝∑Cnet.n，exist，dev，i
Wherein,
i＝1，2，3，…，Nnet，n，dev_cnum；
Nnet, n, dev_cnum goes up the stray capacitance quantity that device causes for gauze n.
Stray capacitance Cnet.n between the interconnection line of other gauze interconnection lines of step S1040202 and gauze n, exist, the calculating of wire: read in parasitic parameter and extract circuit meshwork list that obtain, that comprise the spurious element device; Traversal gauze n goes up the stray capacitance that interconnection line causes; They are sued for peace, can obtain Cnet.n, exist, wire:
Cnet.n，exist，wire＝∑Cnet.n，exist，wire，i
Wherein,
i＝1，2，3，…，Nnet，n，wire_cnum；
Nnet, n, wire_cnum goes up the stray capacitance quantity that interconnection line causes for gauze n.
The existing equivalent parasitic capacitances of step S1030203 circuit node is calculated Cnet.n, the calculating of exist: to Cnet.n, and exist, dev and Cnet.n, exist, wire sues for peace, and can obtain Cnet.n, exist:
Cnet.n，exist＝Cnet.n，exist，dev+Cnet.n，exist，wire
Referring to Fig. 4, in the embodiment of the invention, step S10303 circuit node equivalence conducting resistance is calculated: be this circuit node stray capacitance Cnet, the calculating of the conducting resistance Ron that n, extra_limit discharge and recharge comprises:
Step S1040301 calculate power supply between the corresponding node of gauze n to power supply equivalent resistance Rp_on;
Step S1040302 calculate ground between the corresponding node of gauze n to power supply equivalent resistance Rn_on;
Step S1040303 is this circuit node stray capacitance Cnet, the conducting resistance Ron that n, extra_limit discharge and recharge.
Step S1040301 calculate power supply between the corresponding node of gauze n to power supply equivalent resistance Rp_on: as starting point, search out the DC channel of power supply with the corresponding node of gauze n; Calculate the equivalent conducting electricity of each conduction device with the bias condition of device to the DC channel of power supply and conducting state thereof and lead gp_on, i or conducting resistance rpon, i; Set up the SP annexation of these conducting resistance and associated interconnect line dead resistance according to the annexation of these conduction devices and associated interconnect line dead resistance; According to these equivalent conducting resistance rp_on, the SP annexation of i and associated interconnect line dead resistance calculate power supply between the corresponding node of gauze n to power supply equivalent resistance Rp_on;
Step S1040302 calculate ground between the corresponding node of gauze n to power supply equivalent resistance Rn_on: as starting point, search out the DC channel on ground with the corresponding node of gauze n; Calculate the equivalent conducting electricity of each conduction device with the bias condition of device to the DC channel on ground and conducting state thereof and lead gn_on, i or conducting resistance rnon, i; Set up the SP annexation of these conducting resistance and associated interconnect line dead resistance according to the annexation of these conduction devices and associated interconnect line dead resistance; According to these equivalent conducting resistance rn_on, the SP annexation of i and associated interconnect line dead resistance is calculated power supply to the Rn_on of equivalent resistance over the ground between the corresponding node of gauze n;
Step S1040303 is this circuit node stray capacitance Cnet; N; The conducting resistance Ron that extra_limit discharges and recharges: to power supply equivalent resistance Rp_on and choose the equivalent resistance Rn_on over the ground resistance bigger as gauze n circuit node stray capacitance Cnet, the conducting resistance Ron that n, extra_limit discharge and recharge; Be Ron=max (Rp_on, Rp_on).
In the embodiment of the invention, step S105 confirms the mute metal filled limit stray capacitance of introducing to gauze of redundancy that each circuit node can carry according to the time-delay limit of each circuit node, the equivalent electrical information of closing circuit node under the gram distortion situation: the time-delay limit computing formula of gauze n is following
Tdealylimit，n＝Ron*(Cnet.n，exist+Cnet，n，extra_limit)
Wherein,
Tdealylimit, n are the time-delay limit of gauze n;
Ron is the conducting resistance of gauze when discharging and recharging;
Cnet.n, exist are the existing stray capacitance of gauze n;
Cnet, n, extra_limit are the limit stray capacitance that the redundant mute metal filled gauze n of giving introduces.
This computing formula conversion is obtained the limit stray capacitance computing formula that the redundant mute metal filled gauze n of giving introduces
Cnet，n，extra?limit＝Tdealylimit，n/Ron-Cnet.n，exist
Wherein,
The time-delay limit Tdealylimit of gauze n, n is calculated by a last step;
Conducting resistance Ron_limit when gauze discharges and recharges is calculated by a last step;
The existing stray capacitance Cnet.n of gauze n, exist are the existing stray capacitance sum of this gauze, comprise that the device itself that is connected to this gauze n is connected to the stray capacitance between the interconnection line of the stray capacitance of this gauze, other gauze interconnection lines and gauze n.
Referring to Fig. 5, in embodiments of the present invention, step S106 is that the upper limit serves as that basis estimation stray capacitance, optimization are filled mute metal and guaranteed that the planarization of chemically mechanical polishing comprises as constraint condition, with the lithography simulation with the extra limit stray capacitance that can carry:
It is mute metal filled that step S10601 produces the redundancy of attempting;
Step S10602 lithography simulation;
Step S10603 parasitic parameter extracts;
The redundant mute metal filled stray capacitance that causes in step S10604 estimation circuit node place;
Step S10605 checks the mute metal filled constraint condition that whether satisfies of current redundancy, if satisfy condition, then carries out next step, otherwise execution in step S10601;
Step S10606 calculating target function; Determine whether to select current filling and be left the best record of filling according to optimized Algorithm; Repeating step step S10601 is to step S10606; The mute metal filled target function value that makes of constantly adjustment redundancy constantly reduces under the situation that cycling condition satisfies in optimized Algorithm, and the cycling condition in satisfying optimized Algorithm does not withdraw from circulation when not satisfying, and carries out next step;
Step S10607 finishes to fill optimizing process.
In filling mute metal process; Stray capacitance summation to each gauze can not surpass the additional parasitic capacitance pole limit value that last step calculated; Adjust pattern filling with this understanding and make the metal height standard deviation after the chemically mechanical polishing, its mathematical description is following
Constraint condition: C net, n≤Cnet, n, extra_limit n=1,2 ..., Nnets
Objective function: f=min{SQRT [∑ (Hi-Hmean) 2/Nnet_wire] }
i＝1，2，...，Nnet_wire
Wherein
C net, n be n gauze because of about it, about fill the stray capacitance that metal is introduced;
Cnet, n, extra_limit be n gauze because of about it, about fill the ultimate value of the stray capacitance that metal introduces;
Nnets is a line screen;
Nnet_wire is a gauze metal connecting line hop count.
Hmean is the average height of gauze metal connecting line, Hmean=∑ Hi i=1, and 2 ..., Nnet_wire.
C net, its calculation expression of n does
C?net，n＝∑C?net，n，i
Wherein,
i＝1，2，...，Nnet，n，fc_num；
Nnet, n, fc_numw is the corresponding redundant mute metal filled stray capacitance quantity of causing for gauze n;
C net, n, i is redundant mute metal filled i dead resistance of causing for gauze n, this stray capacitance is that the corresponding redundant mute metal filled lithography simulation that carries out afterwards carries out parasitic parameter again and extracts resulting stray capacitance.
Optimization problem under the constraint condition is found the solution, and existing simulated annealing, genetic algorithm, particle cluster algorithm all can the Control and Optimization realization process, and concrete realization can not done detailed explanation at this with reference to the corresponding reference of these algorithms.
The above only is preferred embodiment of the present invention, so all equivalences of doing according to the described structure of patent claim of the present invention, characteristic and principle change or modify, includes in patent claim of the present invention.
Claims (8)
1. a mute metal filled method is characterized in that, comprises the steps:
A lithography simulation semiconductor physical layout, the semiconductor physics layout data that obtains distorting;
B carries out the parasitic parameter extraction to the semiconductor physics layout data of said distortion, obtains comprising the circuit meshwork list of spurious element device;
C carries out transient analysis through circuit simulation to the circuit of the semiconductor physics domain of said distortion, obtains the transient analysis result;
D calculates said transient analysis result, confirms the time-delay limit and the equivalent electrical information of circuit node in the circuit of semiconductor physics domain of said distortion;
E is according to the time-delay limit and the equivalent electrical information of said circuit node, behind the gauze of introducing the redundant mute metal filled physical layout of giving said distortion, calculates the limit stray capacitance that said circuit node carries;
F is the upper limit, repeatedly adjusts mute metal filled method with said circuit node limit stray capacitance, optimizes the mechanical planarization degree of the chip of semiconductor physics domain.
2. method according to claim 1 is characterized in that, the time-delay limit basis of circuit node described in the step D is suc as formula calculating shown in (1):
Tdealylimit，n ＝k/fclk；
Wherein, Tdealylimit, n are the time-delay limit on the gauze n of physical layout of said distortion; Fclk is the clock signal frequency of said gauze n direct correlation; K is a constant, and its span is generally between [0.01,0.10].
3. method according to claim 1 is characterized in that, said equivalent electrical information comprises circuit node equivalent parasitic capacitances and circuit node equivalence conducting resistance.
4. method according to claim 3; It is characterized in that; Said circuit node equivalent parasitic capacitances is the existing stray capacitance sum of institute's wired network, comprises that promptly the device of said gauze is connected to the stray capacitance of said gauze and the stray capacitance between the said gauze interconnection line.
5. method according to claim 4 is characterized in that, the stray capacitance that the device of said gauze is connected to said gauze is according to suc as formula calculating shown in (2);
Cnet.n，exist，dev＝∑Cnet.n，exist，dev，i
(2)
Wherein,
i＝1，2，3，…，Nnet，n，dev_cnum；
Nnet, n, dev_cnum goes up the stray capacitance quantity that device causes for gauze n;
Cnet.n, exist, dev are the stray capacitance that the device of said gauze n is connected to said gauze.
6. method according to claim 4 is characterized in that, stray capacitance between the mutual interconnection line of said gauze is calculated according to suc as formula calculating shown in (3);
Cnet.n，exist，wire＝∑Cnet.n，exist，wire，i
(3)
Wherein,
i＝1，2，3，…，Nnet，n，wire_cnum；
Nnet, n, wire_cnum are that said gauze n goes up the stray capacitance quantity that interconnection line causes;
Cnet.n, exist, wir are the stray capacitance between the said gauze n interconnection line.
7. method according to claim 3 is characterized in that, the computing method of said circuit node equivalence conducting resistance comprise the steps:
A calculate power supply between the corresponding node of said gauze to the power supply equivalent resistance;
B calculates ground wire to the equivalent resistance over the ground between the corresponding node of gauze;
C said to power supply equivalent resistance and said equivalent resistance over the ground in, choose maximal value and be said circuit node equivalence conducting resistance.
8. method according to claim 1 is characterized in that, said gauze limit stray capacitance is by calculating as shown in the formula (4):
Cnet，n，extra_limit＝Tdealylimit，n/Ron-Cnet.n，exist
Wherein,
Tdealylimit, n are the time-delay limit of gauze n;
Ron is said gauze equivalence conducting resistance;
Cnet.n, exist are the equivalent parasitic capacitances of gauze n;
Cnet, n, extra_limit are the limit stray capacitance that the redundant mute metal filled gauze n of giving introduces.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106815380A (en) * | 2015-11-27 | 2017-06-09 | 中国科学院微电子研究所 | A kind of method and system for extracting dead resistance |
| CN106815379A (en) * | 2015-11-27 | 2017-06-09 | 中国科学院微电子研究所 | A kind of method and system for extracting parasitic capacitance |
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2011
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| 冯春阳: "《纳米集成电路化学机械抛光工艺建模与仿真及可制造性设计技术研究》", 30 November 2010 * |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106815380A (en) * | 2015-11-27 | 2017-06-09 | 中国科学院微电子研究所 | A kind of method and system for extracting dead resistance |
| CN106815379A (en) * | 2015-11-27 | 2017-06-09 | 中国科学院微电子研究所 | A kind of method and system for extracting parasitic capacitance |
| CN106815379B (en) * | 2015-11-27 | 2020-07-14 | 中国科学院微电子研究所 | Method and system for extracting parasitic capacitance |
| CN106815380B (en) * | 2015-11-27 | 2020-08-18 | 中国科学院微电子研究所 | Method and system for extracting parasitic resistance |
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